From nobody Thu Oct 2 09:19:03 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C4A7D1F4297; Fri, 19 Sep 2025 00:01:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758240092; cv=none; b=N7yC8t1iqei5tDP09tCdUMc+zDfCgHGQS9rbPZ5WCyFzn7koes0d3xjqAZ8DaPRZy6DNMI+EiPMG2bSoz7uzaEQFExgTUNzXOkAyos2lzv+FwnnVa47hLNUjvJ8wtItg6mgrT0efNREHRaiOJ8kyCaGImELbEMtaXegZVpKsTbI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758240092; c=relaxed/simple; bh=Tg1ld0C9aJV9Taesd/GOIbrFd9dLKzMX+uwTJypScp8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Yo3l14ivi6SQDQ3/aeqdXv+sR9x3zfEATTMjrFzLOQYzldAYzYCXPTjC+z1NZunWOD8GgXtt7KmTkg6JNkKiU10e/JH6udrauORVQP9ndPS6xpWxD22edd99C5dSRUxb6OWtgumAi1yLNlQ4F0GHY6Pov1Mlpq4N+VA67V6isoc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1148B1762; Thu, 18 Sep 2025 17:01:22 -0700 (PDT) Received: from minigeek.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 058443F673; Thu, 18 Sep 2025 17:01:27 -0700 (PDT) From: Andre Przywara To: Lee Jones , Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jernej Skrabec , Samuel Holland , Liam Girdwood , Mark Brown Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mikhail Kalashnikov Subject: [RFC PATCH 5/5] arm64: dts: allwinner: a523: Mark dual-phased regulators Date: Fri, 19 Sep 2025 01:00:20 +0100 Message-ID: <20250919000020.16969-6-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.4 In-Reply-To: <20250919000020.16969-1-andre.przywara@arm.com> References: <20250919000020.16969-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The X-Powers AXP323 PMIC on the boards with a SoC from the Allwinner A523 family typically uses DCDC1 and DCDC2 in a dual-phase setup to supply the "big" CPU cluster. For some reason this dual-phase configuration is not the PMIC's reset default, but needs to be actively programmed at runtime. Add the newly introduced x-powers,polyphased property in the board DTs, to mark this connection and let drivers program the dual-phase setup. Signed-off-by: Andre Przywara --- arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts | 5 ++++- arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts | 5 ++++- arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts | 5 ++++- arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts | 5 ++++- 4 files changed, 16 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch= /arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts index 4ad91b6f01d34..a51446482927c 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts @@ -269,9 +269,12 @@ reg_dcdc1_323: dcdc1 { regulator-min-microvolt =3D <900000>; regulator-max-microvolt =3D <1160000>; regulator-name =3D "vdd-cpub"; + x-powers,polyphased =3D <®_dcdc2_323>; }; =20 - /* DCDC2 is polyphased with DCDC1 */ + reg_dcdc2_323: dcdc2 { + /* dual-phased with DCDC1 */ + }; =20 /* RISC-V management core supply */ reg_dcdc3_323: dcdc3 { diff --git a/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts b/arch/= arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts index 68c5765c2e919..848b5abb4203f 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts @@ -285,9 +285,12 @@ reg_dcdc1_323: dcdc1 { regulator-min-microvolt =3D <900000>; regulator-max-microvolt =3D <1160000>; regulator-name =3D "vdd-cpub"; + x-powers,polyphased =3D <®_dcdc2_323>; }; =20 - /* DCDC2 is polyphased with DCDC1 */ + reg_dcdc2_323: dcdc2 { + /* dual-phased with DCDC1 */ + }; =20 reg_dcdc3_323: dcdc3 { regulator-always-on; diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch= /arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts index 7b7ef54ec7684..ec69b409ac47f 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -291,9 +291,12 @@ reg_dcdc1_323: dcdc1 { regulator-min-microvolt =3D <900000>; regulator-max-microvolt =3D <1160000>; regulator-name =3D "vdd-cpub"; + x-powers,polyphased =3D <®_dcdc2_323>; }; =20 - /* DCDC2 is polyphased with DCDC1 */ + reg_dcdc2_323: dcdc2 { + /* dual-phased with DCDC1 */ + }; =20 /* Some RISC-V management core related voltage */ reg_dcdc3_323: dcdc3 { diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/ar= ch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts index d07bb9193b438..e9e6d85fb84f7 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts @@ -322,9 +322,12 @@ reg_dcdc1_323: dcdc1 { regulator-min-microvolt =3D <900000>; regulator-max-microvolt =3D <1150000>; regulator-name =3D "vdd-cpub"; + x-powers,polyphased =3D <®_dcdc2_323>; }; =20 - /* DCDC2 is polyphased with DCDC1 */ + reg_dcdc2_323: dcdc2 { + /* dual-phased with DCDC1 */ + }; =20 /* Some RISC-V management core related voltage */ reg_dcdc3_323: dcdc3 { --=20 2.46.4