From nobody Thu Oct 2 09:19:05 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 246481EF39E; Fri, 19 Sep 2025 00:01:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758240089; cv=none; b=T8ad7ryAW07NZfTRWNMYuOxqbktNhTVBgZYuNifBO6hwS40BRY90XKuK2LhecEOAlXNgGj4L8uKkf1PYZVXhrW4XlTVkvw8KvVohKFs2TV3ZASTpHcgf2Y0ohfLinvVybzgc+0U8txK+Zj2zaaUiE1TD3dekHPvIDMo5CVZdIp8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758240089; c=relaxed/simple; bh=hWfeolTkLmLOZzrDK+LL+Wr5aDUFlhHnjGWW9bVTJ70=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oLZOthCu2ZkQ+2fU3xfzxkhn9t9AoMr8ML4PhJYzijeKXCDNpj56gz+Vj7slaI3eRUaFDa5c/Gf5DigsFVhickyU+qzeVPifpZ7UuUiRACIyp9dMPWweLLhhn2A5L7pxsmDSSOshVqJ5DQH/uP0qAcpk5Q9uwMQN9dQhF0Lo0/s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7F7C11762; Thu, 18 Sep 2025 17:01:19 -0700 (PDT) Received: from minigeek.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 760DB3F673; Thu, 18 Sep 2025 17:01:25 -0700 (PDT) From: Andre Przywara To: Lee Jones , Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jernej Skrabec , Samuel Holland , Liam Girdwood , Mark Brown Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mikhail Kalashnikov Subject: [RFC PATCH 4/5] mfd: axp20x: Support tri-phase setup Date: Fri, 19 Sep 2025 01:00:19 +0100 Message-ID: <20250919000020.16969-5-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.4 In-Reply-To: <20250919000020.16969-1-andre.przywara@arm.com> References: <20250919000020.16969-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Of the PMICs that support multi-phased regulators, all but one just support a dual-phase setup, with exactly two regulators tied together. This allows for a simple data model, since just two is somewhat of a special case. However there is the AXP806, which supports a triple-phase setup, that is also used on at least one board: the Cubieboard 4, where DCDC-A+B+C together supply the Cortex-A15 CPU cluster. Since this is just one case, and a fairly old one now, let's not boil the ocean by coming up with a complex data structure that allows describing arbitrary combinations, but instead handle this as a special case. This is supported by the fact, that the AXP806 only supports two specific setups: DCDC-A+B or DCDC-A+B+C, but nothing else. Add a function that checks for the regulators on this PMIC, and handle the two cases, plus the one without any poly-phasing. Signed-off-by: Andre Przywara Acked-by: Mark Brown --- drivers/regulator/axp20x-regulator.c | 45 ++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20= x-regulator.c index e3acc4635a0ed..9dd666f228b1e 100644 --- a/drivers/regulator/axp20x-regulator.c +++ b/drivers/regulator/axp20x-regulator.c @@ -1569,6 +1569,39 @@ static int axp20x_find_polyphased_reg(const struct r= egulator_desc *regs, return -ENODEV; } =20 +static int axp20x_handle_triphase(struct axp20x_dev *axp20x, + int reg1, int reg2, int reg3) +{ + if (axp20x->variant =3D=3D AXP806_ID && reg1 =3D=3D AXP806_DCDCA) { + /* no other regulator listed: single phase setup */ + if (reg2 =3D=3D -ENOENT && reg3 =3D=3D -ENOENT) { + regmap_update_bits(axp20x->regmap, + AXP806_DCDC_MODE_CTRL2, + AXP806_DCDCABC_POLYPHASE_MASK, 0); + return 0; + } + /* only regulator listed is DCDC-B: dual phase setup */ + if (reg2 =3D=3D AXP806_DCDCB && reg3 =3D=3D -ENOENT) { + regmap_update_bits(axp20x->regmap, + AXP806_DCDC_MODE_CTRL2, + AXP806_DCDCABC_POLYPHASE_MASK, + AXP806_DCDCAB_POLYPHASE_DUAL); + return 0; + } + /* both DCDC-B+C regulators listed: tri phase setup */ + if ((reg2 =3D=3D AXP806_DCDCB && reg3 =3D=3D AXP806_DCDCC) || + (reg2 =3D=3D AXP806_DCDCC && reg3 =3D=3D AXP806_DCDCB)) { + regmap_update_bits(axp20x->regmap, + AXP806_DCDC_MODE_CTRL2, + AXP806_DCDCABC_POLYPHASE_MASK, + AXP806_DCDCABC_POLYPHASE_TRI); + return 0; + } + } + + return 0; +} + static int axp20x_parse_polyphase(struct axp20x_dev *axp20x, int primary_r= eg_id, const struct regulator_desc *regs, int nregulators, const struct device_node *np) @@ -1610,6 +1643,18 @@ static int axp20x_parse_polyphase(struct axp20x_dev = *axp20x, int primary_reg_id, } } =20 + /* Special handling for the AXP806 DCDC-A/B/C tri-phase regulator. */ + if (axp20x->variant =3D=3D AXP806_ID && primary_reg_id =3D=3D AXP806_DCDC= A) { + int reg3_id; + + reg3_id =3D axp20x_find_polyphased_reg(regs, nregulators, np, 1); + if (reg3_id < 0 && reg3_id !=3D -ENOENT) + return reg_id; + + return axp20x_handle_triphase(axp20x, primary_reg_id, + reg_id, reg3_id); + } + return 0; } =20 --=20 2.46.4