From nobody Thu Oct 2 07:45:15 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C78E733F6; Fri, 19 Sep 2025 00:01:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758240083; cv=none; b=H5zb5wCciq/jL15jUvNIsMBmh7CDpXOV1LCMwBaghzu2s/YlzACHTKMrgfXq6M0nYFy2naqTEICJsG3HODLoo1JZ8sJoRvYUjmwhurD+bVVDV2HceABJyYqt6KvpdNwYD4yrKRRw/fGPo2cRAV0PBdy36vCrGNapAwP8piVhllQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758240083; c=relaxed/simple; bh=w1JZP16dHFAp2HzwYCVCO5AvFOMNfcErG9cWpNaZHRM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lsEYbJlipY/qTMoFYrWuYQtsNcoUD0OfTwUzRi/f17IOSnQbsxMv5ZJA2dpbE194IB2QUjzUxYRwqqcDHWAFK93utnWZfYx9GeG9z3I3Qj9BxpuqrbPPg4ZPxFi/Jhdaoj5nW7TMdIlDrWFtiKYiRVYCeQAseO4gleQZqb54R5M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CF0FD1764; Thu, 18 Sep 2025 17:01:11 -0700 (PDT) Received: from minigeek.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C2AD83F673; Thu, 18 Sep 2025 17:01:17 -0700 (PDT) From: Andre Przywara To: Lee Jones , Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jernej Skrabec , Samuel Holland , Liam Girdwood , Mark Brown Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mikhail Kalashnikov Subject: [RFC PATCH 1/5] dt-bindings: mfd: x-powers,axp152: Add polyphased property Date: Fri, 19 Sep 2025 01:00:16 +0100 Message-ID: <20250919000020.16969-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.4 In-Reply-To: <20250919000020.16969-1-andre.przywara@arm.com> References: <20250919000020.16969-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some X-Powers AXP PMICs can combine some of their DC/DC buck converter outputs in a multi-phase fashion, to achieve higher currents and decrease the output ripple. The datasheets call this poly-phase. This is programmable in the PMIC, although often set up as the PMIC's reset default. Add the "x-powers,polyphased" property to the binding, to describe those pairs or tuples of regulators that should work together. In the lead regulator node, the property lists the phandles of the connected regulators. Just an empty property means no poly-phasing. Signed-off-by: Andre Przywara --- .../devicetree/bindings/mfd/x-powers,axp152.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml b/D= ocumentation/devicetree/bindings/mfd/x-powers,axp152.yaml index 45f015d63df16..260c4c0afc475 100644 --- a/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml +++ b/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml @@ -304,6 +304,15 @@ properties: noise. This probably makes sense for HiFi audio related applications that aren't battery constrained. =20 + x-powers,polyphased: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + A list of phandles pointing to other regulators that should = be + polyphased with this regulator. The linked regulators will be + synchronised with this regulator, within the PMIC, but only = if + supported by the PMIC. An empty list means this regulator + should be configured in a single-phase setup. + additionalProperties: false =20 required: @@ -377,6 +386,7 @@ examples: regulator-min-microvolt =3D <1000000>; regulator-max-microvolt =3D <1450000>; regulator-name =3D "vdd-cpu"; + x-powers,polyphased =3D <®_dcdc4>; }; =20 reg_dcdc3: dcdc3 { @@ -386,6 +396,10 @@ examples: regulator-name =3D "vdd-int-dll"; }; =20 + reg_dcdc4: dcdc4 { + /* dual-phased with DCDC2 */ + }; + reg_ldo1: ldo1 { /* LDO1 is a fixed output regulator */ regulator-always-on; --=20 2.46.4 From nobody Thu Oct 2 07:45:15 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 23DBA3987D; Fri, 19 Sep 2025 00:01:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758240085; cv=none; b=eQ8b8zwKojF9aXiNwrbcHnrj/YqEjH/1E2ql2EuUJn04QnoMWK7VSPNprKGDv1Tfk9KzQ33d3kpWuwrwknIO7qmviOj/DA7fMxJn9zAwaaPbU7ecrwXyW38N0Eem2tFHEviUIrNtRccO10BJXN2gsdOKHnukaCRFlIvDzPmHW3s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758240085; c=relaxed/simple; bh=AGLpL8ozHA74H8FAdvO2M1aEr9vo4KPtCeJmMIG6cpc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rSYNPUIYGBqdAhF1NSNP7JEMKw+OIjuXCp4p4UWZymvf0rp3AonZDXz1JMeXy7gQFUgUQWWhofG/3SKAhReR7OeVK3BqSHgwId+9yxWF5d+7IwicBG8FW9nDLY+wVcDtJDRTApYbkQWaWwoG3BonQrjjiZS/PiUlP+3WD+jwqa4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5D3A11762; Thu, 18 Sep 2025 17:01:14 -0700 (PDT) Received: from minigeek.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 51FE83F673; Thu, 18 Sep 2025 17:01:20 -0700 (PDT) From: Andre Przywara To: Lee Jones , Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jernej Skrabec , Samuel Holland , Liam Girdwood , Mark Brown Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mikhail Kalashnikov Subject: [RFC PATCH 2/5] mfd: axp20x: Refactor axp20x_is_polyphase_slave() Date: Fri, 19 Sep 2025 01:00:17 +0100 Message-ID: <20250919000020.16969-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.4 In-Reply-To: <20250919000020.16969-1-andre.przywara@arm.com> References: <20250919000020.16969-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some X-Powers AXP PMICs allow to combine certain DC/DC rails together in a multi-phase fashion. So far we don't actively program those connections, but we detect the existing setup, and prevent the connected regulators from being re-programmed or turned off. At the moment this is done in a switch/case construct, listing the known regulator pairs for those PMICs supported. To get rid of this ever growing code section, create a data structure that describes the relationship, and have generic code that iterates over the entries and checks for matches. This not only cleans that function up and makes extensions much simpler, but also allows to reuse this information for the upcoming programming of those poly-phase setups. Signed-off-by: Andre Przywara --- drivers/regulator/axp20x-regulator.c | 91 ++++++++++++++-------------- 1 file changed, 45 insertions(+), 46 deletions(-) diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20= x-regulator.c index da891415efc0b..19c9a98d1835a 100644 --- a/drivers/regulator/axp20x-regulator.c +++ b/drivers/regulator/axp20x-regulator.c @@ -1481,70 +1481,69 @@ static int axp20x_set_dcdc_workmode(struct regulato= r_dev *rdev, int id, u32 work return regmap_update_bits(rdev->regmap, reg, mask, workmode); } =20 +struct dualphase_regulator { + int axp_id; + int reg1, reg2; + unsigned int polyphase_reg; + unsigned int bitmask; +} dualphase_regulators[] =3D { + { AXP323_ID, AXP313A_DCDC1, AXP313A_DCDC2, + AXP323_DCDC_MODE_CTRL2, BIT(1), }, + { AXP803_ID, AXP803_DCDC2, AXP803_DCDC3, AXP803_POLYPHASE_CTRL, + AXP803_DCDC23_POLYPHASE_DUAL, }, + { AXP803_ID, AXP803_DCDC5, AXP803_DCDC6, AXP803_POLYPHASE_CTRL, + AXP803_DCDC56_POLYPHASE_DUAL, }, + /* AXP806's DCDC-A/B/C is a tri-phase regulator */ + { AXP806_ID, AXP806_DCDCD, AXP806_DCDCE, AXP806_DCDC_MODE_CTRL2, + AXP806_DCDCDE_POLYPHASE_DUAL, }, + { AXP813_ID, AXP803_DCDC2, AXP803_DCDC3, AXP803_POLYPHASE_CTRL, + AXP803_DCDC23_POLYPHASE_DUAL, }, + { AXP813_ID, AXP803_DCDC5, AXP803_DCDC6, AXP803_POLYPHASE_CTRL, + AXP803_DCDC56_POLYPHASE_DUAL, }, + { AXP15060_ID, AXP15060_DCDC2, AXP15060_DCDC3, AXP15060_DCDC_MODE_CTRL1, + AXP15060_DCDC23_POLYPHASE_DUAL_MASK, }, + { AXP15060_ID, AXP15060_DCDC4, AXP15060_DCDC6, AXP15060_DCDC_MODE_CTRL1, + AXP15060_DCDC46_POLYPHASE_DUAL_MASK, }, +}; + /* * This function checks whether a regulator is part of a poly-phase * output setup based on the registers settings. Returns true if it is. */ static bool axp20x_is_polyphase_slave(struct axp20x_dev *axp20x, int id) { + struct dualphase_regulator *dpreg; u32 reg =3D 0; + int i; =20 - /* - * Currently in our supported AXP variants, only AXP803, AXP806, - * AXP813 and AXP15060 have polyphase regulators. - */ - switch (axp20x->variant) { - case AXP803_ID: - case AXP813_ID: - regmap_read(axp20x->regmap, AXP803_POLYPHASE_CTRL, ®); + for (i =3D 0; i < ARRAY_SIZE(dualphase_regulators); i++) { + dpreg =3D &dualphase_regulators[i]; =20 - switch (id) { - case AXP803_DCDC3: - return !!(reg & AXP803_DCDC23_POLYPHASE_DUAL); - case AXP803_DCDC6: - return !!(reg & AXP803_DCDC56_POLYPHASE_DUAL); + if (axp20x->variant !=3D dpreg->axp_id) + continue; + /* Is this the second regulator from a dual-phase pair? */ + if (id =3D=3D dpreg->reg2) { + regmap_read(axp20x->regmap, dpreg->polyphase_reg, ®); + + return !!(reg & dpreg->bitmask); } - break; + } =20 - case AXP806_ID: + /* + * DCDC-A/B/C can be configured either as a dual-phase (A+B) or + * as a triple-phase regulator (A+B+C), but not in any other + * combination. Treat this as a special case here. + */ + if (axp20x->variant =3D=3D AXP806_ID) { regmap_read(axp20x->regmap, AXP806_DCDC_MODE_CTRL2, ®); - - switch (id) { - case AXP806_DCDCB: + if (id =3D=3D AXP806_DCDCB) return (((reg & AXP806_DCDCABC_POLYPHASE_MASK) =3D=3D AXP806_DCDCAB_POLYPHASE_DUAL) || ((reg & AXP806_DCDCABC_POLYPHASE_MASK) =3D=3D AXP806_DCDCABC_POLYPHASE_TRI)); - case AXP806_DCDCC: + if (id =3D=3D AXP806_DCDCC) return ((reg & AXP806_DCDCABC_POLYPHASE_MASK) =3D=3D AXP806_DCDCABC_POLYPHASE_TRI); - case AXP806_DCDCE: - return !!(reg & AXP806_DCDCDE_POLYPHASE_DUAL); - } - break; - - case AXP15060_ID: - regmap_read(axp20x->regmap, AXP15060_DCDC_MODE_CTRL1, ®); - - switch (id) { - case AXP15060_DCDC3: - return !!(reg & AXP15060_DCDC23_POLYPHASE_DUAL_MASK); - case AXP15060_DCDC6: - return !!(reg & AXP15060_DCDC46_POLYPHASE_DUAL_MASK); - } - break; - - case AXP323_ID: - regmap_read(axp20x->regmap, AXP323_DCDC_MODE_CTRL2, ®); - - switch (id) { - case AXP313A_DCDC2: - return !!(reg & BIT(1)); - } - break; - - default: - return false; } =20 return false; --=20 2.46.4 From nobody Thu Oct 2 07:45:15 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C24924A01; Fri, 19 Sep 2025 00:01:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758240087; cv=none; b=VaqzNvQPm94/Tg4XdSpQlGfloFPRQDnXtRMayI7OMP2DAJjBWdYJ8NZm0G5bQjYvNa1Lm417hQU66aaiWZfHh7lHDvVogMbi68jBTfDnpvl3Wxx+LzttCj+bnkMjAVoJgniHB98E5divdTWb3dJippaXeavSvs/1DCJ056gjZKc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758240087; c=relaxed/simple; bh=cdIxo26J50n61tBpp0c4Fy/shWP6orIMRcVXxPYBqAI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Dm/INOk649gFqupJL070EKJaJiDptXT7DCbGNJbaQKa1nIKPqW56NFXhci5VdaSlKh7q0el65A6MU80Ua2t7rZQGbgOwfYXQLQ3CutlNyAcoqJ6try+1P8sKLSg1v0R0DVOSqxvAPNH5G0b3aL6a/DErvr61UKNpdziUnm8DXb4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F191A1764; Thu, 18 Sep 2025 17:01:16 -0700 (PDT) Received: from minigeek.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D5E343F673; Thu, 18 Sep 2025 17:01:22 -0700 (PDT) From: Andre Przywara To: Lee Jones , Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jernej Skrabec , Samuel Holland , Liam Girdwood , Mark Brown Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mikhail Kalashnikov Subject: [RFC PATCH 3/5] mfd: axp20x: Allow programming dual-phase regulator pairs Date: Fri, 19 Sep 2025 01:00:18 +0100 Message-ID: <20250919000020.16969-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.4 In-Reply-To: <20250919000020.16969-1-andre.przywara@arm.com> References: <20250919000020.16969-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some X-Powers AXP PMICs allow to combine certain DC/DC rails together in a multi-phase fashion. So far we don't actively program those connections, since the PMIC reset default for the multi-phasing setup was always correct for the existing boards. Now a new set of boards appeared where the reset default is not correct, so we need to actively program the multi-phase setup. Use the new data structure describing the dual-phased regulators, and the new "x-powers,polyphased" DT property to enable or disable the dual-phase setup on the PMICs that support it. This works by checking how many regulators this DT property list: - If it's none, this means any existing poly-phase setup should be broken up. - If the property references at least one other regulator, we can use our dual-phase regulator table to find the register and bitmask required to establish the dual-phase connection. This supports only dual-phased regulator pairs so far, but we will somewhat paper ov^W^W fix this in the next patch. Signed-off-by: Andre Przywara --- drivers/regulator/axp20x-regulator.c | 68 ++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20= x-regulator.c index 19c9a98d1835a..e3acc4635a0ed 100644 --- a/drivers/regulator/axp20x-regulator.c +++ b/drivers/regulator/axp20x-regulator.c @@ -1549,6 +1549,70 @@ static bool axp20x_is_polyphase_slave(struct axp20x_= dev *axp20x, int id) return false; } =20 +static int axp20x_find_polyphased_reg(const struct regulator_desc *regs, + int nregulators, + const struct device_node *np, int index) +{ + struct of_phandle_args args; + int ret, i; + + ret =3D of_parse_phandle_with_fixed_args(np, "x-powers,polyphased", + 0, index, &args); + if (ret) + return ret; + + for (i =3D 0; i < nregulators; i++) { + if (!strcmp(regs[i].name, args.np->name)) + return i; + } + + return -ENODEV; +} + +static int axp20x_parse_polyphase(struct axp20x_dev *axp20x, int primary_r= eg_id, + const struct regulator_desc *regs, + int nregulators, const struct device_node *np) +{ + struct dualphase_regulator *dpreg; + int reg_id, i; + + if (!of_property_present(np, "x-powers,polyphased")) + return 0; + + reg_id =3D axp20x_find_polyphased_reg(regs, nregulators, np, 0); + if (reg_id < 0 && reg_id !=3D -ENOENT) /* not just empty property */ + return reg_id; + + for (i =3D 0; i < ARRAY_SIZE(dualphase_regulators); i++) { + dpreg =3D &dualphase_regulators[i]; + + if (axp20x->variant !=3D dpreg->axp_id) + continue; + + if (dpreg->reg1 !=3D primary_reg_id && + dpreg->reg2 !=3D primary_reg_id) + continue; + + /* Empty property means breaking any polyphase setup. */ + if (reg_id =3D=3D -ENOENT) { + regmap_update_bits(axp20x->regmap, dpreg->polyphase_reg, + dpreg->bitmask, 0); + + return 0; + } + + if ((dpreg->reg1 =3D=3D primary_reg_id && dpreg->reg2 =3D=3D reg_id) || + (dpreg->reg2 =3D=3D primary_reg_id && dpreg->reg1 =3D=3D reg_id)) { + regmap_update_bits(axp20x->regmap, dpreg->polyphase_reg, + dpreg->bitmask, dpreg->bitmask); + + return 0; + } + } + + return 0; +} + static int axp20x_regulator_probe(struct platform_device *pdev) { struct regulator_dev *rdev; @@ -1703,6 +1767,10 @@ static int axp20x_regulator_probe(struct platform_de= vice *pdev) rdev->desc->name); } =20 + if (rdev->dev.of_node) + axp20x_parse_polyphase(axp20x, i, regulators, + nregulators, rdev->dev.of_node); + /* * Save AXP22X DCDC1 / DCDC5 / AXP15060 ALDO1 regulator names for later. */ --=20 2.46.4 From nobody Thu Oct 2 07:45:15 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 246481EF39E; Fri, 19 Sep 2025 00:01:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758240089; cv=none; b=T8ad7ryAW07NZfTRWNMYuOxqbktNhTVBgZYuNifBO6hwS40BRY90XKuK2LhecEOAlXNgGj4L8uKkf1PYZVXhrW4XlTVkvw8KvVohKFs2TV3ZASTpHcgf2Y0ohfLinvVybzgc+0U8txK+Zj2zaaUiE1TD3dekHPvIDMo5CVZdIp8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758240089; c=relaxed/simple; bh=hWfeolTkLmLOZzrDK+LL+Wr5aDUFlhHnjGWW9bVTJ70=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oLZOthCu2ZkQ+2fU3xfzxkhn9t9AoMr8ML4PhJYzijeKXCDNpj56gz+Vj7slaI3eRUaFDa5c/Gf5DigsFVhickyU+qzeVPifpZ7UuUiRACIyp9dMPWweLLhhn2A5L7pxsmDSSOshVqJ5DQH/uP0qAcpk5Q9uwMQN9dQhF0Lo0/s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7F7C11762; Thu, 18 Sep 2025 17:01:19 -0700 (PDT) Received: from minigeek.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 760DB3F673; Thu, 18 Sep 2025 17:01:25 -0700 (PDT) From: Andre Przywara To: Lee Jones , Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jernej Skrabec , Samuel Holland , Liam Girdwood , Mark Brown Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mikhail Kalashnikov Subject: [RFC PATCH 4/5] mfd: axp20x: Support tri-phase setup Date: Fri, 19 Sep 2025 01:00:19 +0100 Message-ID: <20250919000020.16969-5-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.4 In-Reply-To: <20250919000020.16969-1-andre.przywara@arm.com> References: <20250919000020.16969-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Of the PMICs that support multi-phased regulators, all but one just support a dual-phase setup, with exactly two regulators tied together. This allows for a simple data model, since just two is somewhat of a special case. However there is the AXP806, which supports a triple-phase setup, that is also used on at least one board: the Cubieboard 4, where DCDC-A+B+C together supply the Cortex-A15 CPU cluster. Since this is just one case, and a fairly old one now, let's not boil the ocean by coming up with a complex data structure that allows describing arbitrary combinations, but instead handle this as a special case. This is supported by the fact, that the AXP806 only supports two specific setups: DCDC-A+B or DCDC-A+B+C, but nothing else. Add a function that checks for the regulators on this PMIC, and handle the two cases, plus the one without any poly-phasing. Signed-off-by: Andre Przywara Acked-by: Mark Brown --- drivers/regulator/axp20x-regulator.c | 45 ++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20= x-regulator.c index e3acc4635a0ed..9dd666f228b1e 100644 --- a/drivers/regulator/axp20x-regulator.c +++ b/drivers/regulator/axp20x-regulator.c @@ -1569,6 +1569,39 @@ static int axp20x_find_polyphased_reg(const struct r= egulator_desc *regs, return -ENODEV; } =20 +static int axp20x_handle_triphase(struct axp20x_dev *axp20x, + int reg1, int reg2, int reg3) +{ + if (axp20x->variant =3D=3D AXP806_ID && reg1 =3D=3D AXP806_DCDCA) { + /* no other regulator listed: single phase setup */ + if (reg2 =3D=3D -ENOENT && reg3 =3D=3D -ENOENT) { + regmap_update_bits(axp20x->regmap, + AXP806_DCDC_MODE_CTRL2, + AXP806_DCDCABC_POLYPHASE_MASK, 0); + return 0; + } + /* only regulator listed is DCDC-B: dual phase setup */ + if (reg2 =3D=3D AXP806_DCDCB && reg3 =3D=3D -ENOENT) { + regmap_update_bits(axp20x->regmap, + AXP806_DCDC_MODE_CTRL2, + AXP806_DCDCABC_POLYPHASE_MASK, + AXP806_DCDCAB_POLYPHASE_DUAL); + return 0; + } + /* both DCDC-B+C regulators listed: tri phase setup */ + if ((reg2 =3D=3D AXP806_DCDCB && reg3 =3D=3D AXP806_DCDCC) || + (reg2 =3D=3D AXP806_DCDCC && reg3 =3D=3D AXP806_DCDCB)) { + regmap_update_bits(axp20x->regmap, + AXP806_DCDC_MODE_CTRL2, + AXP806_DCDCABC_POLYPHASE_MASK, + AXP806_DCDCABC_POLYPHASE_TRI); + return 0; + } + } + + return 0; +} + static int axp20x_parse_polyphase(struct axp20x_dev *axp20x, int primary_r= eg_id, const struct regulator_desc *regs, int nregulators, const struct device_node *np) @@ -1610,6 +1643,18 @@ static int axp20x_parse_polyphase(struct axp20x_dev = *axp20x, int primary_reg_id, } } =20 + /* Special handling for the AXP806 DCDC-A/B/C tri-phase regulator. */ + if (axp20x->variant =3D=3D AXP806_ID && primary_reg_id =3D=3D AXP806_DCDC= A) { + int reg3_id; + + reg3_id =3D axp20x_find_polyphased_reg(regs, nregulators, np, 1); + if (reg3_id < 0 && reg3_id !=3D -ENOENT) + return reg_id; + + return axp20x_handle_triphase(axp20x, primary_reg_id, + reg_id, reg3_id); + } + return 0; } =20 --=20 2.46.4 From nobody Thu Oct 2 07:45:15 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C4A7D1F4297; Fri, 19 Sep 2025 00:01:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758240092; cv=none; b=N7yC8t1iqei5tDP09tCdUMc+zDfCgHGQS9rbPZ5WCyFzn7koes0d3xjqAZ8DaPRZy6DNMI+EiPMG2bSoz7uzaEQFExgTUNzXOkAyos2lzv+FwnnVa47hLNUjvJ8wtItg6mgrT0efNREHRaiOJ8kyCaGImELbEMtaXegZVpKsTbI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758240092; c=relaxed/simple; bh=Tg1ld0C9aJV9Taesd/GOIbrFd9dLKzMX+uwTJypScp8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Yo3l14ivi6SQDQ3/aeqdXv+sR9x3zfEATTMjrFzLOQYzldAYzYCXPTjC+z1NZunWOD8GgXtt7KmTkg6JNkKiU10e/JH6udrauORVQP9ndPS6xpWxD22edd99C5dSRUxb6OWtgumAi1yLNlQ4F0GHY6Pov1Mlpq4N+VA67V6isoc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1148B1762; Thu, 18 Sep 2025 17:01:22 -0700 (PDT) Received: from minigeek.fritz.box (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 058443F673; Thu, 18 Sep 2025 17:01:27 -0700 (PDT) From: Andre Przywara To: Lee Jones , Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jernej Skrabec , Samuel Holland , Liam Girdwood , Mark Brown Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mikhail Kalashnikov Subject: [RFC PATCH 5/5] arm64: dts: allwinner: a523: Mark dual-phased regulators Date: Fri, 19 Sep 2025 01:00:20 +0100 Message-ID: <20250919000020.16969-6-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.4 In-Reply-To: <20250919000020.16969-1-andre.przywara@arm.com> References: <20250919000020.16969-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The X-Powers AXP323 PMIC on the boards with a SoC from the Allwinner A523 family typically uses DCDC1 and DCDC2 in a dual-phase setup to supply the "big" CPU cluster. For some reason this dual-phase configuration is not the PMIC's reset default, but needs to be actively programmed at runtime. Add the newly introduced x-powers,polyphased property in the board DTs, to mark this connection and let drivers program the dual-phase setup. Signed-off-by: Andre Przywara --- arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts | 5 ++++- arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts | 5 ++++- arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts | 5 ++++- arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts | 5 ++++- 4 files changed, 16 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch= /arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts index 4ad91b6f01d34..a51446482927c 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts @@ -269,9 +269,12 @@ reg_dcdc1_323: dcdc1 { regulator-min-microvolt =3D <900000>; regulator-max-microvolt =3D <1160000>; regulator-name =3D "vdd-cpub"; + x-powers,polyphased =3D <®_dcdc2_323>; }; =20 - /* DCDC2 is polyphased with DCDC1 */ + reg_dcdc2_323: dcdc2 { + /* dual-phased with DCDC1 */ + }; =20 /* RISC-V management core supply */ reg_dcdc3_323: dcdc3 { diff --git a/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts b/arch/= arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts index 68c5765c2e919..848b5abb4203f 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts @@ -285,9 +285,12 @@ reg_dcdc1_323: dcdc1 { regulator-min-microvolt =3D <900000>; regulator-max-microvolt =3D <1160000>; regulator-name =3D "vdd-cpub"; + x-powers,polyphased =3D <®_dcdc2_323>; }; =20 - /* DCDC2 is polyphased with DCDC1 */ + reg_dcdc2_323: dcdc2 { + /* dual-phased with DCDC1 */ + }; =20 reg_dcdc3_323: dcdc3 { regulator-always-on; diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch= /arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts index 7b7ef54ec7684..ec69b409ac47f 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -291,9 +291,12 @@ reg_dcdc1_323: dcdc1 { regulator-min-microvolt =3D <900000>; regulator-max-microvolt =3D <1160000>; regulator-name =3D "vdd-cpub"; + x-powers,polyphased =3D <®_dcdc2_323>; }; =20 - /* DCDC2 is polyphased with DCDC1 */ + reg_dcdc2_323: dcdc2 { + /* dual-phased with DCDC1 */ + }; =20 /* Some RISC-V management core related voltage */ reg_dcdc3_323: dcdc3 { diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/ar= ch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts index d07bb9193b438..e9e6d85fb84f7 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts @@ -322,9 +322,12 @@ reg_dcdc1_323: dcdc1 { regulator-min-microvolt =3D <900000>; regulator-max-microvolt =3D <1150000>; regulator-name =3D "vdd-cpub"; + x-powers,polyphased =3D <®_dcdc2_323>; }; =20 - /* DCDC2 is polyphased with DCDC1 */ + reg_dcdc2_323: dcdc2 { + /* dual-phased with DCDC1 */ + }; =20 /* Some RISC-V management core related voltage */ reg_dcdc3_323: dcdc3 { --=20 2.46.4