From nobody Thu Oct 2 09:22:04 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC97B2D97BF; Thu, 18 Sep 2025 18:49:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758221398; cv=none; b=LR5sd+PrL5hY+JA+Mij/g9/NTSxx8P4Akjj/Q62E8DO0x+T3tHLvAmceodW+/JyW0L3YgisDAi9FXefUscg17zhDN2wIJevajMbr8YvURbrCJbMqosKKZ/AHmXZkyksTQKW9S3Mqh9Ep9On8DpZz5sCi4x1vOhaqmsAd415ZSfw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758221398; c=relaxed/simple; bh=65t1RPp0ka+Y5SQw4gZNb7wOM4Xg/4h5FQ+MMy0If5o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=i2TMGQu5fA8CBSMpvZaC+bFTmeaoE0MZtOt8576sOO6FcvnyxYEPJw09Zyz/vH6lVkWRdhFolP0T9uGlJ7QpTfLtkiTF8g55b860SmYsPGhv61ZHl4jFA60poqUNICQXvMLBnXIa0AZ2VMlIrx6oOn5zhXbC4VtP+4EhpIhvbr0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cPYRYtUx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cPYRYtUx" Received: by smtp.kernel.org (Postfix) with ESMTPS id 800EFC19421; Thu, 18 Sep 2025 18:49:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758221398; bh=65t1RPp0ka+Y5SQw4gZNb7wOM4Xg/4h5FQ+MMy0If5o=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=cPYRYtUxsRVr9TyEYjCtAQTqYPvJrV1iY9MI6vrjRkwS/ofN48fRnHmKGT2MPRLOX 8+G8kJGwfWV4aaqZnUoR79jTLrXH9wC3uNTdABh5TW2aLaa1hdcmPX2502qAaqlz1y KOZ4/9SR648YUuTRIkWyrCHqwwTKxIs/64TmBhMQOZfJx9NcvHvvuxZjNYdeaumcc9 RRm9kTWVHnUIwBEbKBQ07vlUQTmpUSg4+1i7RBP8RWQ15G2U/9Ho+8wToWa+iTo9Yj 7yYZbXR7dGaRGMHGVEcAa21cE7q7XAzRSdVvHWnUXimqBTPu8bz1v9tJLeBjYUnJO1 bOCeMGi+vT0aA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76D83CA1013; Thu, 18 Sep 2025 18:49:58 +0000 (UTC) From: Dang Huynh via B4 Relay Date: Fri, 19 Sep 2025 01:48:50 +0700 Subject: [PATCH 10/10] ARM: dts: unisoc: rda8810pl: Add SDMMC controllers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250919-rda8810pl-mmc-v1-10-d4f08a05ba4d@mainlining.org> References: <20250919-rda8810pl-mmc-v1-0-d4f08a05ba4d@mainlining.org> In-Reply-To: <20250919-rda8810pl-mmc-v1-0-d4f08a05ba4d@mainlining.org> To: Manivannan Sadhasivam , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Vinod Koul , Ulf Hansson , Philipp Zabel , Kees Cook , "Gustavo A. R. Silva" Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, linux-hardening@vger.kernel.org, Dang Huynh X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758221395; l=5720; i=dang.huynh@mainlining.org; s=20250917; h=from:subject:message-id; bh=zi1lBIjsLiJ+MvStlhu52N5g0U+YipGaIL9gPvgvEPE=; b=l77vToHDcYswIc8WztAJWYO/+3IYOVrmTQlZnFRvjc0lKarYC0h4XR0hoxgA2q3ZB98uFJham quoNd+aQB2RCTuhZ8oSMEutdqzVeCxtTOtcZpguuNT9Z4JHuV24Oxly X-Developer-Key: i=dang.huynh@mainlining.org; a=ed25519; pk=RyzH4CL4YU/ItXYUurA51EVBidfx4lIy8/E4EKRJCUk= X-Endpoint-Received: by B4 Relay for dang.huynh@mainlining.org/20250917 with auth_id=526 X-Original-From: Dang Huynh Reply-To: dang.huynh@mainlining.org From: Dang Huynh Add SDMMC1 and 2 controllers for the RDA8810PL platform and enable it on the Orange Pi i96 and 2G-IOT. Signed-off-by: Dang Huynh --- .../boot/dts/unisoc/rda8810pl-orangepi-2g-iot.dts | 20 +++++++++ .../arm/boot/dts/unisoc/rda8810pl-orangepi-i96.dts | 20 +++++++++ arch/arm/boot/dts/unisoc/rda8810pl.dtsi | 47 ++++++++++++++++++= ++-- 3 files changed, 83 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/unisoc/rda8810pl-orangepi-2g-iot.dts b/arch/= arm/boot/dts/unisoc/rda8810pl-orangepi-2g-iot.dts index 98e34248ae80b1fcd673ff01fe045db412d5bcc9..b462057ec0d1eb1877eb770afa6= aced99efd84b7 100644 --- a/arch/arm/boot/dts/unisoc/rda8810pl-orangepi-2g-iot.dts +++ b/arch/arm/boot/dts/unisoc/rda8810pl-orangepi-2g-iot.dts @@ -6,6 +6,7 @@ =20 /dts-v1/; =20 +#include #include "rda8810pl.dtsi" =20 / { @@ -27,6 +28,13 @@ memory@80000000 { reg =3D <0x80000000 0x10000000>; }; =20 + vdd_sdmmc: regulator-fixed { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_sdmmc"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + }; + uart_clk: uart-clk { compatible =3D "fixed-clock"; clock-frequency =3D <921600>; @@ -34,6 +42,18 @@ uart_clk: uart-clk { }; }; =20 +&mmc1 { + status =3D "okay"; + no-sdio; + no-mmc; + bus-width =3D <4>; + max-frequency =3D <30000000>; + cd-gpios =3D <&gpiob 4 GPIO_ACTIVE_LOW>; + vmmc-supply =3D <&vdd_sdmmc>; + rda,mclk-adj =3D /bits/ 8 <1>; + rda,mclk-inv; +}; + &uart1 { status =3D "okay"; clocks =3D <&uart_clk>; diff --git a/arch/arm/boot/dts/unisoc/rda8810pl-orangepi-i96.dts b/arch/arm= /boot/dts/unisoc/rda8810pl-orangepi-i96.dts index 728f76931b995fdfc036b586f899b15a7f07528b..cf4b75f114b33b27fad0ead4951= b15abb1f5cabd 100644 --- a/arch/arm/boot/dts/unisoc/rda8810pl-orangepi-i96.dts +++ b/arch/arm/boot/dts/unisoc/rda8810pl-orangepi-i96.dts @@ -6,6 +6,7 @@ =20 /dts-v1/; =20 +#include #include "rda8810pl.dtsi" =20 / { @@ -27,6 +28,13 @@ memory@80000000 { reg =3D <0x80000000 0x10000000>; }; =20 + vdd_sdmmc: regulator-fixed { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_sdmmc"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + }; + uart_clk: uart-clk { compatible =3D "fixed-clock"; clock-frequency =3D <921600>; @@ -34,6 +42,18 @@ uart_clk: uart-clk { }; }; =20 +&mmc1 { + status =3D "okay"; + no-sdio; + no-mmc; + bus-width =3D <4>; + max-frequency =3D <30000000>; + cd-gpios =3D <&gpiob 4 GPIO_ACTIVE_LOW>; + vmmc-supply =3D <&vdd_sdmmc>; + rda,mclk-adj =3D /bits/ 8 <1>; + rda,mclk-inv; +}; + &uart1 { status =3D "okay"; clocks =3D <&uart_clk>; diff --git a/arch/arm/boot/dts/unisoc/rda8810pl.dtsi b/arch/arm/boot/dts/un= isoc/rda8810pl.dtsi index f30d6ece49fb33d9c5c3ad9522c83bb8e4f8b488..438be79a89060655e4a12edc6d3= c42574748108b 100644 --- a/arch/arm/boot/dts/unisoc/rda8810pl.dtsi +++ b/arch/arm/boot/dts/unisoc/rda8810pl.dtsi @@ -7,6 +7,8 @@ */ =20 #include +#include +#include =20 / { compatible =3D "rda,8810pl"; @@ -39,7 +41,7 @@ modem@10000000 { #size-cells =3D <1>; ranges =3D <0x0 0x10000000 0xfffffff>; =20 - gpioc@1a08000 { + gpioc: gpioc@1a08000 { compatible =3D "rda,8810pl-gpio"; reg =3D <0x1a08000 0x1000>; gpio-controller; @@ -68,6 +70,13 @@ apb@20900000 { #size-cells =3D <1>; ranges =3D <0x0 0x20900000 0x100000>; =20 + ap_syscon: syscon@0 { + compatible =3D "rda,8810pl-apsyscon", "syscon"; + reg =3D <0x0 0x1000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + timer@10000 { compatible =3D "rda,8810pl-timer"; reg =3D <0x10000 0x1000>; @@ -76,7 +85,7 @@ timer@10000 { interrupt-names =3D "hwtimer", "ostimer"; }; =20 - gpioa@30000 { + gpioa: gpioa@30000 { compatible =3D "rda,8810pl-gpio"; reg =3D <0x30000 0x1000>; gpio-controller; @@ -87,7 +96,7 @@ gpioa@30000 { interrupts =3D <12 IRQ_TYPE_LEVEL_HIGH>; }; =20 - gpiob@31000 { + gpiob: gpiob@31000 { compatible =3D "rda,8810pl-gpio"; reg =3D <0x31000 0x1000>; gpio-controller; @@ -98,7 +107,7 @@ gpiob@31000 { interrupts =3D <13 IRQ_TYPE_LEVEL_HIGH>; }; =20 - gpiod@32000 { + gpiod: gpiod@32000 { compatible =3D "rda,8810pl-gpio"; reg =3D <0x32000 0x1000>; gpio-controller; @@ -123,6 +132,30 @@ uart1: serial@0 { status =3D "disabled"; }; =20 + mmc1: mmc@50000 { + compatible =3D "rda,8810pl-mmc", "rda,mmc"; + reg =3D <0x50000 0x1000>; + interrupts =3D <3 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ap_syscon CLK_APB2>; + clock-names =3D "mclk"; + resets =3D <&ap_syscon RST_APB2_SDMMC1>; + dmas =3D <&ifc IFC_SDMMC1_TX>, <&ifc IFC_SDMMC1_RX>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + mmc2: mmc@60000 { + compatible =3D "rda,8810pl-mmc", "rda,mmc"; + reg =3D <0x60000 0x1000>; + interrupts =3D <4 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ap_syscon CLK_APB2>; + clock-names =3D "mclk"; + resets =3D <&ap_syscon RST_APB2_SDMMC2>; + dmas =3D <&ifc IFC_SDMMC2_TX>, <&ifc IFC_SDMMC2_RX>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + uart2: serial@10000 { compatible =3D "rda,8810pl-uart"; reg =3D <0x10000 0x1000>; @@ -136,6 +169,12 @@ uart3: serial@90000 { interrupts =3D <11 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; }; + + ifc: dma-controller@f0000 { + compatible =3D "rda,8810pl-ifc", "rda,ifc"; + reg =3D <0xf0000 0x1000>; + #dma-cells =3D <1>; + }; }; =20 l2: cache-controller@21100000 { --=20 2.51.0