From nobody Thu Oct 2 07:48:54 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4462522D7A1; Fri, 19 Sep 2025 03:19:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758251940; cv=none; b=WJCpG0TimDjGxt9qwJg56qXCCw5huQVfJSzZsoXMsW9RNkIW8IodBfVA2QFGUble+LKvznkWT7A2lIxNfCLz6D5dffBNyWCUOmxo0gAvJp7l/CncEQrDOC/pV9+EVzATNmDvaSfx0j408wa+FeuzW5zvUM1xAhQ5GmMsS3MLNFg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758251940; c=relaxed/simple; bh=gAv/gWsQ2Cl0kOldV7g5ft4pBj0bRxTan5ynAs/Ai3Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Jonj/inv80gFcaStSKo75eWHgoefKDYGvIdzRJm1rVZsdL1tCNylXSHeysVY3fTOLNijfxyNGnRM48x+3d2y7aPmxXTtWUNsNkM9nq3iniPv55h5AFR67IsdboXgzMIHA+Z2h8VDcJHMO+24CcD7Xb0BvnG57gmb/0gHCLPHWAw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lHiL0BN5; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lHiL0BN5" Received: by smtp.kernel.org (Postfix) with ESMTPS id ED6C3C4CEF7; Fri, 19 Sep 2025 03:18:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758251940; bh=gAv/gWsQ2Cl0kOldV7g5ft4pBj0bRxTan5ynAs/Ai3Y=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=lHiL0BN5glP0kfHhMPE9I1M+DBjKGDaRXz5YWcsetzcdBK+RBA7XqKTpmDlPVAvep jIsafS0RrYZerS48oAam5LFyXl7CCtOWu1yM69+UqtscGfJRt9zmRjrcu3qVmuHONw TDgrUjRWO21+vR+Ih4L7aTZZ908/JSNvk1ElFXEDar58FutLgOby/L9pjFPDQIbUjv IWIBJLJzGCZQ4L84BW9XfnV05PReYhBMNSCrhD7mRmR2iCBmcWHL4q+mKNTDv0p3Qb J8/wK08Fh3xCp31XqaTIw5bS1nXhDxheO5ZlrfKNEj0xnBG5cFIRKkvmxeyXsOGaJw 0gtJljouzKYTQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1BA3CA1013; Fri, 19 Sep 2025 03:18:59 +0000 (UTC) From: Fenglin Wu via B4 Relay Date: Fri, 19 Sep 2025 11:18:50 +0800 Subject: [PATCH v6 1/2] arm64: dts: qcom: x1e80100-crd: Add charge limit nvmem Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250919-qcom_battmgr_update_new-v6-1-ed5c38867614@oss.qualcomm.com> References: <20250919-qcom_battmgr_update_new-v6-0-ed5c38867614@oss.qualcomm.com> In-Reply-To: <20250919-qcom_battmgr_update_new-v6-0-ed5c38867614@oss.qualcomm.com> To: kernel@oss.qualcomm.com, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sebastian Reichel , Konrad Dybcio , Dmitry Baryshkov Cc: Subbaraman Narayanamurthy , David Collins , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Fenglin Wu , Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758251938; l=2081; i=fenglin.wu@oss.qualcomm.com; s=20240327; h=from:subject:message-id; bh=nPLGHoTJ5NTWoHSd8PH9bD21pqqTFHYPJjavOYsTnQM=; b=Qp3/B+LF3wqioqgmabrMHJVOowVh8ukpc4RgSqGleDq4wKLqjAuYJnP6TjFOGdig2SSHGFqzv rwXgC4/m20nCC4bkKA4hSx4apR2QwABRpioEVkbFdc4+s5MU9s9/qlq X-Developer-Key: i=fenglin.wu@oss.qualcomm.com; a=ed25519; pk=BF8SA4IVDk8/EBCwlBehKtn2hp6kipuuAuDAHh9s+K4= X-Endpoint-Received: by B4 Relay for fenglin.wu@oss.qualcomm.com/20240327 with auth_id=406 X-Original-From: Fenglin Wu Reply-To: fenglin.wu@oss.qualcomm.com From: Fenglin Wu Add nvmem cells for getting charge control thresholds if they have been set previously. Tested-by: Neil Armstrong # on Thinkpad T14S OL= ED Reviewed-by: Konrad Dybcio Signed-off-by: Fenglin Wu --- arch/arm64/boot/dts/qcom/x1-crd.dtsi | 7 +++++++ arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi | 20 ++++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qco= m/x1-crd.dtsi index c9f0d505267081af66b0973fe6c1e33832a2c86b..cd3c071624ce66f8c28ee4521fe= 3db8b737757a6 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -82,6 +82,13 @@ pmic-glink { <&tlmm 123 GPIO_ACTIVE_HIGH>, <&tlmm 125 GPIO_ACTIVE_HIGH>; =20 + nvmem-cells =3D <&charge_limit_en>, + <&charge_limit_end>, + <&charge_limit_delta>; + nvmem-cell-names =3D "charge_limit_en", + "charge_limit_end", + "charge_limit_delta"; + /* Left-side rear port */ connector@0 { compatible =3D "usb-c-connector"; diff --git a/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi b/arch/arm64/boot= /dts/qcom/x1e80100-pmics.dtsi index e3888bc143a0aaae23c92d400d48ea94423e0366..cc4994f890f83540c4fb238811b= c879ac9356256 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi @@ -240,6 +240,26 @@ reboot_reason: reboot-reason@48 { }; }; =20 + pmk8550_sdam_15: nvram@7e00 { + compatible =3D "qcom,spmi-sdam"; + reg =3D <0x7e00>; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0x7e00 0x100>; + + charge_limit_en: charge-limit-en@73 { + reg =3D <0x73 0x1>; + }; + + charge_limit_end: charge-limit-end@75 { + reg =3D <0x75 0x1>; + }; + + charge_limit_delta: charge-limit-delta@76 { + reg =3D <0x76 0x1>; + }; + }; + pmk8550_gpios: gpio@8800 { compatible =3D "qcom,pmk8550-gpio", "qcom,spmi-gpio"; reg =3D <0xb800>; --=20 2.34.1 From nobody Thu Oct 2 07:48:54 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9D6526529A; Fri, 19 Sep 2025 03:19:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758251940; cv=none; b=Kq/YCjC8tOsMcjGz46g1I7xPnAhiyhDBnkhAKft83LCJmprnua487CnrhRz/42dsxNP4jroX3fT/+IXw5/wtFqc6u+aVra08Oxb+bZVsGrW4iuq2Zg6uNAyCiIrPKdsWu7Zd6wvsTlfAZYekfF/NT/HJQRjwLz61fWuD6FAIaB0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758251940; c=relaxed/simple; bh=ggPk5dpFrY5d2ktYSzXrZSvVa0LXccEQketSd+fFRQo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IeIxCYg5jj0gbzqcozyAnrIClo5+1JM9DCEMb8RnJmOnv56saNAb7dg01UfdbROLKsLYUrQmPmzes/skeB4d8fN3/3YvA9XYK6+PYBJK1KdiosHrL6u9dMsgjacOZE3EAc5GMGrrppFK3J9S3WrWB8rjNyb6EYMOMlzbKL37OHk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ILDIsli4; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ILDIsli4" Received: by smtp.kernel.org (Postfix) with ESMTPS id F3418C4CEEB; Fri, 19 Sep 2025 03:18:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758251940; bh=ggPk5dpFrY5d2ktYSzXrZSvVa0LXccEQketSd+fFRQo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ILDIsli4+KUscphy54iXEx04Nis5Q+lxBqWeu2hdMUXHej/8A0GN3QLyAke8fWvlb go6kMXMqsfGg0AvsdwHswXcDmuduGdWmOyjlUKcpPMK6qqv8MdH2SScrt50sNw3s0W /oo69yD8SwRb3usaorm+ur+zDKhvEX+2VitztkxT7BjHAYTUdArvP/Wwwlm/Tf0pwn hYW4GpRN5SDakfnBSXyVU5xJEUiAbm1YezaWaR3XMIH31H84A4eFZPSwueLC8VDKDk MlNGWMxjjvo6krgEfs4Mp4KRfWVU6BGdzxdSTNQr/VfqyMLRVgvGEzaVpA0JrXVAQ7 8JmYFMCpgxa7g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFEE5CAC5A8; Fri, 19 Sep 2025 03:18:59 +0000 (UTC) From: Fenglin Wu via B4 Relay Date: Fri, 19 Sep 2025 11:18:51 +0800 Subject: [PATCH v6 2/2] power: supply: qcom_battmgr: handle charging state change notifications Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250919-qcom_battmgr_update_new-v6-2-ed5c38867614@oss.qualcomm.com> References: <20250919-qcom_battmgr_update_new-v6-0-ed5c38867614@oss.qualcomm.com> In-Reply-To: <20250919-qcom_battmgr_update_new-v6-0-ed5c38867614@oss.qualcomm.com> To: kernel@oss.qualcomm.com, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sebastian Reichel , Konrad Dybcio , Dmitry Baryshkov Cc: Subbaraman Narayanamurthy , David Collins , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Fenglin Wu , Sebastian Reichel X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758251938; l=2311; i=fenglin.wu@oss.qualcomm.com; s=20240327; h=from:subject:message-id; bh=qjtOHMPRwa1lClP72psxdJHsxXcpoXRVZvAtkWmKRnw=; b=uSCs45ufv9KjscLuuIBQVIsz9B6oD0bnb8skr2MyeHUxpvyB+mjw6PZYJ+JJWPdSprJZdl09D L04pPpex0mCCrwVOWPbHq3B/2uNiPafD2rlsa9m2V1LjFpVdasPGKdn X-Developer-Key: i=fenglin.wu@oss.qualcomm.com; a=ed25519; pk=BF8SA4IVDk8/EBCwlBehKtn2hp6kipuuAuDAHh9s+K4= X-Endpoint-Received: by B4 Relay for fenglin.wu@oss.qualcomm.com/20240327 with auth_id=406 X-Original-From: Fenglin Wu Reply-To: fenglin.wu@oss.qualcomm.com From: Fenglin Wu The X1E80100 battery management firmware sends a notification with code 0x83 when the battery charging state changes, such as switching between fast charge, taper charge, end of charge, or any other error charging states. The same notification code is used with bit[8] set when charging stops because the charge control end threshold is reached. Additionally, a 2-bit value is included in bit[10:9] with the same code to indicate the charging source capability, which is determined by the calculated power from voltage and current readings from PDOs: 2 means a strong charger over 60W, 1 indicates a weak charger, and 0 means there is no charging source. These 3-MSB [10:8] in the notification code is not much useful for now, hence just ignore them and trigger a power supply change event whenever 0x83 notification code is received. This helps to eliminate the unknown notification error messages. Reported-by: Sebastian Reichel Closes: https://lore.kernel.org/all/r65idyc4of5obo6untebw4iqfj2zteiggnnzabr= qtlcinvtddx@xc4aig5abesu/ Signed-off-by: Fenglin Wu --- drivers/power/supply/qcom_battmgr.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/power/supply/qcom_battmgr.c b/drivers/power/supply/qco= m_battmgr.c index 0fe14a109b70fcc15575730573a7a16d1d843613..3c2837ef3461730369b52a4edb0= 96795a531926a 100644 --- a/drivers/power/supply/qcom_battmgr.c +++ b/drivers/power/supply/qcom_battmgr.c @@ -34,8 +34,9 @@ enum qcom_battmgr_variant { #define NOTIF_BAT_PROPERTY 0x30 #define NOTIF_USB_PROPERTY 0x32 #define NOTIF_WLS_PROPERTY 0x34 -#define NOTIF_BAT_INFO 0x81 #define NOTIF_BAT_STATUS 0x80 +#define NOTIF_BAT_INFO 0x81 +#define NOTIF_BAT_CHARGING_STATE 0x83 =20 #define BATTMGR_BAT_INFO 0x9 =20 @@ -1209,12 +1210,14 @@ static void qcom_battmgr_notification(struct qcom_b= attmgr *battmgr, } =20 notification =3D le32_to_cpu(msg->notification); + notification &=3D 0xff; switch (notification) { case NOTIF_BAT_INFO: battmgr->info.valid =3D false; fallthrough; case NOTIF_BAT_STATUS: case NOTIF_BAT_PROPERTY: + case NOTIF_BAT_CHARGING_STATE: power_supply_changed(battmgr->bat_psy); break; case NOTIF_USB_PROPERTY: --=20 2.34.1