From nobody Thu Oct 2 07:48:25 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF6B42153D2; Fri, 19 Sep 2025 05:59:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758261551; cv=none; b=eKwKRqdy17qQZxzZzXUET6CUqcgAR/7GQgLn56uL6Kv9OamlIsUSsP1mtlML+VQ19xZk5fXTFmoOL+vDWBYIrs0d6ej2h4QxTDwILo3B9NSlJBZDxd/phcLAWDcdGMsZ0OgMpFpKHRQCC1v5vJv5n6A1R2yMzyiLAYFrhdcwZqM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758261551; c=relaxed/simple; bh=QLoUf6MbemExweEkSHZ6Cs4Fo/cev8YIR8uKZymd67k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lL9FzGcwfK64PEmt4VCiHpZkSiTS9fe4xxYBwsfaDegtPrdfknRBhFLqrEHlcyU97KebpKvfuD9xfG3CoUiV3hvjWPd4oxL1LmC+h3rZQ3fcFrjwl3ST9WS3ctgwFfIzsHvlbO74HyudzQQ2SK2nI1MqTwFbj2645DG9e0X1nFU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DdmmGPmg; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DdmmGPmg" Received: by smtp.kernel.org (Postfix) with ESMTPS id 91F59C4CEF7; Fri, 19 Sep 2025 05:59:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758261550; bh=QLoUf6MbemExweEkSHZ6Cs4Fo/cev8YIR8uKZymd67k=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=DdmmGPmg3TR3TMfxLtnLjyVcgG9cVOkyMT+JFYcLGXFUlyF1fl4JODVB8CF+VTHXK F9ExPLXTcQNzAbSun1YmtzOxc+VouR635zPDG0pVePHDRIHDOvzi9ZZZVYL5fu4RLC iBJgGBFBI6AbE13rqU7/kCXUFZ7z3V7dxU4Ljkv0OQ2KMBZUkLglxrWAxTBeSestrI hUefAAbJsKFsxUQ/jHTSvFFyQc2pV9XDWvHooqRrVDsW8m3jqWR2lF2rLMuUJMPpeD fLLjwS2Hb7+yXhhd3QQ0vXwBX4bLW/2ob86U+aXmdZsCkm7PtyeLRqY60sL8/9d8eb 0NJyA/08sSyiw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81091CAC5A8; Fri, 19 Sep 2025 05:59:10 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Fri, 19 Sep 2025 13:58:59 +0800 Subject: [PATCH v6 1/3] dt-bindings: clock: add video clock indices for Amlogic S4 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250919-add_video_clk-v6-1-fe223161fb3f@amlogic.com> References: <20250919-add_video_clk-v6-0-fe223161fb3f@amlogic.com> In-Reply-To: <20250919-add_video_clk-v6-0-fe223161fb3f@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Chuan Liu , Krzysztof Kozlowski , Conor Dooley X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758261548; l=1277; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=oFTBK7GmWCd1bTbEyxd9lw2QoXtneH1SDFph2xdcxG4=; b=qgOii3kCYety9Xap68/0E6rPikg6BVV+MXY2JSJ82KyPp0Vw9nm3HCAFXsY+3VabzegaeHx4p P0bxD3847auCuNMQOyYEvyTNeronrG/nAohEiE3pqXV7p+ioBRh4M0x X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add indices for video encoder, demodulator and CVBS clocks. Acked-by: Rob Herring (Arm) Acked-by: Krzysztof Kozlowski Acked-by: Conor Dooley Signed-off-by: Chuan Liu --- include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h b/incl= ude/dt-bindings/clock/amlogic,s4-peripherals-clkc.h index 861a331963ac..b0fc549f53e3 100644 --- a/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h +++ b/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h @@ -232,5 +232,16 @@ #define CLKID_HDCP22_SKPCLK_SEL 222 #define CLKID_HDCP22_SKPCLK_DIV 223 #define CLKID_HDCP22_SKPCLK 224 +#define CLKID_CTS_ENCL_SEL 225 +#define CLKID_CTS_ENCL 226 +#define CLKID_CDAC_SEL 227 +#define CLKID_CDAC_DIV 228 +#define CLKID_CDAC 229 +#define CLKID_DEMOD_CORE_SEL 230 +#define CLKID_DEMOD_CORE_DIV 231 +#define CLKID_DEMOD_CORE 232 +#define CLKID_ADC_EXTCLK_IN_SEL 233 +#define CLKID_ADC_EXTCLK_IN_DIV 234 +#define CLKID_ADC_EXTCLK_IN 235 =20 #endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S4_PERIPHERALS_CLKC_H */ --=20 2.42.0 From nobody Thu Oct 2 07:48:25 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1768328466C; Fri, 19 Sep 2025 05:59:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758261551; cv=none; b=hjTfHEpB9GpkwMYpFDmTaoWs5cUWALgUnJU48J26uNurTKWyIhbI1+u0lskgzTeyScIEiEk9Qp/rj13VheF2Jj9rqviduvSWJ3F5PFrTYT1FC43KTKRKv/efzbYWTRACBxpahwBFyiF8b7EbOqfr0aN/4JmdEGfvKUOQnGkq5xc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758261551; c=relaxed/simple; bh=VPHrTQDDEYO21a94I8JiwUQGWbVLi46Ixi6m9z/mf5I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZE5KjdhEFWrzrBOEYj3z/ryQs3tsfshYYsyT82fSmJPDT3gS7t7EFszt8DZkURIOnnfFuvZLiZ1mAGtIT7qcTMJnlK8r+oIz5+q1IHTPFH22C7pC0khkpU9ZVsRfw7TM5UVSWmT/KBSSvoyDC3Ph/Bc0cNv7oLWNeZs65a48p1s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=QJOkbXP2; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QJOkbXP2" Received: by smtp.kernel.org (Postfix) with ESMTPS id A5C31C4AF0B; Fri, 19 Sep 2025 05:59:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758261550; bh=VPHrTQDDEYO21a94I8JiwUQGWbVLi46Ixi6m9z/mf5I=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=QJOkbXP29P7Lk6a3p/1oTDd6ha3eRZF6Mt5yUSLV/xE4PYLWrH7tZSgsnoI3uSU1O aDOrg8l4HWh80L3yBw6dgYyi0CVdh78TL1nqbq32ol/A0TDuH4nOjWF7qrb2n+YuKH LxmaPB0ND7Fq6BgCqZDxnafdHIsAWSIazarWuAFww20yGeTcz3u9EimHrmxTDKMQ3s VArAMbehHvGc8ETGBZ1oXIEapdyCWKVzZ4+GOT9VuetcWp1voQCZan9ofHjmECXd7Z 6j5qUiV9T4J4oD/5zGswSRKNlzbBIMzlv5cMyGzoYxz0/fNIv2s0Kj2rfRYrPo35x9 Zju1lolxygUxQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91DE5CAC5A5; Fri, 19 Sep 2025 05:59:10 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Fri, 19 Sep 2025 13:59:00 +0800 Subject: [PATCH v6 2/3] clk: amlogic: add video-related clocks for S4 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250919-add_video_clk-v6-2-fe223161fb3f@amlogic.com> References: <20250919-add_video_clk-v6-0-fe223161fb3f@amlogic.com> In-Reply-To: <20250919-add_video_clk-v6-0-fe223161fb3f@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758261548; l=7108; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=Q4yUJrrH7nm8dR16U53oyYIkqzh2f0kcV3s4j1jZIus=; b=oob6e/DY3vATqWvRmwF3Rcn9uIPkMSOFx209c8+xqPfO8cN7TrIf261YquhKnhpwT1liqT4aq vXmPZE9hdHABRvkFs900ymrXnLEEfsJezkAwUGk5XygDsVlKIcSFXAw X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu Add video encoder, demodulator and CVBS clocks. Signed-off-by: Chuan Liu --- drivers/clk/meson/s4-peripherals.c | 202 +++++++++++++++++++++++++++++++++= ++++ 1 file changed, 202 insertions(+) diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peri= pherals.c index 6d69b132d1e1..aa500ea8ef9c 100644 --- a/drivers/clk/meson/s4-peripherals.c +++ b/drivers/clk/meson/s4-peripherals.c @@ -44,6 +44,7 @@ #define CLKCTRL_VDIN_MEAS_CLK_CTRL 0x0f8 #define CLKCTRL_VAPBCLK_CTRL 0x0fc #define CLKCTRL_HDCP22_CTRL 0x100 +#define CLKCTRL_CDAC_CLK_CTRL 0x108 #define CLKCTRL_VDEC_CLK_CTRL 0x140 #define CLKCTRL_VDEC2_CLK_CTRL 0x144 #define CLKCTRL_VDEC3_CLK_CTRL 0x148 @@ -1126,6 +1127,21 @@ static struct clk_regmap s4_cts_encp_sel =3D { }, }; =20 +static struct clk_regmap s4_cts_encl_sel =3D { + .data =3D &(struct clk_regmap_mux_data){ + .offset =3D CLKCTRL_VIID_CLK_DIV, + .mask =3D 0xf, + .shift =3D 12, + .table =3D s4_cts_parents_val_table, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cts_encl_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_hws =3D s4_cts_parents, + .num_parents =3D ARRAY_SIZE(s4_cts_parents), + }, +}; + static struct clk_regmap s4_cts_vdac_sel =3D { .data =3D &(struct clk_regmap_mux_data){ .offset =3D CLKCTRL_VIID_CLK_DIV, @@ -1205,6 +1221,22 @@ static struct clk_regmap s4_cts_encp =3D { }, }; =20 +static struct clk_regmap s4_cts_encl =3D { + .data =3D &(struct clk_regmap_gate_data){ + .offset =3D CLKCTRL_VID_CLK_CTRL2, + .bit_idx =3D 3, + }, + .hw.init =3D &(struct clk_init_data) { + .name =3D "cts_encl", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_cts_encl_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + static struct clk_regmap s4_cts_vdac =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CLKCTRL_VID_CLK_CTRL2, @@ -2735,6 +2767,165 @@ static struct clk_regmap s4_gen_clk =3D { }, }; =20 +/* CVBS DAC */ +static struct clk_regmap s4_cdac_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_CDAC_CLK_CTRL, + .mask =3D 0x3, + .shift =3D 16, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cdac_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .fw_name =3D "xtal", }, + { .fw_name =3D "fclk_div5" }, + }, + .num_parents =3D 2, + }, +}; + +static struct clk_regmap s4_cdac_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_CDAC_CLK_CTRL, + .shift =3D 0, + .width =3D 16, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cdac_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_cdac_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap s4_cdac =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_CDAC_CLK_CTRL, + .bit_idx =3D 20, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "cdac", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_cdac_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap s4_demod_core_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_DEMOD_CLK_CTRL, + .mask =3D 0x3, + .shift =3D 9, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "demod_core_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .fw_name =3D "xtal" }, + { .fw_name =3D "fclk_div7" }, + { .fw_name =3D "fclk_div4" } + }, + .num_parents =3D 3, + }, +}; + +static struct clk_regmap s4_demod_core_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_DEMOD_CLK_CTRL, + .shift =3D 0, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "demod_core_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_demod_core_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap s4_demod_core =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_DEMOD_CLK_CTRL, + .bit_idx =3D 8 + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "demod_core", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_demod_core_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +/* CVBS ADC */ +static struct clk_regmap s4_adc_extclk_in_sel =3D { + .data =3D &(struct clk_regmap_mux_data) { + .offset =3D CLKCTRL_DEMOD_CLK_CTRL, + .mask =3D 0x7, + .shift =3D 25, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "adc_extclk_in_sel", + .ops =3D &clk_regmap_mux_ops, + .parent_data =3D (const struct clk_parent_data []) { + { .fw_name =3D "xtal" }, + { .fw_name =3D "fclk_div4" }, + { .fw_name =3D "fclk_div3" }, + { .fw_name =3D "fclk_div5" }, + { .fw_name =3D "fclk_div7" }, + { .fw_name =3D "mpll2" }, + { .fw_name =3D "gp0_pll" }, + { .fw_name =3D "hifi_pll" } + }, + .num_parents =3D 8, + }, +}; + +static struct clk_regmap s4_adc_extclk_in_div =3D { + .data =3D &(struct clk_regmap_div_data) { + .offset =3D CLKCTRL_DEMOD_CLK_CTRL, + .shift =3D 16, + .width =3D 7, + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "adc_extclk_in_div", + .ops =3D &clk_regmap_divider_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_adc_extclk_in_sel.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap s4_adc_extclk_in =3D { + .data =3D &(struct clk_regmap_gate_data) { + .offset =3D CLKCTRL_DEMOD_CLK_CTRL, + .bit_idx =3D 24 + }, + .hw.init =3D &(struct clk_init_data){ + .name =3D "adc_extclk_in", + .ops =3D &clk_regmap_gate_ops, + .parent_hws =3D (const struct clk_hw *[]) { + &s4_adc_extclk_in_div.hw + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + }, +}; + static const struct clk_parent_data s4_pclk_parents =3D { .hw =3D &s4_sys_= clk.hw }; =20 #define S4_PCLK(_name, _reg, _bit, _flags) \ @@ -3028,6 +3219,17 @@ static struct clk_hw *s4_peripherals_hw_clks[] =3D { [CLKID_HDCP22_SKPCLK_SEL] =3D &s4_hdcp22_skpclk_sel.hw, [CLKID_HDCP22_SKPCLK_DIV] =3D &s4_hdcp22_skpclk_div.hw, [CLKID_HDCP22_SKPCLK] =3D &s4_hdcp22_skpclk.hw, + [CLKID_CTS_ENCL_SEL] =3D &s4_cts_encl_sel.hw, + [CLKID_CTS_ENCL] =3D &s4_cts_encl.hw, + [CLKID_CDAC_SEL] =3D &s4_cdac_sel.hw, + [CLKID_CDAC_DIV] =3D &s4_cdac_div.hw, + [CLKID_CDAC] =3D &s4_cdac.hw, + [CLKID_DEMOD_CORE_SEL] =3D &s4_demod_core_sel.hw, + [CLKID_DEMOD_CORE_DIV] =3D &s4_demod_core_div.hw, + [CLKID_DEMOD_CORE] =3D &s4_demod_core.hw, + [CLKID_ADC_EXTCLK_IN_SEL] =3D &s4_adc_extclk_in_sel.hw, + [CLKID_ADC_EXTCLK_IN_DIV] =3D &s4_adc_extclk_in_div.hw, + [CLKID_ADC_EXTCLK_IN] =3D &s4_adc_extclk_in.hw, }; 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Fri, 19 Sep 2025 05:59:10 +0000 (UTC) From: Chuan Liu via B4 Relay Date: Fri, 19 Sep 2025 13:59:01 +0800 Subject: [PATCH v6 3/3] clk: amlogic: remove potentially unsafe flags from S4 video clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250919-add_video_clk-v6-3-fe223161fb3f@amlogic.com> References: <20250919-add_video_clk-v6-0-fe223161fb3f@amlogic.com> In-Reply-To: <20250919-add_video_clk-v6-0-fe223161fb3f@amlogic.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Kevin Hilman , Martin Blumenstingl Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Chuan Liu X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758261548; l=1493; i=chuan.liu@amlogic.com; s=20240902; h=from:subject:message-id; bh=pOpocCKNpaziWiHhDcJu1vTMZ5jdWqLvQRMLrgn1IXk=; b=r14O5cCFsk9df7Bw/kETEQkh7o9IKmZ5Q7JHBFdXPEM/dxZevMJ3AfIfwazFWlcs/xX0Ssh/0 S6wSIFg/QLZBFbHr4/RDzoZr2PLcvw8lScuSWpG6CdNg7pj084sfRQX X-Developer-Key: i=chuan.liu@amlogic.com; a=ed25519; pk=fnKDB+81SoWGKW2GJNFkKy/ULvsDmJZRGBE7pR5Xcpo= X-Endpoint-Received: by B4 Relay for chuan.liu@amlogic.com/20240902 with auth_id=203 X-Original-From: Chuan Liu Reply-To: chuan.liu@amlogic.com From: Chuan Liu The video clocks enci, encp, vdac and hdmitx share the same clock source. Adding CLK_SET_RATE_PARENT to the mux may unintentionally change the shared parent clock, which could affect other video clocks. Signed-off-by: Chuan Liu --- drivers/clk/meson/s4-peripherals.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peri= pherals.c index aa500ea8ef9c..ba41fcd90588 100644 --- a/drivers/clk/meson/s4-peripherals.c +++ b/drivers/clk/meson/s4-peripherals.c @@ -1107,7 +1107,6 @@ static struct clk_regmap s4_cts_enci_sel =3D { .ops =3D &clk_regmap_mux_ops, .parent_hws =3D s4_cts_parents, .num_parents =3D ARRAY_SIZE(s4_cts_parents), - .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -1123,7 +1122,6 @@ static struct clk_regmap s4_cts_encp_sel =3D { .ops =3D &clk_regmap_mux_ops, .parent_hws =3D s4_cts_parents, .num_parents =3D ARRAY_SIZE(s4_cts_parents), - .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -1154,7 +1152,6 @@ static struct clk_regmap s4_cts_vdac_sel =3D { .ops =3D &clk_regmap_mux_ops, .parent_hws =3D s4_cts_parents, .num_parents =3D ARRAY_SIZE(s4_cts_parents), - .flags =3D CLK_SET_RATE_PARENT, }, }; =20 @@ -1185,7 +1182,6 @@ static struct clk_regmap s4_hdmi_tx_sel =3D { .ops =3D &clk_regmap_mux_ops, .parent_hws =3D s4_hdmi_tx_parents, .num_parents =3D ARRAY_SIZE(s4_hdmi_tx_parents), - .flags =3D CLK_SET_RATE_PARENT, }, }; =20 --=20 2.42.0