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a=ed25519-sha256; t=1758291893; l=3530; i=xiangxu.yin@oss.qualcomm.com; s=20241125; h=from:subject:message-id; bh=LgccMGQtMns6i0nd4D5JzFa/u0XEgWzMdMJHz1iq7Mg=; b=RZ+pfI6lFlal5bTRELifiJDJOmNfSXOrbV3GmlnRc2mTgli3PLCghwRB5J5m50K8n1B+MODV2 XfXIoGT1Ml/BuEV6FMILLRv1YKYgdDV2m82jRmd6HmmA/ON7VD3gTd3 X-Developer-Key: i=xiangxu.yin@oss.qualcomm.com; a=ed25519; pk=F1TwipJzpywfbt3n/RPi4l/A4AVF+QC89XzCHgZYaOc= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTE2MDIwMiBTYWx0ZWRfX1sUgqIy/S99w CmxAGATTWjz9maU3Wj1dOl/1mTJWUoidfy6eKtrmxxuS3uiZ9NUZzLo47JRT4YV5nuXxmLcRwSl iKj3BMv3HK8YpYfAueLDRvC2VjaJuTuWeWqzjK19PSJ7Ao6zqF9BYSXJB7cMOvu2Gg49dBzNB7P nIFYLd0OT1+OaEuWyTNdgnzoKX2lh8PkNrLTCju0MEKHf3UidPbu5h2xGacgqvDLVp+7vB6PoZe n6xSg5zQ3r1R+l/jbNxUOn94w0oB09K2RdchaBSwpI8EgA0XCEZRkWbbun7ySIFaehOrtkbXn+b 05+oQ6aFtZLYBZ+kFasgRRM51YBGaYhoNRnO8eylbmTCEj7z23Tw4iByyU5k7WrxYLeL1GQqAZk wq2ir2pl X-Proofpoint-ORIG-GUID: 4TCNSHEUW-1r8C74ewAnbxSKuSxBU51l X-Authority-Analysis: v=2.4 cv=KJZaDEFo c=1 sm=1 tr=0 ts=68cd67cd cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=Uz3yg00KUFJ2y2WijEJ4bw==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=z8W1oWq9hX_DlPyfQGsA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-GUID: 4TCNSHEUW-1r8C74ewAnbxSKuSxBU51l X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-19_01,2025-09-19_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 bulkscore=0 adultscore=0 impostorscore=0 suspectscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509160202 Add device tree binding documentation for the Qualcomm QMP USB3+DP PHY on QCS615 Platform. This PHY supports both USB3 and DP functionality over USB-C, with PHY mode switching capability. It does not support combo mode. Signed-off-by: Xiangxu Yin Reviewed-by: Rob Herring (Arm) --- .../bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml | 111 +++++++++++++++++= ++++ 1 file changed, 111 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-p= hy.yaml b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.= yaml new file mode 100644 index 0000000000000000000000000000000000000000..efb465c71c1b5870bd7ad3b0ec2= 15cf693a32f04 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,qcs615-qmp-usb3dp-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QMP USB3-DP PHY controller (DP, QCS615) + +maintainers: + - Xiangxu Yin + +description: + The QMP PHY controller supports physical layer functionality for both US= B3 + and DisplayPort over USB-C. While it enables mode switching between USB3= and + DisplayPort, but does not support combo mode. + +properties: + compatible: + enum: + - qcom,qcs615-qmp-usb3-dp-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + + clock-names: + items: + - const: aux + - const: ref + - const: cfg_ahb + - const: pipe + + resets: + maxItems: 2 + + reset-names: + items: + - const: phy_phy + - const: dp_phy + + vdda-phy-supply: true + + vdda-pll-supply: true + + "#clock-cells": + const: 1 + description: + See include/dt-bindings/phy/phy-qcom-qmp.h + + "#phy-cells": + const: 1 + description: + See include/dt-bindings/phy/phy-qcom-qmp.h + + qcom,tcsr-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to TCSR hardware block + - description: offset of the VLS CLAMP register + - description: offset of the PHY mode register + description: Clamp and PHY mode register present in the TCSR + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - vdda-phy-supply + - vdda-pll-supply + - "#clock-cells" + - "#phy-cells" + - qcom,tcsr-reg + +additionalProperties: false + +examples: + - | + #include + #include + + phy@88e8000 { + compatible =3D "qcom,qcs615-qmp-usb3-dp-phy"; + reg =3D <0x88e8000 0x2000>; + + clocks =3D <&gcc GCC_USB2_SEC_PHY_AUX_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>, + <&gcc GCC_AHB2PHY_WEST_CLK>, + <&gcc GCC_USB2_SEC_PHY_PIPE_CLK>; + clock-names =3D "aux", + "ref", + "cfg_ahb", + "pipe"; + + resets =3D <&gcc GCC_USB3PHY_PHY_SEC_BCR>, + <&gcc GCC_USB3_DP_PHY_SEC_BCR>; + reset-names =3D "phy_phy", + "dp_phy"; + + vdda-phy-supply =3D <&vreg_l5a>; + vdda-pll-supply =3D <&vreg_l12a>; + + #clock-cells =3D <1>; + #phy-cells =3D <1>; + + qcom,tcsr-reg =3D <&tcsr 0xbff0 0xb24c>; + }; --=20 2.34.1