From nobody Thu Oct 2 10:55:27 2025 Received: from smtpout-03.galae.net (smtpout-03.galae.net [185.246.85.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48A3B2FF65D for ; Thu, 18 Sep 2025 10:40:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.85.4 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758192044; cv=none; b=ftMXNArvDy1rvMJxirdQ1zoV8i5z71hArG5tsKWOJp8YQGWNDLt+nI7i+UcM6VXL0dgeu3kNfn8L87/UKEGY0ZVXS4EYhIAO6uc9NjdLlDNyXY3bU+ASX09iQ65tPl8ClE/DBKD/G/YRQX2Qhy5zI/2GIkPGiyn5X5phRE4yRgo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758192044; c=relaxed/simple; bh=R8Xsmkzx7aOYm1jK65/dyFCdtO4BUsHKP1UuUfcs/ew=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=q8NH3Ft2tmi2dI1DkoQpdEE1pMfKTnX3LKnMMUd6Jm3r6YhTBH3Tjka+ZH7qxeOhEsjXx+RQl8/kGE3BD4C+Q0fd1FIDJdL3QPeum19umurzW2DhUPhKjUNbXVgJnkFa74HeCVV2M3+uIFtiPEV8lbCPhcUy6StPnfa2tojvl9A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=ZJAf1huG; arc=none smtp.client-ip=185.246.85.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="ZJAf1huG" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-03.galae.net (Postfix) with ESMTPS id DC5574E40D08; Thu, 18 Sep 2025 10:40:40 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id A81FA6062C; Thu, 18 Sep 2025 10:40:40 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id DECC4102F1D06; Thu, 18 Sep 2025 12:40:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1758192039; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=K6kewgS5GEy/Q8lFyYhTpZvLBbKsoFjT0ZyUNHYjTdo=; b=ZJAf1huGXR2YOfnuItyX9Wx0KPv8cX2ezVcYUprOCmFHvGma8wYiq8ZLre7FhTIDxoM6bR mdvj7O0yaHX7Dyz4F7zEW1E+4nNKCB833W/iEbtNpiuJurelinsgTG9WHyM7JZ3Db4EIbk IwQjmPb5RBWwVMa2JgiSrkBtdNWvCvy5Ole9TqWWaqk/9RTHNgfKdfoFE3qLp+b5FmIETT w2OGjs9O57XhvfcER+I8fRJgq//0wX7JDdRaPnZSiQeOuH3Zy3knvBs1wMMLPmKpg2c14l SLNyX6Did4U7hIsMBuD5zyivW92eKw9OIc1wiID/An5IT57cleXq0dgjlQZa+A== From: "Herve Codina (Schneider Electric)" To: Thomas Gleixner , Wolfram Sang , Hoan Tran , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Saravana Kannan , Serge Semin , Herve Codina Cc: Phil Edworthy , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Pascal Eberhard , Miquel Raynal , Thomas Petazzoni Subject: [PATCH v3 6/8] dt-bindings: soc: renesas: Add the Renesas RZ/N1 GPIO Interrupt Multiplexer Date: Thu, 18 Sep 2025 12:40:04 +0200 Message-ID: <20250918104009.94754-7-herve.codina@bootlin.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250918104009.94754-1-herve.codina@bootlin.com> References: <20250918104009.94754-1-herve.codina@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Content-Type: text/plain; charset="utf-8" On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those interruption lines are multiplexed by the GPIO Interrupt Multiplexer in order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines. The GPIO interrupt multiplexer IP does nothing but select 8 GPIO IRQ lines out of the 96 available to wire them to the GIC input lines. Signed-off-by: Herve Codina (Schneider Electric) Acked-by: Conor Dooley --- .../soc/renesas/renesas,rzn1-gpioirqmux.yaml | 87 +++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,r= zn1-gpioirqmux.yaml diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpi= oirqmux.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-g= pioirqmux.yaml new file mode 100644 index 000000000000..21c6b6e1fa9a --- /dev/null +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux= .yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/renesas/renesas,rzn1-gpioirqmux.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1 SoCs GPIO Interrupt Multiplexer + +description: | + The Renesas RZ/N1 GPIO Interrupt Multiplexer multiplexes GPIO interrupt + lines to the interrupt controller available in the SoC. + + It selects up to 8 of the 96 GPIO interrupt lines available and connect= them + to 8 output interrupt lines. + +maintainers: + - Herve Codina + +properties: + compatible: + items: + - enum: + - renesas,r9a06g032-gpioirqmux + - const: renesas,rzn1-gpioirqmux + + reg: + maxItems: 1 + + "#address-cells": + const: 0 + + "#interrupt-cells": + const: 1 + + interrupt-map-mask: + items: + - const: 0x7f + + interrupt-map: + description: + Specifies the mapping from external GPIO interrupt lines to the outp= ut + interrupts. The array items have to be ordered with the first item + related to the output line 0 (IRQ 103), the next one to the output l= ine 1 + (IRQ 104) and so on up to the output line 8 (IRQ 110). + +required: + - compatible + - reg + - "#address-cells" + - "#interrupt-cells" + - interrupt-map-mask + - interrupt-map + +additionalProperties: false + +examples: + - | + #include + + gic: interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <3>; + }; + + interrupt-controller@51000480 { + compatible =3D "renesas,r9a06g032-gpioirqmux", "renesas,rzn1-gpioi= rqmux"; + reg =3D <0x51000480 0x20>; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0x7f>; + /* + * The child interrupt number is computed using the following form= ula: + * gpio_bank * 32 + gpio_number + * + * with: + * - gpio_bank: The GPIO bank number + * - 0 for GPIO0A, + * - 1 for GPIO1A, + * - 2 for GPIO2A + * - gpio_number: Number of the gpio in the bank (0..31) + */ + interrupt-map =3D + <32 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1A.0 */ + <89 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* GPIO2A.25 */ + <9 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; /* GPIO0A.9 */ + }; --=20 2.51.0