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To: Vinod Koul , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Thierry Reding" , Marc Zyngier , "Thomas Gleixner" , Liam Girdwood , "Mark Brown" CC: Jonathan Hunter , Sameer Pujar , , , , , , , sheetal Subject: [PATCH 1/4] dt-bindings: dma: Update ADMA bindings for tegra264 Date: Thu, 18 Sep 2025 15:50:06 +0530 Message-ID: <20250918102009.1519588-2-sheetal@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250918102009.1519588-1-sheetal@nvidia.com> References: <20250918102009.1519588-1-sheetal@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB52:EE_|IA1PR12MB9064:EE_ X-MS-Office365-Filtering-Correlation-Id: 2cac1764-5942-48f1-fbfd-08ddf69d0a91 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?U9VfUUV1vsVbvB+2UCUrX4/EIO2nZ224qqIkybRGxTN3rbb8NybfzEm7E9NK?= =?us-ascii?Q?OvqcqFT8ldGV7adWzxVeWg+UCi6cEQXbJG2BbnYoLWE7tdvBhpuJixpW08s2?= =?us-ascii?Q?rvdwMoUzrOoVyXH5Iski9m+Hw46aa3Gs5hWPeqbTDUSI9S55eD7kYYMlJbo+?= =?us-ascii?Q?wzWmjIEhp+iiH4Uh2DnW06EGF28ksjMOYiOGRwsXGY14jMqwZIjuI/0aFHS+?= =?us-ascii?Q?cg8QeLtejKzofmBfoy3IUNRZ28QWWvXD0VnppLzYqNsOzqdCdHMSD1CGMmLZ?= =?us-ascii?Q?Znexy+qVQw5FS7IhBrSMrlEsbo9MnWIi3u7t0sv70F/lKyuZb1QYhKRiilCf?= =?us-ascii?Q?sIghyW08cC3J5tawoT2Xt89uVQUTP2d5aY9ZXTX5siJ5JnfXz7yy9mMlBLk6?= =?us-ascii?Q?uJi+/sNPS+i1nXs5DAHln4cNOhx9LVhVg2UNSA5PLL5AfxoBkk8GSsX1A5lN?= =?us-ascii?Q?TARDTF35jJk64wvoOkMLRIiKqOZOEBKweXX0gdEvifghHm+/WmgNS6N+gN+G?= =?us-ascii?Q?D6BZV5PvKxNHFc8kLysqWO4GtJO81fwHNDtpCdJLbJlqJAqlteWSHOhZWjvc?= =?us-ascii?Q?HOmfRfDX2HGcP3Sub0cx5mePwrbJOFRF0y3hbTRfcj32vtMPItyVF+fa0ud7?= =?us-ascii?Q?7ynMBYRJ4TLFdCjF6hFIvMgTq9L48ejOxiC+5NX89JM+QOupWMjcplXpip/B?= =?us-ascii?Q?rcrta7eKKo54+YlLC2eoJpXrKHJ+Kn+lzAuJmKC9JmEPOoZ2fTOo1PxaH7tZ?= =?us-ascii?Q?BDHwS4aDno5JtNnou22vBLQzy0rGdwnSqsaTO714YB1bCS8jLKgqRAJyVP5Y?= =?us-ascii?Q?aBJsA+V4ie6N12c6LpsWXuVtbrBNyXMFsu6JlY6UndoXE2/WpC5EKMJd1sYW?= =?us-ascii?Q?1R+ntn7BcBuiWAvGBpM6Xz/VaSMloHW8VvKX//5ZtnH190sfLpcH7mv6WvHr?= =?us-ascii?Q?MBelbc2IYGzJnA082fKwuPQslVod+JYqQmsFQvhvbvOaoXEZziXJMGlSCAgZ?= =?us-ascii?Q?nE6GFwNjfrV+uZgmvAW110R0RjMHLHtemcrIR3k6ICAA5T8YvK12kgiIR4iq?= =?us-ascii?Q?YP6qEeI+mdggQpw0U1F5z6LOPoX2B3YDyTzZeJm451qK8lPgvo9LjTi1R4XW?= =?us-ascii?Q?pbRYtS7BMcuNg075z37zzUa1G+mccato0rKjFDdsvUwfS294RVIckJUKKGu5?= =?us-ascii?Q?xMkMze50YabPbV3pbYTbKul1+K91M2qjMskRUcZXRmDG8oxnGEaO0dDyN6LX?= =?us-ascii?Q?52GQc9aAMBUrcsSa0zHFFhlqpK391WTjht/bRDzJzd5CWsZ2XYd6ZCYfzeTo?= =?us-ascii?Q?dEU9zk7ZYEu5UhoNLgmarX5LF6PaG2bUHVwyaF6hyx5WqqlvZt1jDGJGZQSa?= =?us-ascii?Q?4UcuHk+El8XMa7qbZi6wAUmbNDXxGKP3wFV3Pgya4pSPuH8k2Cd2MKSSlxe4?= =?us-ascii?Q?wHgPPf+kQzHflVJYl1LgIfEQg/x1fzgDhOzTy+EXGm66Io+3tJgM3FReMuLe?= =?us-ascii?Q?JSyUyEBbWU322b4rLXrJEm5nB5FQg8wfl5/6?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Sep 2025 10:20:50.2355 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2cac1764-5942-48f1-fbfd-08ddf69d0a91 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB52.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB9064 Content-Type: text/plain; charset="utf-8" From: sheetal - Update ADMA device tree bindings for tegra264 to support up to 64 interrupt channels by setting 'interrupts' property maxItems to 64. - Also, update the 'allOf' conditional schema to ensure correct maxItems for 'interrupts' based on compatible string, including tegra210 (22) and tegra186 (32) ADMA controllers. Signed-off-by: sheetal Reviewed-by: Rob Herring (Arm) --- .../bindings/dma/nvidia,tegra210-adma.yaml | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yam= l b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml index da0235e451d6..269a1f7ebdbb 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml @@ -46,7 +46,7 @@ properties: Should contain all of the per-channel DMA interrupts in ascending order with respect to the DMA channel index. minItems: 1 - maxItems: 32 + maxItems: 64 =20 clocks: description: Must contain one entry for the ADMA module clock @@ -86,6 +86,19 @@ allOf: reg: items: - description: Full address space range of DMA registers. + interrupts: + maxItems: 22 + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra186-adma + then: + properties: + interrupts: + maxItems: 32 =20 - if: properties: --=20 2.34.1