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To: Vinod Koul , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Thierry Reding" , Marc Zyngier , "Thomas Gleixner" , Liam Girdwood , "Mark Brown" CC: Jonathan Hunter , Sameer Pujar , , , , , , , sheetal Subject: [PATCH 1/4] dt-bindings: dma: Update ADMA bindings for tegra264 Date: Thu, 18 Sep 2025 15:50:06 +0530 Message-ID: <20250918102009.1519588-2-sheetal@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250918102009.1519588-1-sheetal@nvidia.com> References: <20250918102009.1519588-1-sheetal@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB52:EE_|IA1PR12MB9064:EE_ X-MS-Office365-Filtering-Correlation-Id: 2cac1764-5942-48f1-fbfd-08ddf69d0a91 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?U9VfUUV1vsVbvB+2UCUrX4/EIO2nZ224qqIkybRGxTN3rbb8NybfzEm7E9NK?= =?us-ascii?Q?OvqcqFT8ldGV7adWzxVeWg+UCi6cEQXbJG2BbnYoLWE7tdvBhpuJixpW08s2?= =?us-ascii?Q?rvdwMoUzrOoVyXH5Iski9m+Hw46aa3Gs5hWPeqbTDUSI9S55eD7kYYMlJbo+?= =?us-ascii?Q?wzWmjIEhp+iiH4Uh2DnW06EGF28ksjMOYiOGRwsXGY14jMqwZIjuI/0aFHS+?= =?us-ascii?Q?cg8QeLtejKzofmBfoy3IUNRZ28QWWvXD0VnppLzYqNsOzqdCdHMSD1CGMmLZ?= =?us-ascii?Q?Znexy+qVQw5FS7IhBrSMrlEsbo9MnWIi3u7t0sv70F/lKyuZb1QYhKRiilCf?= =?us-ascii?Q?sIghyW08cC3J5tawoT2Xt89uVQUTP2d5aY9ZXTX5siJ5JnfXz7yy9mMlBLk6?= =?us-ascii?Q?uJi+/sNPS+i1nXs5DAHln4cNOhx9LVhVg2UNSA5PLL5AfxoBkk8GSsX1A5lN?= =?us-ascii?Q?TARDTF35jJk64wvoOkMLRIiKqOZOEBKweXX0gdEvifghHm+/WmgNS6N+gN+G?= =?us-ascii?Q?D6BZV5PvKxNHFc8kLysqWO4GtJO81fwHNDtpCdJLbJlqJAqlteWSHOhZWjvc?= =?us-ascii?Q?HOmfRfDX2HGcP3Sub0cx5mePwrbJOFRF0y3hbTRfcj32vtMPItyVF+fa0ud7?= =?us-ascii?Q?7ynMBYRJ4TLFdCjF6hFIvMgTq9L48ejOxiC+5NX89JM+QOupWMjcplXpip/B?= =?us-ascii?Q?rcrta7eKKo54+YlLC2eoJpXrKHJ+Kn+lzAuJmKC9JmEPOoZ2fTOo1PxaH7tZ?= =?us-ascii?Q?BDHwS4aDno5JtNnou22vBLQzy0rGdwnSqsaTO714YB1bCS8jLKgqRAJyVP5Y?= =?us-ascii?Q?aBJsA+V4ie6N12c6LpsWXuVtbrBNyXMFsu6JlY6UndoXE2/WpC5EKMJd1sYW?= =?us-ascii?Q?1R+ntn7BcBuiWAvGBpM6Xz/VaSMloHW8VvKX//5ZtnH190sfLpcH7mv6WvHr?= =?us-ascii?Q?MBelbc2IYGzJnA082fKwuPQslVod+JYqQmsFQvhvbvOaoXEZziXJMGlSCAgZ?= =?us-ascii?Q?nE6GFwNjfrV+uZgmvAW110R0RjMHLHtemcrIR3k6ICAA5T8YvK12kgiIR4iq?= =?us-ascii?Q?YP6qEeI+mdggQpw0U1F5z6LOPoX2B3YDyTzZeJm451qK8lPgvo9LjTi1R4XW?= =?us-ascii?Q?pbRYtS7BMcuNg075z37zzUa1G+mccato0rKjFDdsvUwfS294RVIckJUKKGu5?= =?us-ascii?Q?xMkMze50YabPbV3pbYTbKul1+K91M2qjMskRUcZXRmDG8oxnGEaO0dDyN6LX?= =?us-ascii?Q?52GQc9aAMBUrcsSa0zHFFhlqpK391WTjht/bRDzJzd5CWsZ2XYd6ZCYfzeTo?= =?us-ascii?Q?dEU9zk7ZYEu5UhoNLgmarX5LF6PaG2bUHVwyaF6hyx5WqqlvZt1jDGJGZQSa?= =?us-ascii?Q?4UcuHk+El8XMa7qbZi6wAUmbNDXxGKP3wFV3Pgya4pSPuH8k2Cd2MKSSlxe4?= =?us-ascii?Q?wHgPPf+kQzHflVJYl1LgIfEQg/x1fzgDhOzTy+EXGm66Io+3tJgM3FReMuLe?= =?us-ascii?Q?JSyUyEBbWU322b4rLXrJEm5nB5FQg8wfl5/6?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Sep 2025 10:20:50.2355 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2cac1764-5942-48f1-fbfd-08ddf69d0a91 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB52.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB9064 Content-Type: text/plain; charset="utf-8" From: sheetal - Update ADMA device tree bindings for tegra264 to support up to 64 interrupt channels by setting 'interrupts' property maxItems to 64. - Also, update the 'allOf' conditional schema to ensure correct maxItems for 'interrupts' based on compatible string, including tegra210 (22) and tegra186 (32) ADMA controllers. Signed-off-by: sheetal Reviewed-by: Rob Herring (Arm) --- .../bindings/dma/nvidia,tegra210-adma.yaml | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yam= l b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml index da0235e451d6..269a1f7ebdbb 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml @@ -46,7 +46,7 @@ properties: Should contain all of the per-channel DMA interrupts in ascending order with respect to the DMA channel index. minItems: 1 - maxItems: 32 + maxItems: 64 =20 clocks: description: Must contain one entry for the ADMA module clock @@ -86,6 +86,19 @@ allOf: reg: items: - description: Full address space range of DMA registers. + interrupts: + maxItems: 22 + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra186-adma + then: + properties: + interrupts: + maxItems: 32 =20 - if: properties: --=20 2.34.1 From nobody Thu Oct 2 09:18:57 2025 Received: from SN4PR0501CU005.outbound.protection.outlook.com (mail-southcentralusazon11011062.outbound.protection.outlook.com [40.93.194.62]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EAE52F9C2C; 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To: Vinod Koul , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Thierry Reding" , Marc Zyngier , "Thomas Gleixner" , Liam Girdwood , "Mark Brown" CC: Jonathan Hunter , Sameer Pujar , , , , , , , sheetal Subject: [PATCH 2/4] dt-bindings: sound: Update ADMAIF bindings for tegra264 Date: Thu, 18 Sep 2025 15:50:07 +0530 Message-ID: <20250918102009.1519588-3-sheetal@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250918102009.1519588-1-sheetal@nvidia.com> References: <20250918102009.1519588-1-sheetal@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB59:EE_|DS7PR12MB9041:EE_ X-MS-Office365-Filtering-Correlation-Id: 1e0c1a00-0925-463b-f1d9-08ddf69d0d78 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?iSXeq6z4pAJcZVipxZ5ib9UZGQ2PSeWT2iR6Ob27QwAunuVXVXe5MrBi67DP?= =?us-ascii?Q?AubbNq63on/aq1yi6MCSUCoBwY1OO5ltva3kfwvq6Y2ccHbUq0c36y2mtPWT?= =?us-ascii?Q?UAz6PoEVweWO+UVPuNQvNgPGkxTEqAf1dfbJimHx1N/Fzvm3qIwgQjcCHJEL?= =?us-ascii?Q?PnXnc/dltQriv4WJlo6qNA1KMZClEih6ct8xKnmK1fLu6t+dOVw5Tr8hb9Np?= =?us-ascii?Q?b7OewlHD2bH3HlnF2LFwxJtohNjquzDHxTQSl8Ejmkk5m8aoTgypTD/rJ6L5?= =?us-ascii?Q?OP88nHiP9uHBoC2f10FTf50nQy5wWliAxcF5GEHVIgvw4iNh52iqH4l2XYRe?= =?us-ascii?Q?AuCPBvmYR4WVghNFRx2xpB1rTH3FbKLz3FHjfMsaRdUT/ajlzo2TVg+FQAIq?= =?us-ascii?Q?56KxcR5+q05bxPhe4ykBMxeyE303YB882WCjUXJ5YgvKezSgDhha5UMMh24k?= =?us-ascii?Q?pP8uu1BPdRPNPSgWYRRZ623Y+FJoL/kzeyH3IX45BtMR0WY1OeIqxebNEZwQ?= =?us-ascii?Q?H2G/Zb/KilFgDQImIPzv7Nurgo3DDL87TvVYpTE4UZSfNwJeWyeI7XucNKKp?= =?us-ascii?Q?+lR3k2LUABmM72W2dWipzVOqxyjsHS4dGRgWajq86wrFK/PFwYK0bNk8XLZp?= =?us-ascii?Q?ZhFwSO77EHfJTVLhKIE+KynLmiYn8Xnn1auF0+h2KQR4umbi+U63uJncIK9l?= =?us-ascii?Q?J01FnAkYr7CKawgjc6wecTD4AIwdCnuYGDyH6oQg8UshngdkMsGVtDgYQLK8?= =?us-ascii?Q?cWnl+062QEEHe5GTFhOof0bxAsa5SlhoQ+f3xCDuIaB/j4wkAgPaeIApaDOd?= =?us-ascii?Q?GouAo1izw5W+W+LiMiKqikd0hyklwqAUOv6Claur1wwzPiEQVCp04+j1ciYu?= =?us-ascii?Q?oDJD1sJngQSmlcrOEjH+jUBxC7l/iA4SEkaC9vO4TRDuJLDtrx/ZV9GXK42q?= =?us-ascii?Q?q7FgCWUT0i64QDwppMuS2HbfFnvA9oHVLn/ojYlAY8VjsCnoK7gxT31DvbWj?= =?us-ascii?Q?7cJB944ulE5fuO5WGaWhsfTNzhor3xbfGb41QDL+M4PwdasWH9BAp9/PSI/W?= =?us-ascii?Q?4YIebTKjWPl4E8WkBfmHmWOKcpExBST0H8Lx83naDarA1iwZDc89rINV3w9f?= =?us-ascii?Q?CJyi67ymrYRv2aVLxnlmyH7x0B8QkYlvDYdyhL++5V/1wuVHxubtfnB84zn1?= =?us-ascii?Q?/gY+479cKMmmXcAAlRSQJI5fmFCFgdRmZll3JkwPtC/c0Bc6LQgu1zpgaaVZ?= =?us-ascii?Q?D1JjVoL5HFC0HTQ7Zleo1dFUolSSzy6NXp4pBjpuESU9XQuYNRfCb/doSpvn?= =?us-ascii?Q?ta+XTohqegQBj142SPisamSKQUIEjmt7AvKZmAwspL+K4GO4eiUwmzI8NJJw?= =?us-ascii?Q?/N80NMD7ZmC+KzMt8tO39NXJcf1WfNkWDIDRarwd1nUUpTd1KAmBQXX5lx46?= =?us-ascii?Q?RgWbandIFsKbyCs8Tsch5Rt/fzHG4JC38luW7ocp9wgyT2dwYL3c8UmVHyQ5?= =?us-ascii?Q?XczMXwNpo9kZS5oFiPzzE2zUUfZ5Y1yr3BiY?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Sep 2025 10:20:55.0928 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1e0c1a00-0925-463b-f1d9-08ddf69d0d78 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB59.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB9041 Content-Type: text/plain; charset="utf-8" From: sheetal Update the ADMAIF bindings as tegra264 supports 64 channels, which includes 32 RX and 32 TX channels. Signed-off-by: sheetal --- .../sound/nvidia,tegra210-admaif.yaml | 49 +++++++++++++------ 1 file changed, 35 insertions(+), 14 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-admaif= .yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-admaif.yaml index b32f33214ba6..f53ecef379b3 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-admaif.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-admaif.yaml @@ -93,20 +93,41 @@ then: iommus: false =20 else: - properties: - dmas: - description: - DMA channel specifiers, equally divided for Tx and Rx. - minItems: 1 - maxItems: 40 - dma-names: - items: - pattern: "^[rt]x(1[0-9]|[1-9]|20)$" - description: - Should be "rx1", "rx2" ... "rx20" for DMA Rx channel - Should be "tx1", "tx2" ... "tx20" for DMA Tx channel - minItems: 1 - maxItems: 40 + if: + properties: + compatible: + contains: + const: nvidia,tegra264-admaif + then: + properties: + dmas: + description: + DMA channel specifiers, equally divided for Tx and Rx. + minItems: 1 + maxItems: 64 + dma-names: + items: + pattern: "^[rt]x(3[0-2]|[1-2][0-9]|[1-9])$" + description: + Should be "rx1", "rx2" ... "rx32" for DMA Rx channel + Should be "tx1", "tx2" ... "tx32" for DMA Tx channel + minItems: 1 + maxItems: 64 + else: + properties: + dmas: + description: + DMA channel specifiers, equally divided for Tx and Rx. + minItems: 1 + maxItems: 40 + dma-names: + items: + pattern: "^[rt]x(1[0-9]|[1-9]|20)$" + description: + Should be "rx1", "rx2" ... "rx20" for DMA Rx channel + Should be "tx1", "tx2" ... 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To: Vinod Koul , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Thierry Reding" , Marc Zyngier , "Thomas Gleixner" , Liam Girdwood , "Mark Brown" CC: Jonathan Hunter , Sameer Pujar , , , , , , , sheetal Subject: [PATCH 3/4] dt-bindings: interrupt-controller: arm,gic: Add tegra264-agic Date: Thu, 18 Sep 2025 15:50:08 +0530 Message-ID: <20250918102009.1519588-4-sheetal@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250918102009.1519588-1-sheetal@nvidia.com> References: <20250918102009.1519588-1-sheetal@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA52:EE_|SJ0PR12MB8613:EE_ X-MS-Office365-Filtering-Correlation-Id: e0f9ac4c-2b84-4d99-860d-08ddf69d1390 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|36860700013|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?jN4nBfYXYPajjSgRVyPQdgvcDEeca8SGQiAvx+fN8ypaYs41XEJaCSvCEm0u?= =?us-ascii?Q?X9HK45R/hJJtDW4m2fwBmBhzkip81SMhQLSRdV9EYSwy5N21kykEadf9ji6+?= =?us-ascii?Q?WWJylMjvGS5Q8nSNzM5Uk8NYySN7cA5tLX8gZUPeYgm4hpSCYq6zC0PVAS1N?= =?us-ascii?Q?H4z9cEJVem8/7/1G25YEZK+w8pSKphXLtJp32IBWnBTcbQe73kzPGpB2wein?= =?us-ascii?Q?A1OQHD9ITr/aV9vV7lBl3C0dzNmhFwUvgJ3l3kyvYlk9b47+Qjx7o0VJg5IZ?= =?us-ascii?Q?p3NqwAZYz2079sJVdNNQ0s2Zh948IWBc2o4NmypnIHFTwbuOXMQAXXG75mjE?= =?us-ascii?Q?cb67/I5A2/MmifB4AZRrGBU8bIsdfM3LRu9vagqwBPX8TVn+FwPCwiVMgkkV?= =?us-ascii?Q?6UG79cI16E6NX+oexKdwEIPn/qqXBL/JYqgjyzYxhodahiZ0h6wG+uGOgwc5?= =?us-ascii?Q?xDk/iNhcq9fO7bhms37uJ5gS5beDNaDZVNvBRcM7Yx1mM70eA0hCbrHqdAhV?= =?us-ascii?Q?DiaauN4TYczBX/J/0z1bRJ/WjSfOIgQ3JhEKBbPSv/xZis7nDye4vtoTx/8k?= =?us-ascii?Q?kmR0wYOoCBLCQ9E2BqbY9eXRm1VnLu/i0lt3XaWAjpCZVl1mwdsq1E24uY0v?= =?us-ascii?Q?ZPlyq5VxLO55rQ6CdkF6UjKeiBxI7f8PW9e9hOelWkVgEgCsKBaS5wv7Q3gG?= =?us-ascii?Q?piHiHYrt5S3/Qyden/dOBT00P+c1GcShbbCylNisT23hgmTFy5OP8TPuunh9?= =?us-ascii?Q?N9sU6RzCRkD3uR+S5J8E+mD8wtklnUc54wkbApISAG8rEYIXFc2W92xmkjrA?= =?us-ascii?Q?+5H8WlChQaCqmavDZV6ibsbkCQ5gfcP21lybo3n8RgAOdZmjgJ1fjXbi2kOQ?= =?us-ascii?Q?Z4Qu3sFxXFi0+dB8oeULUdFJ4CiDEl9DQIjsMlROyxt05BzNShnVXdyfH2qT?= =?us-ascii?Q?r17OZZ90bQf31s1oppwhCHWQ89V1lV9DvPiLRBV6dyFFjjdLrLHdHOV9KieZ?= =?us-ascii?Q?nzhp+MI6xXpgfhOxDmu4A/b1Y4L1PBpEBVFTcfzPrKW1J4VdbbWb4jOsb+em?= =?us-ascii?Q?jaSJBKDKpX2G2P0vFuiKx7tSaVolRbI+kc1hH1O2Uz4AkIkmT9QXgU3ywHlx?= =?us-ascii?Q?4E9JdTkqZkTpbCDC8r7Wfuvj9vL8llkPCufm9jWzIF+/SuqW+YIcElFxjMti?= =?us-ascii?Q?6SkJ53nMsQP07iJRtlpPV0LqVtj9odcUeKV8/De5pG4ooWGqU6owwgxOBZWh?= =?us-ascii?Q?Ef3jX54PaQR+Z8LV7DAii2dztXt0hSdB7OtQQ3kydlXGtacf7bUggtYYsETl?= =?us-ascii?Q?xZcVoUHCj81IgDycLcsS+/T0P2YuwJzVPGyTdsu8hXpz6rc9thDONli0Nypb?= =?us-ascii?Q?KcXk3zKOdJHysUDDJCa23VkLBTaD5j7tPWglFEw8UpX17locIkWHb1svCnyS?= =?us-ascii?Q?7/F2d+zV/iMAY07uARgurg1KKMvBM1ge6DdV6GiIZcwU22cBnYTKcZyZ/O6Z?= =?us-ascii?Q?FZOWtInDg67d5t0mln1DF6I7tAV5/5XzRqB7?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(36860700013)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Sep 2025 10:21:05.3560 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e0f9ac4c-2b84-4d99-860d-08ddf69d1390 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA52.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB8613 Content-Type: text/plain; charset="utf-8" From: sheetal Add nvidia,tegra264-agic to the arm,gic binding for tegra264 audio interrupt controller support. Signed-off-by: sheetal --- .../devicetree/bindings/interrupt-controller/arm,gic.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic= .yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml index 7173c4b5a228..ee4c77dac201 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml @@ -59,6 +59,7 @@ properties: - nvidia,tegra186-agic - nvidia,tegra194-agic - nvidia,tegra234-agic + - nvidia,tegra264-agic - const: nvidia,tegra210-agic =20 interrupt-controller: true --=20 2.34.1 From nobody Thu Oct 2 09:18:57 2025 Received: from CH1PR05CU001.outbound.protection.outlook.com (mail-northcentralusazon11010054.outbound.protection.outlook.com [52.101.193.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 214902FFF98; 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To: Vinod Koul , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Thierry Reding" , Marc Zyngier , "Thomas Gleixner" , Liam Girdwood , "Mark Brown" CC: Jonathan Hunter , Sameer Pujar , , , , , , , sheetal Subject: [PATCH 4/4] arm64: tegra: Add tegra264 audio support Date: Thu, 18 Sep 2025 15:50:09 +0530 Message-ID: <20250918102009.1519588-5-sheetal@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250918102009.1519588-1-sheetal@nvidia.com> References: <20250918102009.1519588-1-sheetal@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA50:EE_|SJ2PR12MB8873:EE_ X-MS-Office365-Filtering-Correlation-Id: e2759e1b-b606-4e69-66ae-08ddf69d15fd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?gzydDXhX21icgx62LnL6MYr1gatgtjlborlC7YOk80Y+WSBcASc30wd63xHf?= =?us-ascii?Q?ub+BBItfyzIoWRKB8q3s8tQ7VFc1f+LeTeFddpXfAVLXfAeQhG/7J0ZfEnYg?= =?us-ascii?Q?PYUOinUlIdEuHXkXs+esNH/I0a5UaCTWRK2+io+Ht4bDL4Vci1K4JW8BhYOP?= =?us-ascii?Q?un7Zhels40DKoZMPUv/Tebn7OcTtJtPq5mmWyAdOVC9Th5MFP4PAY/bmb/pa?= =?us-ascii?Q?iDaei1rBFzrc5IKhxXX8iIX8OWkEO5CEVMFrIkgNzugmZ4sC/jpD6ixx4kVQ?= =?us-ascii?Q?vWp/31CEs0GxtJLcTVZI5sfB4GoWlyoXLxJc6GkhgS7tcmosS01ZYa201hQR?= =?us-ascii?Q?ZmUjr6A6DiRrHt3GxBaPWJuDZEUUSrQ4OCZ7ZTV56UFqminuChLdDlwCuayO?= =?us-ascii?Q?6xDWZsCMJbgKXa12n6Oj77/g3GXC64RYkesTBRe3g95XiXGj13UVahciDLIF?= =?us-ascii?Q?bFLvCyEx/ToaDJAj9rxLOW18wGCEZPtRJn8U5+aSdQQbBZiNQVJcqK0jGcTH?= =?us-ascii?Q?npirprnyu23k455lPo7XITW3N6yp/cU3yuCPqvCnXhV/odePFja8vrQ4NZzH?= =?us-ascii?Q?pEp6awb4iA9JKIUgSktNX8dFUZO4P94X/PcjK5BKxso+aQCGPM9KpFme8RYc?= =?us-ascii?Q?RtFtn0Ty6BCIlJWPiXow22uA9nJLSSpoAv2/FxfJGnt9O7YDKF5vWo4xjuPs?= =?us-ascii?Q?s1Iv4LRKY8+SRdMjQMnNW2Ehyt2Gc5i1ONuRRLFr7c05Qmg0/OHlnkeAM0Hk?= =?us-ascii?Q?6FIZQaHjI0FiL4UtVcHPQTfpFAhbtrnK1XyENOWQyUfr25MAwiIpnATmJ8fu?= =?us-ascii?Q?VGcfhAS0Z/VB/mMRcYVzu6SjsivIwd4Cf/xMXzYLtfXLBxNthBCHe5xUaN5F?= =?us-ascii?Q?OQ8zbUNORXW92QrFktBSQADOdnuUdrqwukI16iBfOFGYP520k51OtXJywaki?= =?us-ascii?Q?8zAIvGjoaBbEVwchDO4N4nt5H8qEffvdIt7sxPTiqc/TbQ48ufyuAsj+7T10?= =?us-ascii?Q?W29WBAW6lAVtwZWC8ttgv/bqEFz7BH2aYgwX1Xyi6qNZYrj6L3ktOBopjpWh?= =?us-ascii?Q?f/7nIHmQDTFRjLAUmep72ilaG5YqiW2bw/fzgirIY40PFFVzprFr1kc9qKRU?= =?us-ascii?Q?M4HgslsAu7LlDikKIZMF54CmIKet8OXn8BdrbeGLO4oyKgrc7IxTvvsWwYAd?= =?us-ascii?Q?VfDvxPEK1msTYeJXP1ock4CsgPIy+teblQIEs0bWygwTtTJBR5f1NgTPOB7p?= =?us-ascii?Q?5CQq0paKmU4knzfCY9YVFLSzgHo74c7YzPl/5sMtdFSjNoKUqZBNP78lBMRS?= =?us-ascii?Q?2t+YriZ3xpE0NbFL3uq9jDSEbuc7/5kB7mq3JVp7RwYZVcye1NEzjzkzY84p?= =?us-ascii?Q?+CjrUQa87WQS+rdixZ4pOW06IanQETIV9Md+8o7zAR/OZ5gN6vqGIpydZb6k?= =?us-ascii?Q?JAm9xWabAoTPSICWQbJ+r0cOx02O2bfBsXtpWlU0Lo3hC0TNAoYg2iht9V6J?= =?us-ascii?Q?EqIJsUTYdzZ/g3QFSN1MNBZSldfQpKrcLD6W?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(7416014)(376014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Sep 2025 10:21:09.4156 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e2759e1b-b606-4e69-66ae-08ddf69d15fd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA50.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8873 Content-Type: text/plain; charset="utf-8" From: sheetal - Add the audio devices for the tegra264 SoC in the tegra264.dtsi file, which includes sound, HDA and APE(Audio Processing Engine) subsystem nodes. APE subsystem includes, - I/O interfaces such as I2S, DMIC and DSPK (all the available instances). - HW accelerators such as ASRC, OPE, MVC, SFC, AMX, ADX and Mixer (all the available instances). - ADMA controller and Interrupt controllers. - Enable the audio nodes in tegra264-p3971.dtsi platform DT file. Signed-off-by: sheetal --- .../arm64/boot/dts/nvidia/tegra264-p3971.dtsi | 106 + arch/arm64/boot/dts/nvidia/tegra264.dtsi | 3190 +++++++++++++++++ 2 files changed, 3296 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3971.dtsi b/arch/arm64/bo= ot/dts/nvidia/tegra264-p3971.dtsi index 6b6259b7310f..1fcfac2066ae 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264-p3971.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264-p3971.dtsi @@ -1,4 +1,110 @@ // SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause =20 / { + bus@0 { + aconnect@9000000 { + status =3D "okay"; + + dma-controller@9440000 { + status =3D "okay"; + }; + + ahub@9630000 { + status =3D "okay"; + + i2s@9280000 { + status =3D "okay"; + }; + + i2s@9290000 { + status =3D "okay"; + }; + + i2s@92b0000 { + status =3D "okay"; + }; + }; + + interrupt-controller@9960000 { + status =3D "okay"; + }; + }; + + hda@88090b0000 { + nvidia,model =3D "NVIDIA Jetson Thor AGX HDA"; + status =3D "okay"; + }; + }; + + sound { + status =3D "okay"; + + dais =3D /* ADMAIF (FE) Ports */ + <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port= >, + <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port= >, + <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_po= rt>, + <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_= port>, + <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_= port>, + <&admaif20_port>, <&admaif21_port>, <&admaif22_port>, <&admaif23_= port>, + <&admaif24_port>, <&admaif25_port>, <&admaif26_port>, <&admaif27_= port>, + <&admaif28_port>, <&admaif29_port>, <&admaif30_port>, <&admaif31_= port>, + /* XBAR Ports */ + <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s4_port>, + <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>, + <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>, + <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>, + <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>, + <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>, + <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>, + <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>, + <&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>, + <&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>, + <&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>, + <&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>, + <&xbar_amx5_in1_port>, <&xbar_amx5_in2_port>, + <&xbar_amx5_in3_port>, <&xbar_amx5_in4_port>, + <&xbar_amx6_in1_port>, <&xbar_amx6_in2_port>, + <&xbar_amx6_in3_port>, <&xbar_amx6_in4_port>, + <&xbar_adx1_in_port>, <&xbar_adx2_in_port>, + <&xbar_adx3_in_port>, <&xbar_adx4_in_port>, + <&xbar_adx5_in_port>, <&xbar_adx6_in_port>, + <&xbar_mix_in1_port>, <&xbar_mix_in2_port>, + <&xbar_mix_in3_port>, <&xbar_mix_in4_port>, + <&xbar_mix_in5_port>, <&xbar_mix_in6_port>, + <&xbar_mix_in7_port>, <&xbar_mix_in8_port>, + <&xbar_mix_in9_port>, <&xbar_mix_in10_port>, + <&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>, + <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>, + <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>, + <&xbar_asrc_in7_port>, + <&xbar_ope1_in_port>, + /* HW accelerators */ + <&sfc1_out_port>, <&sfc2_out_port>, + <&sfc3_out_port>, <&sfc4_out_port>, + <&mvc1_out_port>, <&mvc2_out_port>, + <&amx1_out_port>, <&amx2_out_port>, + <&amx3_out_port>, <&amx4_out_port>, + <&amx5_out_port>, <&amx6_out_port>, + <&adx1_out1_port>, <&adx1_out2_port>, + <&adx1_out3_port>, <&adx1_out4_port>, + <&adx2_out1_port>, <&adx2_out2_port>, + <&adx2_out3_port>, <&adx2_out4_port>, + <&adx3_out1_port>, <&adx3_out2_port>, + <&adx3_out3_port>, <&adx3_out4_port>, + <&adx4_out1_port>, <&adx4_out2_port>, + <&adx4_out3_port>, <&adx4_out4_port>, + <&adx5_out1_port>, <&adx5_out2_port>, + <&adx5_out3_port>, <&adx5_out4_port>, + <&adx6_out1_port>, <&adx6_out2_port>, + <&adx6_out3_port>, <&adx6_out4_port>, + <&mix_out1_port>, <&mix_out2_port>, <&mix_out3_port>, + <&mix_out4_port>, <&mix_out5_port>, + <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>, + <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>, + <&ope1_out_port>, + /* BE I/O Ports */ + <&i2s1_port>, <&i2s2_port>, <&i2s4_port>; + + label =3D "NVIDIA Jetson Thor AGX APE"; + }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts= /nvidia/tegra264.dtsi index e02659efa233..49eed7fc16e7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -5,6 +5,7 @@ #include #include #include +#include =20 / { compatible =3D "nvidia,tegra264"; @@ -49,6 +50,3163 @@ timer@8000000 { status =3D "disabled"; }; =20 + aconnect@9000000 { + compatible =3D "nvidia,tegra264-aconnect", + "nvidia,tegra210-aconnect"; + clocks =3D <&bpmp TEGRA264_CLK_APE>, + <&bpmp TEGRA264_CLK_ADSP>; + clock-names =3D "ape", "apb2ape"; + power-domains =3D <&bpmp TEGRA264_POWER_DOMAIN_AUD>; + status =3D "disabled"; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x0 0x9000000 0x0 0x9000000 0x0 0x2000000>; + + adma: dma-controller@9440000 { + compatible =3D "nvidia,tegra264-adma"; + reg =3D <0x0 0x9440000 0x0 0xb0000>; + interrupt-parent =3D <&agic_page0>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + #dma-cells =3D <1>; + clocks =3D <&bpmp TEGRA264_CLK_AHUB>; + clock-names =3D "d_audio"; + status =3D "disabled"; + }; + + tegra_ahub: ahub@9630000 { + compatible =3D "nvidia,tegra264-ahub"; + reg =3D <0x0 0x9630000 0x0 0x10000>; + clocks =3D <&bpmp TEGRA264_CLK_AHUB>; + clock-names =3D "ahub"; + assigned-clocks =3D <&bpmp TEGRA264_CLK_AHUB>; + assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLAON_APE>; + status =3D "disabled"; + + #address-cells =3D <2>; + #size-cells =3D <2>; + /* ADMA is under AHUB range, its excluded in the defined range */ + ranges =3D <0x0 0x9280000 0x0 0x9280000 0x0 0x1c0000>, + <0x0 0x9510000 0x0 0x9510000 0x0 0x370000>; + + tegra_i2s1: i2s@9280000 { + compatible =3D "nvidia,tegra264-i2s"; + reg =3D <0x0 0x9280000 0x0 0x10000>; + clocks =3D <&bpmp TEGRA264_CLK_I2S1>, + <&bpmp TEGRA264_CLK_I2S1_SCLK_IN>; + clock-names =3D "i2s", "sync_input"; + assigned-clocks =3D <&bpmp TEGRA264_CLK_I2S1>; + assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates =3D <1536000>; + sound-name-prefix =3D "I2S1"; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + i2s1_cif: endpoint { + remote-endpoint =3D <&xbar_i2s1>; + }; + }; + + i2s1_port: port@1 { + reg =3D <1>; + + i2s1_dap: endpoint { + dai-format =3D "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_i2s2: i2s@9290000 { + compatible =3D "nvidia,tegra264-i2s"; + reg =3D <0x0 0x9290000 0x0 0x10000>; + clocks =3D <&bpmp TEGRA264_CLK_I2S2>, + <&bpmp TEGRA264_CLK_I2S2_SCLK_IN>; + clock-names =3D "i2s", "sync_input"; + assigned-clocks =3D <&bpmp TEGRA264_CLK_I2S2>; + assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates =3D <1536000>; + sound-name-prefix =3D "I2S2"; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + i2s2_cif: endpoint { + remote-endpoint =3D <&xbar_i2s2>; + }; + }; + + i2s2_port: port@1 { + reg =3D <1>; + + i2s2_dap: endpoint { + dai-format =3D "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_i2s3: i2s@92a0000 { + compatible =3D "nvidia,tegra264-i2s"; + reg =3D <0x0 0x92a0000 0x0 0x10000>; + clocks =3D <&bpmp TEGRA264_CLK_I2S3>, + <&bpmp TEGRA264_CLK_I2S3_SCLK_IN>; + clock-names =3D "i2s", "sync_input"; + assigned-clocks =3D <&bpmp TEGRA264_CLK_I2S3>; + assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates =3D <1536000>; + sound-name-prefix =3D "I2S3"; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + i2s3_cif: endpoint { + remote-endpoint =3D <&xbar_i2s3>; + }; + }; + + i2s3_port: port@1 { + reg =3D <1>; + + i2s3_dap: endpoint { + dai-format =3D "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_i2s4: i2s@92b0000 { + compatible =3D "nvidia,tegra264-i2s"; + reg =3D <0x0 0x92b0000 0x0 0x10000>; + clocks =3D <&bpmp TEGRA264_CLK_I2S4>, + <&bpmp TEGRA264_CLK_I2S4_SCLK_IN>; + clock-names =3D "i2s", "sync_input"; + assigned-clocks =3D <&bpmp TEGRA264_CLK_I2S4>; + assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates =3D <1536000>; + sound-name-prefix =3D "I2S4"; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + i2s4_cif: endpoint { + remote-endpoint =3D <&xbar_i2s4>; + }; + }; + + i2s4_port: port@1 { + reg =3D <1>; + + i2s4_dap: endpoint { + dai-format =3D "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_i2s5: i2s@92c0000 { + compatible =3D "nvidia,tegra264-i2s"; + reg =3D <0x0 0x92c0000 0x0 0x10000>; + clocks =3D <&bpmp TEGRA264_CLK_I2S5>, + <&bpmp TEGRA264_CLK_I2S5_SCLK_IN>; + clock-names =3D "i2s", "sync_input"; + assigned-clocks =3D <&bpmp TEGRA264_CLK_I2S5>; + assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates =3D <1536000>; + sound-name-prefix =3D "I2S5"; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + i2s5_cif: endpoint { + remote-endpoint =3D <&xbar_i2s5>; + }; + }; + + i2s5_port: port@1 { + reg =3D <1>; + + i2s5_dap: endpoint { + dai-format =3D "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_i2s6: i2s@92d0000 { + compatible =3D "nvidia,tegra264-i2s"; + reg =3D <0x0 0x92d0000 0x0 0x10000>; + clocks =3D <&bpmp TEGRA264_CLK_I2S6>, + <&bpmp TEGRA264_CLK_I2S6_SCLK_IN>; + clock-names =3D "i2s", "sync_input"; + assigned-clocks =3D <&bpmp TEGRA264_CLK_I2S6>; + assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates =3D <1536000>; + sound-name-prefix =3D "I2S6"; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + i2s6_cif: endpoint { + remote-endpoint =3D <&xbar_i2s6>; + }; + }; + + i2s6_port: port@1 { + reg =3D <1>; + + i2s6_dap: endpoint { + dai-format =3D "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_i2s7: i2s@92e0000 { + compatible =3D "nvidia,tegra264-i2s"; + reg =3D <0x0 0x92e0000 0x0 0x10000>; + clocks =3D <&bpmp TEGRA264_CLK_I2S7>, + <&bpmp TEGRA264_CLK_I2S7_SCLK_IN>; + clock-names =3D "i2s", "sync_input"; + assigned-clocks =3D <&bpmp TEGRA264_CLK_I2S7>; + assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates =3D <1536000>; + sound-name-prefix =3D "I2S7"; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + i2s7_cif: endpoint { + remote-endpoint =3D <&xbar_i2s7>; + }; + }; + + i2s7_port: port@1 { + reg =3D <1>; + + i2s7_dap: endpoint { + dai-format =3D "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_i2s8: i2s@92f0000 { + compatible =3D "nvidia,tegra264-i2s"; + reg =3D <0x0 0x92f0000 0x0 0x10000>; + clocks =3D <&bpmp TEGRA264_CLK_I2S8>, + <&bpmp TEGRA264_CLK_I2S8_SCLK_IN>; + clock-names =3D "i2s", "sync_input"; + assigned-clocks =3D <&bpmp TEGRA264_CLK_I2S8>; + assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates =3D <1536000>; + sound-name-prefix =3D "I2S8"; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + i2s8_cif: endpoint { + remote-endpoint =3D <&xbar_i2s8>; + }; + }; + + i2s8_port: port@1 { + reg =3D <1>; + + i2s8_dap: endpoint { + dai-format =3D "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_dmic1: dmic@9300000 { + compatible =3D "nvidia,tegra264-dmic", + "nvidia,tegra210-dmic"; + reg =3D <0x0 0x9300000 0x0 0x10000>; + clocks =3D <&bpmp TEGRA264_CLK_DMIC1>; + clock-names =3D "dmic"; + assigned-clocks =3D <&bpmp TEGRA264_CLK_DMIC1>; + assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates =3D <3072000>; + sound-name-prefix =3D "DMIC1"; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dmic1_cif: endpoint { + remote-endpoint =3D <&xbar_dmic1>; + }; + }; + + dmic1_port: port@1 { + reg =3D <1>; + + dmic1_dap: endpoint { + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_dmic2: dmic@9310000 { + compatible =3D "nvidia,tegra264-dmic", + "nvidia,tegra210-dmic"; + reg =3D <0x0 0x9310000 0x0 0x10000>; + clocks =3D <&bpmp TEGRA264_CLK_DMIC1>; + clock-names =3D "dmic"; + assigned-clocks =3D <&bpmp TEGRA264_CLK_DMIC1>; + assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates =3D <3072000>; + sound-name-prefix =3D "DMIC2"; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dmic2_cif: endpoint { + remote-endpoint =3D <&xbar_dmic2>; + }; + }; + + dmic2_port: port@1 { + reg =3D <1>; + + dmic2_dap: endpoint { + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_dspk1: dspk@9380000 { + compatible =3D "nvidia,tegra264-dspk", + "nvidia,tegra186-dspk"; + reg =3D <0x0 0x9380000 0x0 0x10000>; + clocks =3D <&bpmp TEGRA264_CLK_DSPK1>; + clock-names =3D "dspk"; + assigned-clocks =3D <&bpmp TEGRA264_CLK_DSPK1>; + assigned-clock-parents =3D <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + assigned-clock-rates =3D <12288000>; + sound-name-prefix =3D "DSPK1"; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dspk1_cif: endpoint { + remote-endpoint =3D <&xbar_dspk1>; + }; + }; + + dspk1_port: port@1 { + reg =3D <1>; + + dspk1_dap: endpoint { + /* placeholder for external codec */ + }; + }; + }; + }; + + tegra_amx1: amx@9510000 { + compatible =3D "nvidia,tegra264-amx"; + reg =3D <0x0 0x9510000 0x0 0x10000>; + sound-name-prefix =3D "AMX1"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + amx1_in1: endpoint { + remote-endpoint =3D <&xbar_amx1_in1>; + }; + }; + + port@1 { + reg =3D <1>; + + amx1_in2: endpoint { + remote-endpoint =3D <&xbar_amx1_in2>; + }; + }; + + port@2 { + reg =3D <2>; + + amx1_in3: endpoint { + remote-endpoint =3D <&xbar_amx1_in3>; + }; + }; + + port@3 { + reg =3D <3>; + + amx1_in4: endpoint { + remote-endpoint =3D <&xbar_amx1_in4>; + }; + }; + + amx1_out_port: port@4 { + reg =3D <4>; + + amx1_out: endpoint { + remote-endpoint =3D <&xbar_amx1_out>; + }; + }; + }; + }; + + tegra_amx2: amx@9520000 { + compatible =3D "nvidia,tegra264-amx"; + reg =3D <0x0 0x9520000 0x0 0x10000>; + sound-name-prefix =3D "AMX2"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + amx2_in1: endpoint { + remote-endpoint =3D <&xbar_amx2_in1>; + }; + }; + + port@1 { + reg =3D <1>; + + amx2_in2: endpoint { + remote-endpoint =3D <&xbar_amx2_in2>; + }; + }; + + port@2 { + reg =3D <2>; + + amx2_in3: endpoint { + remote-endpoint =3D <&xbar_amx2_in3>; + }; + }; + + port@3 { + reg =3D <3>; + + amx2_in4: endpoint { + remote-endpoint =3D <&xbar_amx2_in4>; + }; + }; + + amx2_out_port: port@4 { + reg =3D <4>; + + amx2_out: endpoint { + remote-endpoint =3D <&xbar_amx2_out>; + }; + }; + }; + }; + + tegra_amx3: amx@9530000 { + compatible =3D "nvidia,tegra264-amx"; + reg =3D <0x0 0x9530000 0x0 0x10000>; + sound-name-prefix =3D "AMX3"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + amx3_in1: endpoint { + remote-endpoint =3D <&xbar_amx3_in1>; + }; + }; + + port@1 { + reg =3D <1>; + + amx3_in2: endpoint { + remote-endpoint =3D <&xbar_amx3_in2>; + }; + }; + + port@2 { + reg =3D <2>; + + amx3_in3: endpoint { + remote-endpoint =3D <&xbar_amx3_in3>; + }; + }; + + port@3 { + reg =3D <3>; + + amx3_in4: endpoint { + remote-endpoint =3D <&xbar_amx3_in4>; + }; + }; + + amx3_out_port: port@4 { + reg =3D <4>; + + amx3_out: endpoint { + remote-endpoint =3D <&xbar_amx3_out>; + }; + }; + }; + }; + + tegra_amx4: amx@9540000 { + compatible =3D "nvidia,tegra264-amx"; + reg =3D <0x0 0x9540000 0x0 0x10000>; + sound-name-prefix =3D "AMX4"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + amx4_in1: endpoint { + remote-endpoint =3D <&xbar_amx4_in1>; + }; + }; + + port@1 { + reg =3D <1>; + + amx4_in2: endpoint { + remote-endpoint =3D <&xbar_amx4_in2>; + }; + }; + + port@2 { + reg =3D <2>; + + amx4_in3: endpoint { + remote-endpoint =3D <&xbar_amx4_in3>; + }; + }; + + port@3 { + reg =3D <3>; + + amx4_in4: endpoint { + remote-endpoint =3D <&xbar_amx4_in4>; + }; + }; + + amx4_out_port: port@4 { + reg =3D <4>; + + amx4_out: endpoint { + remote-endpoint =3D <&xbar_amx4_out>; + }; + }; + }; + }; + + tegra_amx5: amx@9550000 { + compatible =3D "nvidia,tegra264-amx"; + reg =3D <0x0 0x9550000 0x0 0x10000>; + sound-name-prefix =3D "AMX5"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + amx5_in1: endpoint { + remote-endpoint =3D <&xbar_amx5_in1>; + }; + }; + + port@1 { + reg =3D <1>; + + amx5_in2: endpoint { + remote-endpoint =3D <&xbar_amx5_in2>; + }; + }; + + port@2 { + reg =3D <2>; + + amx5_in3: endpoint { + remote-endpoint =3D <&xbar_amx5_in3>; + }; + }; + + port@3 { + reg =3D <3>; + + amx5_in4: endpoint { + remote-endpoint =3D <&xbar_amx5_in4>; + }; + }; + + amx5_out_port: port@4 { + reg =3D <4>; + + amx5_out: endpoint { + remote-endpoint =3D <&xbar_amx5_out>; + }; + }; + }; + }; + + tegra_amx6: amx@9560000 { + compatible =3D "nvidia,tegra264-amx"; + reg =3D <0x0 0x9560000 0x0 0x10000>; + sound-name-prefix =3D "AMX6"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + amx6_in1: endpoint { + remote-endpoint =3D <&xbar_amx6_in1>; + }; + }; + + port@1 { + reg =3D <1>; + + amx6_in2: endpoint { + remote-endpoint =3D <&xbar_amx6_in2>; + }; + }; + + port@2 { + reg =3D <2>; + + amx6_in3: endpoint { + remote-endpoint =3D <&xbar_amx6_in3>; + }; + }; + + port@3 { + reg =3D <3>; + + amx6_in4: endpoint { + remote-endpoint =3D <&xbar_amx6_in4>; + }; + }; + + amx6_out_port: port@4 { + reg =3D <4>; + + amx6_out: endpoint { + remote-endpoint =3D <&xbar_amx6_out>; + }; + }; + }; + }; + + tegra_adx1: adx@9590000 { + compatible =3D "nvidia,tegra264-adx"; + reg =3D <0x0 0x9590000 0x0 0x10000>; + sound-name-prefix =3D "ADX1"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + adx1_in: endpoint { + remote-endpoint =3D <&xbar_adx1_in>; + }; + }; + + adx1_out1_port: port@1 { + reg =3D <1>; + + adx1_out1: endpoint { + remote-endpoint =3D <&xbar_adx1_out1>; + }; + }; + + adx1_out2_port: port@2 { + reg =3D <2>; + + adx1_out2: endpoint { + remote-endpoint =3D <&xbar_adx1_out2>; + }; + }; + + adx1_out3_port: port@3 { + reg =3D <3>; + + adx1_out3: endpoint { + remote-endpoint =3D <&xbar_adx1_out3>; + }; + }; + + adx1_out4_port: port@4 { + reg =3D <4>; + + adx1_out4: endpoint { + remote-endpoint =3D <&xbar_adx1_out4>; + }; + }; + }; + }; + + tegra_adx2: adx@95a0000 { + compatible =3D "nvidia,tegra264-adx"; + reg =3D <0x0 0x95a0000 0x0 0x10000>; + sound-name-prefix =3D "ADX2"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + adx2_in: endpoint { + remote-endpoint =3D <&xbar_adx2_in>; + }; + }; + + adx2_out1_port: port@1 { + reg =3D <1>; + + adx2_out1: endpoint { + remote-endpoint =3D <&xbar_adx2_out1>; + }; + }; + + adx2_out2_port: port@2 { + reg =3D <2>; + + adx2_out2: endpoint { + remote-endpoint =3D <&xbar_adx2_out2>; + }; + }; + + adx2_out3_port: port@3 { + reg =3D <3>; + + adx2_out3: endpoint { + remote-endpoint =3D <&xbar_adx2_out3>; + }; + }; + + adx2_out4_port: port@4 { + reg =3D <4>; + + adx2_out4: endpoint { + remote-endpoint =3D <&xbar_adx2_out4>; + }; + }; + }; + }; + + tegra_adx3: adx@95b0000 { + compatible =3D "nvidia,tegra264-adx"; + reg =3D <0x0 0x95b0000 0x0 0x10000>; + sound-name-prefix =3D "ADX3"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + adx3_in: endpoint { + remote-endpoint =3D <&xbar_adx3_in>; + }; + }; + + adx3_out1_port: port@1 { + reg =3D <1>; + + adx3_out1: endpoint { + remote-endpoint =3D <&xbar_adx3_out1>; + }; + }; + + adx3_out2_port: port@2 { + reg =3D <2>; + + adx3_out2: endpoint { + remote-endpoint =3D <&xbar_adx3_out2>; + }; + }; + + adx3_out3_port: port@3 { + reg =3D <3>; + + adx3_out3: endpoint { + remote-endpoint =3D <&xbar_adx3_out3>; + }; + }; + + adx3_out4_port: port@4 { + reg =3D <4>; + + adx3_out4: endpoint { + remote-endpoint =3D <&xbar_adx3_out4>; + }; + }; + }; + }; + + tegra_adx4: adx@95c0000 { + compatible =3D "nvidia,tegra264-adx"; + reg =3D <0x0 0x95c0000 0x0 0x10000>; + sound-name-prefix =3D "ADX4"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + adx4_in: endpoint { + remote-endpoint =3D <&xbar_adx4_in>; + }; + }; + + adx4_out1_port: port@1 { + reg =3D <1>; + + adx4_out1: endpoint { + remote-endpoint =3D <&xbar_adx4_out1>; + }; + }; + + adx4_out2_port: port@2 { + reg =3D <2>; + + adx4_out2: endpoint { + remote-endpoint =3D <&xbar_adx4_out2>; + }; + }; + + adx4_out3_port: port@3 { + reg =3D <3>; + + adx4_out3: endpoint { + remote-endpoint =3D <&xbar_adx4_out3>; + }; + }; + + adx4_out4_port: port@4 { + reg =3D <4>; + + adx4_out4: endpoint { + remote-endpoint =3D <&xbar_adx4_out4>; + }; + }; + }; + }; + + tegra_adx5: adx@95d0000 { + compatible =3D "nvidia,tegra264-adx"; + reg =3D <0x0 0x95d0000 0x0 0x10000>; + sound-name-prefix =3D "ADX5"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + adx5_in: endpoint { + remote-endpoint =3D <&xbar_adx5_in>; + }; + }; + + adx5_out1_port: port@1 { + reg =3D <1>; + + adx5_out1: endpoint { + remote-endpoint =3D <&xbar_adx5_out1>; + }; + }; + + adx5_out2_port: port@2 { + reg =3D <2>; + + adx5_out2: endpoint { + remote-endpoint =3D <&xbar_adx5_out2>; + }; + }; + + adx5_out3_port: port@3 { + reg =3D <3>; + + adx5_out3: endpoint { + remote-endpoint =3D <&xbar_adx5_out3>; + }; + }; + + adx5_out4_port: port@4 { + reg =3D <4>; + + adx5_out4: endpoint { + remote-endpoint =3D <&xbar_adx5_out4>; + }; + }; + }; + }; + + tegra_adx6: adx@95e0000 { + compatible =3D "nvidia,tegra264-adx"; + reg =3D <0x0 0x95e0000 0x0 0x10000>; + sound-name-prefix =3D "ADX6"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + adx6_in: endpoint { + remote-endpoint =3D <&xbar_adx6_in>; + }; + }; + + adx6_out1_port: port@1 { + reg =3D <1>; + + adx6_out1: endpoint { + remote-endpoint =3D <&xbar_adx6_out1>; + }; + }; + + adx6_out2_port: port@2 { + reg =3D <2>; + + adx6_out2: endpoint { + remote-endpoint =3D <&xbar_adx6_out2>; + }; + }; + + adx6_out3_port: port@3 { + reg =3D <3>; + + adx6_out3: endpoint { + remote-endpoint =3D <&xbar_adx6_out3>; + }; + }; + + adx6_out4_port: port@4 { + reg =3D <4>; + + adx6_out4: endpoint { + remote-endpoint =3D <&xbar_adx6_out4>; + }; + }; + }; + }; + + tegra_admaif: admaif@9610000 { + compatible =3D "nvidia,tegra264-admaif"; + reg =3D <0x0 0x9610000 0x0 0x10000>; + dmas =3D <&adma 1>, <&adma 1>, + <&adma 2>, <&adma 2>, + <&adma 3>, <&adma 3>, + <&adma 4>, <&adma 4>, + <&adma 5>, <&adma 5>, + <&adma 6>, <&adma 6>, + <&adma 7>, <&adma 7>, + <&adma 8>, <&adma 8>, + <&adma 9>, <&adma 9>, + <&adma 10>, <&adma 10>, + <&adma 11>, <&adma 11>, + <&adma 12>, <&adma 12>, + <&adma 13>, <&adma 13>, + <&adma 14>, <&adma 14>, + <&adma 15>, <&adma 15>, + <&adma 16>, <&adma 16>, + <&adma 17>, <&adma 17>, + <&adma 18>, <&adma 18>, + <&adma 19>, <&adma 19>, + <&adma 20>, <&adma 20>, + <&adma 21>, <&adma 21>, + <&adma 22>, <&adma 22>, + <&adma 23>, <&adma 23>, + <&adma 24>, <&adma 24>, + <&adma 25>, <&adma 25>, + <&adma 26>, <&adma 26>, + <&adma 27>, <&adma 27>, + <&adma 28>, <&adma 28>, + <&adma 29>, <&adma 29>, + <&adma 30>, <&adma 30>, + <&adma 31>, <&adma 31>, + <&adma 32>, <&adma 32>; + dma-names =3D "rx1", "tx1", + "rx2", "tx2", + "rx3", "tx3", + "rx4", "tx4", + "rx5", "tx5", + "rx6", "tx6", + "rx7", "tx7", + "rx8", "tx8", + "rx9", "tx9", + "rx10", "tx10", + "rx11", "tx11", + "rx12", "tx12", + "rx13", "tx13", + "rx14", "tx14", + "rx15", "tx15", + "rx16", "tx16", + "rx17", "tx17", + "rx18", "tx18", + "rx19", "tx19", + "rx20", "tx20", + "rx21", "tx21", + "rx22", "tx22", + "rx23", "tx23", + "rx24", "tx24", + "rx25", "tx25", + "rx26", "tx26", + "rx27", "tx27", + "rx28", "tx28", + "rx29", "tx29", + "rx30", "tx30", + "rx31", "tx31", + "rx32", "tx32"; + + interconnects =3D + <&mc TEGRA264_MEMORY_CLIENT_APEDMAR &emc>, + <&mc TEGRA264_MEMORY_CLIENT_APEDMAW &emc>; + interconnect-names =3D "dma-mem", "write"; + + iommus =3D <&smmu1 TEGRA264_SID_APE>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + admaif0_port: port@0 { + reg =3D <0x0>; + + admaif0: endpoint { + remote-endpoint =3D <&xbar_admaif0>; + }; + }; + + admaif1_port: port@1 { + reg =3D <0x1>; + + admaif1: endpoint { + remote-endpoint =3D <&xbar_admaif1>; + }; + }; + + admaif2_port: port@2 { + reg =3D <0x2>; + + admaif2: endpoint { + remote-endpoint =3D <&xbar_admaif2>; + }; + }; + + admaif3_port: port@3 { + reg =3D <0x3>; + + admaif3: endpoint { + remote-endpoint =3D <&xbar_admaif3>; + }; + }; + + admaif4_port: port@4 { + reg =3D <0x4>; + + admaif4: endpoint { + remote-endpoint =3D <&xbar_admaif4>; + }; + }; + + admaif5_port: port@5 { + reg =3D <0x5>; + + admaif5: endpoint { + remote-endpoint =3D <&xbar_admaif5>; + }; + }; + + admaif6_port: port@6 { + reg =3D <0x6>; + + admaif6: endpoint { + remote-endpoint =3D <&xbar_admaif6>; + }; + }; + + admaif7_port: port@7 { + reg =3D <0x7>; + + admaif7: endpoint { + remote-endpoint =3D <&xbar_admaif7>; + }; + }; + + admaif8_port: port@8 { + reg =3D <0x8>; + + admaif8: endpoint { + remote-endpoint =3D <&xbar_admaif8>; + }; + }; + + admaif9_port: port@9 { + reg =3D <0x9>; + + admaif9: endpoint { + remote-endpoint =3D <&xbar_admaif9>; + }; + }; + + admaif10_port: port@a { + reg =3D <0xa>; + + admaif10: endpoint { + remote-endpoint =3D <&xbar_admaif10>; + }; + }; + + admaif11_port: port@b { + reg =3D <0xb>; + + admaif11: endpoint { + remote-endpoint =3D <&xbar_admaif11>; + }; + }; + + admaif12_port: port@c { + reg =3D <0xc>; + + admaif12: endpoint { + remote-endpoint =3D <&xbar_admaif12>; + }; + }; + + admaif13_port: port@d { + reg =3D <0xd>; + + admaif13: endpoint { + remote-endpoint =3D <&xbar_admaif13>; + }; + }; + + admaif14_port: port@e { + reg =3D <0xe>; + + admaif14: endpoint { + remote-endpoint =3D <&xbar_admaif14>; + }; + }; + + admaif15_port: port@f { + reg =3D <0xf>; + + admaif15: endpoint { + remote-endpoint =3D <&xbar_admaif15>; + }; + }; + + admaif16_port: port@10 { + reg =3D <0x10>; + + admaif16: endpoint { + remote-endpoint =3D <&xbar_admaif16>; + }; + }; + + admaif17_port: port@11 { + reg =3D <0x11>; + + admaif17: endpoint { + remote-endpoint =3D <&xbar_admaif17>; + }; + }; + + admaif18_port: port@12 { + reg =3D <0x12>; + + admaif18: endpoint { + remote-endpoint =3D <&xbar_admaif18>; + }; + }; + + admaif19_port: port@13 { + reg =3D <0x13>; + + admaif19: endpoint { + remote-endpoint =3D <&xbar_admaif19>; + }; + }; + + admaif20_port: port@14 { + reg =3D <0x14>; + + admaif20: endpoint { + remote-endpoint =3D <&xbar_admaif20>; + }; + }; + + admaif21_port: port@15 { + reg =3D <0x15>; + + admaif21: endpoint { + remote-endpoint =3D <&xbar_admaif21>; + }; + }; + + admaif22_port: port@16 { + reg =3D <0x16>; + + admaif22: endpoint { + remote-endpoint =3D <&xbar_admaif22>; + }; + }; + + admaif23_port: port@17 { + reg =3D <0x17>; + + admaif23: endpoint { + remote-endpoint =3D <&xbar_admaif23>; + }; + }; + + admaif24_port: port@18 { + reg =3D <0x18>; + + admaif24: endpoint { + remote-endpoint =3D <&xbar_admaif24>; + }; + }; + + admaif25_port: port@19 { + reg =3D <0x19>; + + admaif25: endpoint { + remote-endpoint =3D <&xbar_admaif25>; + }; + }; + + admaif26_port: port@1a { + reg =3D <0x1a>; + + admaif26: endpoint { + remote-endpoint =3D <&xbar_admaif26>; + }; + }; + + admaif27_port: port@1b { + reg =3D <0x1b>; + + admaif27: endpoint { + remote-endpoint =3D <&xbar_admaif27>; + }; + }; + + admaif28_port: port@1c { + reg =3D <0x1c>; + + admaif28: endpoint { + remote-endpoint =3D <&xbar_admaif28>; + }; + }; + + admaif29_port: port@1d { + reg =3D <0x1d>; + + admaif29: endpoint { + remote-endpoint =3D <&xbar_admaif29>; + }; + }; + + admaif30_port: port@1e { + reg =3D <0x1e>; + + admaif30: endpoint { + remote-endpoint =3D <&xbar_admaif30>; + }; + }; + + admaif31_port: port@1f { + reg =3D <0x1f>; + + admaif31: endpoint { + remote-endpoint =3D <&xbar_admaif31>; + }; + }; + }; + }; + + tegra_sfc1: sfc@9700000 { + compatible =3D "nvidia,tegra264-sfc", + "nvidia,tegra210-sfc"; + reg =3D <0x0 0x9700000 0x0 0x10000>; + sound-name-prefix =3D "SFC1"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + sfc1_cif_in: endpoint { + remote-endpoint =3D <&xbar_sfc1_in>; + }; + }; + + sfc1_out_port: port@1 { + reg =3D <1>; + + sfc1_cif_out: endpoint { + remote-endpoint =3D <&xbar_sfc1_out>; + }; + }; + }; + }; + + tegra_sfc2: sfc@9710000 { + compatible =3D "nvidia,tegra264-sfc", + "nvidia,tegra210-sfc"; + reg =3D <0x0 0x9710000 0x0 0x10000>; + sound-name-prefix =3D "SFC2"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + sfc2_cif_in: endpoint { + remote-endpoint =3D <&xbar_sfc2_in>; + }; + }; + + sfc2_out_port: port@1 { + reg =3D <1>; + + sfc2_cif_out: endpoint { + remote-endpoint =3D <&xbar_sfc2_out>; + }; + }; + }; + }; + + tegra_sfc3: sfc@9720000 { + compatible =3D "nvidia,tegra264-sfc", + "nvidia,tegra210-sfc"; + reg =3D <0x0 0x9720000 0x0 0x10000>; + sound-name-prefix =3D "SFC3"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + sfc3_cif_in: endpoint { + remote-endpoint =3D <&xbar_sfc3_in>; + }; + }; + + sfc3_out_port: port@1 { + reg =3D <1>; + + sfc3_cif_out: endpoint { + remote-endpoint =3D <&xbar_sfc3_out>; + }; + }; + }; + }; + + tegra_sfc4: sfc@9730000 { + compatible =3D "nvidia,tegra264-sfc", + "nvidia,tegra210-sfc"; + reg =3D <0x0 0x9730000 0x0 0x10000>; + sound-name-prefix =3D "SFC4"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + sfc4_cif_in: endpoint { + remote-endpoint =3D <&xbar_sfc4_in>; + }; + }; + + sfc4_out_port: port@1 { + reg =3D <1>; + + sfc4_cif_out: endpoint { + remote-endpoint =3D <&xbar_sfc4_out>; + }; + }; + }; + }; + + tegra_ope1: processing-engine@9780000 { + compatible =3D "nvidia,tegra264-ope", + "nvidia,tegra210-ope"; + reg =3D <0x0 0x9780000 0x0 0x10000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges =3D <0x0 0x9780000 0x0 0x9780000 0x0 0x30000>; + sound-name-prefix =3D "OPE1"; + + equalizer@9790000 { + compatible =3D "nvidia,tegra264-peq", + "nvidia,tegra210-peq"; + reg =3D <0x0 0x9790000 0x0 0x10000>; + }; + + dynamic-range-compressor@97a0000 { + compatible =3D "nvidia,tegra264-mbdrc", + "nvidia,tegra210-mbdrc"; + reg =3D <0x0 0x97a0000 0x0 0x10000>; + }; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0x0>; + + ope1_cif_in_ep: endpoint { + remote-endpoint =3D + <&xbar_ope1_in_ep>; + }; + }; + + ope1_out_port: port@1 { + reg =3D <0x1>; + + ope1_cif_out_ep: endpoint { + remote-endpoint =3D + <&xbar_ope1_out_ep>; + }; + }; + }; + }; + + tegra_mvc1: mvc@9800000 { + compatible =3D "nvidia,tegra264-mvc", + "nvidia,tegra210-mvc"; + reg =3D <0x0 0x9800000 0x0 0x10000>; + sound-name-prefix =3D "MVC1"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mvc1_cif_in: endpoint { + remote-endpoint =3D <&xbar_mvc1_in>; + }; + }; + + mvc1_out_port: port@1 { + reg =3D <1>; + + mvc1_cif_out: endpoint { + remote-endpoint =3D <&xbar_mvc1_out>; + }; + }; + }; + }; + + tegra_mvc2: mvc@9810000 { + compatible =3D "nvidia,tegra264-mvc", + "nvidia,tegra210-mvc"; + reg =3D <0x0 0x9810000 0x0 0x10000>; + sound-name-prefix =3D "MVC2"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mvc2_cif_in: endpoint { + remote-endpoint =3D <&xbar_mvc2_in>; + }; + }; + + mvc2_out_port: port@1 { + reg =3D <1>; + + mvc2_cif_out: endpoint { + remote-endpoint =3D <&xbar_mvc2_out>; + }; + }; + }; + }; + + tegra_amixer: amixer@9820000 { + compatible =3D "nvidia,tegra264-amixer", + "nvidia,tegra210-amixer"; + reg =3D <0x0 0x9820000 0x0 0x10000>; + sound-name-prefix =3D "MIXER1"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0x0>; + + mix_in1: endpoint { + remote-endpoint =3D <&xbar_mix_in1>; + }; + }; + + port@1 { + reg =3D <0x1>; + + mix_in2: endpoint { + remote-endpoint =3D <&xbar_mix_in2>; + }; + }; + + port@2 { + reg =3D <0x2>; + + mix_in3: endpoint { + remote-endpoint =3D <&xbar_mix_in3>; + }; + }; + + port@3 { + reg =3D <0x3>; + + mix_in4: endpoint { + remote-endpoint =3D <&xbar_mix_in4>; + }; + }; + + port@4 { + reg =3D <0x4>; + + mix_in5: endpoint { + remote-endpoint =3D <&xbar_mix_in5>; + }; + }; + + port@5 { + reg =3D <0x5>; + + mix_in6: endpoint { + remote-endpoint =3D <&xbar_mix_in6>; + }; + }; + + port@6 { + reg =3D <0x6>; + + mix_in7: endpoint { + remote-endpoint =3D <&xbar_mix_in7>; + }; + }; + + port@7 { + reg =3D <0x7>; + + mix_in8: endpoint { + remote-endpoint =3D <&xbar_mix_in8>; + }; + }; + + port@8 { + reg =3D <0x8>; + + mix_in9: endpoint { + remote-endpoint =3D <&xbar_mix_in9>; + }; + }; + + port@9 { + reg =3D <0x9>; + + mix_in10: endpoint { + remote-endpoint =3D <&xbar_mix_in10>; + }; + }; + + mix_out1_port: port@a { + reg =3D <0xa>; + + mix_out1: endpoint { + remote-endpoint =3D <&xbar_mix_out1>; + }; + }; + + mix_out2_port: port@b { + reg =3D <0xb>; + + mix_out2: endpoint { + remote-endpoint =3D <&xbar_mix_out2>; + }; + }; + + mix_out3_port: port@c { + reg =3D <0xc>; + + mix_out3: endpoint { + remote-endpoint =3D <&xbar_mix_out3>; + }; + }; + + mix_out4_port: port@d { + reg =3D <0xd>; + + mix_out4: endpoint { + remote-endpoint =3D <&xbar_mix_out4>; + }; + }; + + mix_out5_port: port@e { + reg =3D <0xe>; + + mix_out5: endpoint { + remote-endpoint =3D <&xbar_mix_out5>; + }; + }; + }; + }; + + tegra_asrc: asrc@9850000 { + compatible =3D "nvidia,tegra264-asrc"; + reg =3D <0x0 0x9850000 0x0 0x10000>; + sound-name-prefix =3D "ASRC1"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0x0>; + + asrc_in1_ep: endpoint { + remote-endpoint =3D + <&xbar_asrc_in1_ep>; + }; + }; + + port@1 { + reg =3D <0x1>; + + asrc_in2_ep: endpoint { + remote-endpoint =3D + <&xbar_asrc_in2_ep>; + }; + }; + + port@2 { + reg =3D <0x2>; + + asrc_in3_ep: endpoint { + remote-endpoint =3D + <&xbar_asrc_in3_ep>; + }; + }; + + port@3 { + reg =3D <0x3>; + + asrc_in4_ep: endpoint { + remote-endpoint =3D + <&xbar_asrc_in4_ep>; + }; + }; + + port@4 { + reg =3D <0x4>; + + asrc_in5_ep: endpoint { + remote-endpoint =3D + <&xbar_asrc_in5_ep>; + }; + }; + + port@5 { + reg =3D <0x5>; + + asrc_in6_ep: endpoint { + remote-endpoint =3D + <&xbar_asrc_in6_ep>; + }; + }; + + port@6 { + reg =3D <0x6>; + + asrc_in7_ep: endpoint { + remote-endpoint =3D + <&xbar_asrc_in7_ep>; + }; + }; + + asrc_out1_port: port@7 { + reg =3D <0x7>; + + asrc_out1_ep: endpoint { + remote-endpoint =3D + <&xbar_asrc_out1_ep>; + }; + }; + + asrc_out2_port: port@8 { + reg =3D <0x8>; + + asrc_out2_ep: endpoint { + remote-endpoint =3D + <&xbar_asrc_out2_ep>; + }; + }; + + asrc_out3_port: port@9 { + reg =3D <0x9>; + + asrc_out3_ep: endpoint { + remote-endpoint =3D + <&xbar_asrc_out3_ep>; + }; + }; + + asrc_out4_port: port@a { + reg =3D <0xa>; + + asrc_out4_ep: endpoint { + remote-endpoint =3D + <&xbar_asrc_out4_ep>; + }; + }; + + asrc_out5_port: port@b { + reg =3D <0xb>; + + asrc_out5_ep: endpoint { + remote-endpoint =3D + <&xbar_asrc_out5_ep>; + }; + }; + + asrc_out6_port: port@c { + reg =3D <0xc>; + + asrc_out6_ep: endpoint { + remote-endpoint =3D + <&xbar_asrc_out6_ep>; + }; + }; + }; + }; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0x0>; + + xbar_admaif0: endpoint { + remote-endpoint =3D <&admaif0>; + }; + }; + + port@1 { + reg =3D <0x1>; + + xbar_admaif1: endpoint { + remote-endpoint =3D <&admaif1>; + }; + }; + + port@2 { + reg =3D <0x2>; + + xbar_admaif2: endpoint { + remote-endpoint =3D <&admaif2>; + }; + }; + + port@3 { + reg =3D <0x3>; + + xbar_admaif3: endpoint { + remote-endpoint =3D <&admaif3>; + }; + }; + + port@4 { + reg =3D <0x4>; + + xbar_admaif4: endpoint { + remote-endpoint =3D <&admaif4>; + }; + }; + + port@5 { + reg =3D <0x5>; + + xbar_admaif5: endpoint { + remote-endpoint =3D <&admaif5>; + }; + }; + + port@6 { + reg =3D <0x6>; + + xbar_admaif6: endpoint { + remote-endpoint =3D <&admaif6>; + }; + }; + + port@7 { + reg =3D <0x7>; + + xbar_admaif7: endpoint { + remote-endpoint =3D <&admaif7>; + }; + }; + + port@8 { + reg =3D <0x8>; + + xbar_admaif8: endpoint { + remote-endpoint =3D <&admaif8>; + }; + }; + + port@9 { + reg =3D <0x9>; + + xbar_admaif9: endpoint { + remote-endpoint =3D <&admaif9>; + }; + }; + + port@a { + reg =3D <0xa>; + + xbar_admaif10: endpoint { + remote-endpoint =3D <&admaif10>; + }; + }; + + port@b { + reg =3D <0xb>; + + xbar_admaif11: endpoint { + remote-endpoint =3D <&admaif11>; + }; + }; + + port@c { + reg =3D <0xc>; + + xbar_admaif12: endpoint { + remote-endpoint =3D <&admaif12>; + }; + }; + + port@d { + reg =3D <0xd>; + + xbar_admaif13: endpoint { + remote-endpoint =3D <&admaif13>; + }; + }; + + port@e { + reg =3D <0xe>; + + xbar_admaif14: endpoint { + remote-endpoint =3D <&admaif14>; + }; + }; + + port@f { + reg =3D <0xf>; + + xbar_admaif15: endpoint { + remote-endpoint =3D <&admaif15>; + }; + }; + + port@10 { + reg =3D <0x10>; + + xbar_admaif16: endpoint { + remote-endpoint =3D <&admaif16>; + }; + }; + + port@11 { + reg =3D <0x11>; + + xbar_admaif17: endpoint { + remote-endpoint =3D <&admaif17>; + }; + }; + + port@12 { + reg =3D <0x12>; + + xbar_admaif18: endpoint { + remote-endpoint =3D <&admaif18>; + }; + }; + + port@13 { + reg =3D <0x13>; + + xbar_admaif19: endpoint { + remote-endpoint =3D <&admaif19>; + }; + }; + + port@14 { + reg =3D <0x14>; + + xbar_admaif20: endpoint { + remote-endpoint =3D <&admaif20>; + }; + }; + + port@15 { + reg =3D <0x15>; + + xbar_admaif21: endpoint { + remote-endpoint =3D <&admaif21>; + }; + }; + + port@16 { + reg =3D <0x16>; + + xbar_admaif22: endpoint { + remote-endpoint =3D <&admaif22>; + }; + }; + + port@17 { + reg =3D <0x17>; + + xbar_admaif23: endpoint { + remote-endpoint =3D <&admaif23>; + }; + }; + + port@18 { + reg =3D <0x18>; + + xbar_admaif24: endpoint { + remote-endpoint =3D <&admaif24>; + }; + }; + + port@19 { + reg =3D <0x19>; + + xbar_admaif25: endpoint { + remote-endpoint =3D <&admaif25>; + }; + }; + + port@1a { + reg =3D <0x1a>; + + xbar_admaif26: endpoint { + remote-endpoint =3D <&admaif26>; + }; + }; + + port@1b { + reg =3D <0x1b>; + + xbar_admaif27: endpoint { + remote-endpoint =3D <&admaif27>; + }; + }; + + port@1c { + reg =3D <0x1c>; + + xbar_admaif28: endpoint { + remote-endpoint =3D <&admaif28>; + }; + }; + + port@1d { + reg =3D <0x1d>; + + xbar_admaif29: endpoint { + remote-endpoint =3D <&admaif29>; + }; + }; + + port@1e { + reg =3D <0x1e>; + + xbar_admaif30: endpoint { + remote-endpoint =3D <&admaif30>; + }; + }; + + port@1f { + reg =3D <0x1f>; + + xbar_admaif31: endpoint { + remote-endpoint =3D <&admaif31>; + }; + }; + + xbar_i2s1_port: port@20 { + reg =3D <0x20>; + + xbar_i2s1: endpoint { + remote-endpoint =3D <&i2s1_cif>; + }; + }; + + xbar_i2s2_port: port@21 { + reg =3D <0x21>; + + xbar_i2s2: endpoint { + remote-endpoint =3D <&i2s2_cif>; + }; + }; + + xbar_i2s3_port: port@22 { + reg =3D <0x22>; + + xbar_i2s3: endpoint { + remote-endpoint =3D <&i2s3_cif>; + }; + }; + + xbar_i2s4_port: port@23 { + reg =3D <0x23>; + + xbar_i2s4: endpoint { + remote-endpoint =3D <&i2s4_cif>; + }; + }; + + xbar_i2s5_port: port@24 { + reg =3D <0x24>; + + xbar_i2s5: endpoint { + remote-endpoint =3D <&i2s5_cif>; + }; + }; + + xbar_i2s6_port: port@25 { + reg =3D <0x25>; + + xbar_i2s6: endpoint { + remote-endpoint =3D <&i2s6_cif>; + }; + }; + + xbar_i2s7_port: port@26 { + reg =3D <0x26>; + + xbar_i2s7: endpoint { + remote-endpoint =3D <&i2s7_cif>; + }; + }; + + xbar_i2s8_port: port@27 { + reg =3D <0x27>; + + xbar_i2s8: endpoint { + remote-endpoint =3D <&i2s8_cif>; + }; + }; + + xbar_dmic1_port: port@28 { + reg =3D <0x28>; + + xbar_dmic1: endpoint { + remote-endpoint =3D <&dmic1_cif>; + }; + }; + + xbar_dmic2_port: port@29 { + reg =3D <0x29>; + + xbar_dmic2: endpoint { + remote-endpoint =3D <&dmic2_cif>; + }; + }; + + xbar_dspk1_port: port@2a { + reg =3D <0x2a>; + + xbar_dspk1: endpoint { + remote-endpoint =3D <&dspk1_cif>; + }; + }; + + xbar_sfc1_in_port: port@2b { + reg =3D <0x2b>; + + xbar_sfc1_in: endpoint { + remote-endpoint =3D <&sfc1_cif_in>; + }; + }; + + port@2c { + reg =3D <0x2c>; + + xbar_sfc1_out: endpoint { + remote-endpoint =3D <&sfc1_cif_out>; + }; + }; + + xbar_sfc2_in_port: port@2d { + reg =3D <0x2d>; + + xbar_sfc2_in: endpoint { + remote-endpoint =3D <&sfc2_cif_in>; + }; + }; + + port@2e { + reg =3D <0x2e>; + + xbar_sfc2_out: endpoint { + remote-endpoint =3D <&sfc2_cif_out>; + }; + }; + + xbar_sfc3_in_port: port@2f { + reg =3D <0x2f>; + + xbar_sfc3_in: endpoint { + remote-endpoint =3D <&sfc3_cif_in>; + }; + }; + + port@30 { + reg =3D <0x30>; + + xbar_sfc3_out: endpoint { + remote-endpoint =3D <&sfc3_cif_out>; + }; + }; + + xbar_sfc4_in_port: port@31 { + reg =3D <0x31>; + + xbar_sfc4_in: endpoint { + remote-endpoint =3D <&sfc4_cif_in>; + }; + }; + + port@32 { + reg =3D <0x32>; + + xbar_sfc4_out: endpoint { + remote-endpoint =3D <&sfc4_cif_out>; + }; + }; + + xbar_mvc1_in_port: port@33 { + reg =3D <0x33>; + + xbar_mvc1_in: endpoint { + remote-endpoint =3D <&mvc1_cif_in>; + }; + }; + + port@34 { + reg =3D <0x34>; + + xbar_mvc1_out: endpoint { + remote-endpoint =3D <&mvc1_cif_out>; + }; + }; + + xbar_mvc2_in_port: port@35 { + reg =3D <0x35>; + + xbar_mvc2_in: endpoint { + remote-endpoint =3D <&mvc2_cif_in>; + }; + }; + + port@36 { + reg =3D <0x36>; + + xbar_mvc2_out: endpoint { + remote-endpoint =3D <&mvc2_cif_out>; + }; + }; + + xbar_amx1_in1_port: port@37 { + reg =3D <0x37>; + + xbar_amx1_in1: endpoint { + remote-endpoint =3D <&amx1_in1>; + }; + }; + + xbar_amx1_in2_port: port@38 { + reg =3D <0x38>; + + xbar_amx1_in2: endpoint { + remote-endpoint =3D <&amx1_in2>; + }; + }; + + xbar_amx1_in3_port: port@39 { + reg =3D <0x39>; + + xbar_amx1_in3: endpoint { + remote-endpoint =3D <&amx1_in3>; + }; + }; + + xbar_amx1_in4_port: port@3a { + reg =3D <0x3a>; + + xbar_amx1_in4: endpoint { + remote-endpoint =3D <&amx1_in4>; + }; + }; + + port@3b { + reg =3D <0x3b>; + + xbar_amx1_out: endpoint { + remote-endpoint =3D <&amx1_out>; + }; + }; + + xbar_amx2_in1_port: port@3c { + reg =3D <0x3c>; + + xbar_amx2_in1: endpoint { + remote-endpoint =3D <&amx2_in1>; + }; + }; + + xbar_amx2_in2_port: port@3d { + reg =3D <0x3d>; + + xbar_amx2_in2: endpoint { + remote-endpoint =3D <&amx2_in2>; + }; + }; + + xbar_amx2_in3_port: port@3e { + reg =3D <0x3e>; + + xbar_amx2_in3: endpoint { + remote-endpoint =3D <&amx2_in3>; + }; + }; + + xbar_amx2_in4_port: port@3f { + reg =3D <0x3f>; + + xbar_amx2_in4: endpoint { + remote-endpoint =3D <&amx2_in4>; + }; + }; + + port@40 { + reg =3D <0x40>; + + xbar_amx2_out: endpoint { + remote-endpoint =3D <&amx2_out>; + }; + }; + + xbar_amx3_in1_port: port@41 { + reg =3D <0x41>; + + xbar_amx3_in1: endpoint { + remote-endpoint =3D <&amx3_in1>; + }; + }; + + xbar_amx3_in2_port: port@42 { + reg =3D <0x42>; + + xbar_amx3_in2: endpoint { + remote-endpoint =3D <&amx3_in2>; + }; + }; + + xbar_amx3_in3_port: port@43 { + reg =3D <0x43>; + + xbar_amx3_in3: endpoint { + remote-endpoint =3D <&amx3_in3>; + }; + }; + + xbar_amx3_in4_port: port@44 { + reg =3D <0x44>; + + xbar_amx3_in4: endpoint { + remote-endpoint =3D <&amx3_in4>; + }; + }; + + port@45 { + reg =3D <0x45>; + + xbar_amx3_out: endpoint { + remote-endpoint =3D <&amx3_out>; + }; + }; + + xbar_amx4_in1_port: port@46 { + reg =3D <0x46>; + + xbar_amx4_in1: endpoint { + remote-endpoint =3D <&amx4_in1>; + }; + }; + + xbar_amx4_in2_port: port@47 { + reg =3D <0x47>; + + xbar_amx4_in2: endpoint { + remote-endpoint =3D <&amx4_in2>; + }; + }; + + xbar_amx4_in3_port: port@48 { + reg =3D <0x48>; + + xbar_amx4_in3: endpoint { + remote-endpoint =3D <&amx4_in3>; + }; + }; + + xbar_amx4_in4_port: port@49 { + reg =3D <0x49>; + + xbar_amx4_in4: endpoint { + remote-endpoint =3D <&amx4_in4>; + }; + }; + + port@4a { + reg =3D <0x4a>; + + xbar_amx4_out: endpoint { + remote-endpoint =3D <&amx4_out>; + }; + }; + + xbar_amx5_in1_port: port@4b { + reg =3D <0x4b>; + + xbar_amx5_in1: endpoint { + remote-endpoint =3D <&amx5_in1>; + }; + }; + + xbar_amx5_in2_port: port@4c { + reg =3D <0x4c>; + + xbar_amx5_in2: endpoint { + remote-endpoint =3D <&amx5_in2>; + }; + }; + + xbar_amx5_in3_port: port@4d { + reg =3D <0x4d>; + + xbar_amx5_in3: endpoint { + remote-endpoint =3D <&amx5_in3>; + }; + }; + + xbar_amx5_in4_port: port@4e { + reg =3D <0x4e>; + + xbar_amx5_in4: endpoint { + remote-endpoint =3D <&amx5_in4>; + }; + }; + + port@4f { + reg =3D <0x4f>; + + xbar_amx5_out: endpoint { + remote-endpoint =3D <&amx5_out>; + }; + }; + + xbar_amx6_in1_port: port@50 { + reg =3D <0x50>; + + xbar_amx6_in1: endpoint { + remote-endpoint =3D <&amx6_in1>; + }; + }; + + xbar_amx6_in2_port: port@51 { + reg =3D <0x51>; + + xbar_amx6_in2: endpoint { + remote-endpoint =3D <&amx6_in2>; + }; + }; + + xbar_amx6_in3_port: port@52 { + reg =3D <0x52>; + + xbar_amx6_in3: endpoint { + remote-endpoint =3D <&amx6_in3>; + }; + }; + + xbar_amx6_in4_port: port@53 { + reg =3D <0x53>; + + xbar_amx6_in4: endpoint { + remote-endpoint =3D <&amx6_in4>; + }; + }; + + port@54 { + reg =3D <0x54>; + + xbar_amx6_out: endpoint { + remote-endpoint =3D <&amx6_out>; + }; + }; + + xbar_adx1_in_port: port@55 { + reg =3D <0x55>; + + xbar_adx1_in: endpoint { + remote-endpoint =3D <&adx1_in>; + }; + }; + + port@56 { + reg =3D <0x56>; + + xbar_adx1_out1: endpoint { + remote-endpoint =3D <&adx1_out1>; + }; + }; + + port@57 { + reg =3D <0x57>; + + xbar_adx1_out2: endpoint { + remote-endpoint =3D <&adx1_out2>; + }; + }; + + port@58 { + reg =3D <0x58>; + + xbar_adx1_out3: endpoint { + remote-endpoint =3D <&adx1_out3>; + }; + }; + + port@59 { + reg =3D <0x59>; + + xbar_adx1_out4: endpoint { + remote-endpoint =3D <&adx1_out4>; + }; + }; + + xbar_adx2_in_port: port@5a { + reg =3D <0x5a>; + + xbar_adx2_in: endpoint { + remote-endpoint =3D <&adx2_in>; + }; + }; + + port@5b { + reg =3D <0x5b>; + + xbar_adx2_out1: endpoint { + remote-endpoint =3D <&adx2_out1>; + }; + }; + + port@5c { + reg =3D <0x5c>; + + xbar_adx2_out2: endpoint { + remote-endpoint =3D <&adx2_out2>; + }; + }; + + port@5d { + reg =3D <0x5d>; + + xbar_adx2_out3: endpoint { + remote-endpoint =3D <&adx2_out3>; + }; + }; + + port@5e { + reg =3D <0x5e>; + + xbar_adx2_out4: endpoint { + remote-endpoint =3D <&adx2_out4>; + }; + }; + + xbar_adx3_in_port: port@5f { + reg =3D <0x5f>; + + xbar_adx3_in: endpoint { + remote-endpoint =3D <&adx3_in>; + }; + }; + + port@60 { + reg =3D <0x60>; + + xbar_adx3_out1: endpoint { + remote-endpoint =3D <&adx3_out1>; + }; + }; + + port@61 { + reg =3D <0x61>; + + xbar_adx3_out2: endpoint { + remote-endpoint =3D <&adx3_out2>; + }; + }; + + port@62 { + reg =3D <0x62>; + + xbar_adx3_out3: endpoint { + remote-endpoint =3D <&adx3_out3>; + }; + }; + + port@63 { + reg =3D <0x63>; + + xbar_adx3_out4: endpoint { + remote-endpoint =3D <&adx3_out4>; + }; + }; + + xbar_adx4_in_port: port@64 { + reg =3D <0x64>; + + xbar_adx4_in: endpoint { + remote-endpoint =3D <&adx4_in>; + }; + }; + + port@65 { + reg =3D <0x65>; + + xbar_adx4_out1: endpoint { + remote-endpoint =3D <&adx4_out1>; + }; + }; + + port@66 { + reg =3D <0x66>; + + xbar_adx4_out2: endpoint { + remote-endpoint =3D <&adx4_out2>; + }; + }; + + port@67 { + reg =3D <0x67>; + + xbar_adx4_out3: endpoint { + remote-endpoint =3D <&adx4_out3>; + }; + }; + + port@68 { + reg =3D <0x68>; + + xbar_adx4_out4: endpoint { + remote-endpoint =3D <&adx4_out4>; + }; + }; + + xbar_adx5_in_port: port@69 { + reg =3D <0x69>; + + xbar_adx5_in: endpoint { + remote-endpoint =3D <&adx5_in>; + }; + }; + + port@6a { + reg =3D <0x6a>; + + xbar_adx5_out1: endpoint { + remote-endpoint =3D <&adx5_out1>; + }; + }; + + port@6b { + reg =3D <0x6b>; + + xbar_adx5_out2: endpoint { + remote-endpoint =3D <&adx5_out2>; + }; + }; + + port@6c { + reg =3D <0x6c>; + + xbar_adx5_out3: endpoint { + remote-endpoint =3D <&adx5_out3>; + }; + }; + + port@6d { + reg =3D <0x6d>; + + xbar_adx5_out4: endpoint { + remote-endpoint =3D <&adx5_out4>; + }; + }; + + xbar_adx6_in_port: port@6e { + reg =3D <0x6e>; + + xbar_adx6_in: endpoint { + remote-endpoint =3D <&adx6_in>; + }; + }; + + port@6f { + reg =3D <0x6f>; + + xbar_adx6_out1: endpoint { + remote-endpoint =3D <&adx6_out1>; + }; + }; + + port@70 { + reg =3D <0x70>; + + xbar_adx6_out2: endpoint { + remote-endpoint =3D <&adx6_out2>; + }; + }; + + port@71 { + reg =3D <0x71>; + + xbar_adx6_out3: endpoint { + remote-endpoint =3D <&adx6_out3>; + }; + }; + + port@72 { + reg =3D <0x72>; + + xbar_adx6_out4: endpoint { + remote-endpoint =3D <&adx6_out4>; + }; + }; + + xbar_mix_in1_port: port@73 { + reg =3D <0x73>; + + xbar_mix_in1: endpoint { + remote-endpoint =3D <&mix_in1>; + }; + }; + + xbar_mix_in2_port: port@74 { + reg =3D <0x74>; + + xbar_mix_in2: endpoint { + remote-endpoint =3D <&mix_in2>; + }; + }; + + xbar_mix_in3_port: port@75 { + reg =3D <0x75>; + + xbar_mix_in3: endpoint { + remote-endpoint =3D <&mix_in3>; + }; + }; + + xbar_mix_in4_port: port@76 { + reg =3D <0x76>; + + xbar_mix_in4: endpoint { + remote-endpoint =3D <&mix_in4>; + }; + }; + + xbar_mix_in5_port: port@77 { + reg =3D <0x77>; + + xbar_mix_in5: endpoint { + remote-endpoint =3D <&mix_in5>; + }; + }; + + xbar_mix_in6_port: port@78 { + reg =3D <0x78>; + + xbar_mix_in6: endpoint { + remote-endpoint =3D <&mix_in6>; + }; + }; + + xbar_mix_in7_port: port@79 { + reg =3D <0x79>; + + xbar_mix_in7: endpoint { + remote-endpoint =3D <&mix_in7>; + }; + }; + + xbar_mix_in8_port: port@7a { + reg =3D <0x7a>; + + xbar_mix_in8: endpoint { + remote-endpoint =3D <&mix_in8>; + }; + }; + + xbar_mix_in9_port: port@7b { + reg =3D <0x7b>; + + xbar_mix_in9: endpoint { + remote-endpoint =3D <&mix_in9>; + }; + }; + + xbar_mix_in10_port: port@7c { + reg =3D <0x7c>; + + xbar_mix_in10: endpoint { + remote-endpoint =3D <&mix_in10>; + }; + }; + + port@7d { + reg =3D <0x7d>; + + xbar_mix_out1: endpoint { + remote-endpoint =3D <&mix_out1>; + }; + }; + + port@7e { + reg =3D <0x7e>; + + xbar_mix_out2: endpoint { + remote-endpoint =3D <&mix_out2>; + }; + }; + + port@7f { + reg =3D <0x7f>; + + xbar_mix_out3: endpoint { + remote-endpoint =3D <&mix_out3>; + }; + }; + + port@80 { + reg =3D <0x80>; + + xbar_mix_out4: endpoint { + remote-endpoint =3D <&mix_out4>; + }; + }; + + port@81 { + reg =3D <0x81>; + + xbar_mix_out5: endpoint { + remote-endpoint =3D <&mix_out5>; + }; + }; + + xbar_asrc_in1_port: port@82 { + reg =3D <0x82>; + + xbar_asrc_in1_ep: endpoint { + remote-endpoint =3D <&asrc_in1_ep>; + }; + }; + + port@83 { + reg =3D <0x83>; + + xbar_asrc_out1_ep: endpoint { + remote-endpoint =3D <&asrc_out1_ep>; + }; + }; + + xbar_asrc_in2_port: port@84 { + reg =3D <0x84>; + + xbar_asrc_in2_ep: endpoint { + remote-endpoint =3D <&asrc_in2_ep>; + }; + }; + + port@85 { + reg =3D <0x85>; + + xbar_asrc_out2_ep: endpoint { + remote-endpoint =3D <&asrc_out2_ep>; + }; + }; + + xbar_asrc_in3_port: port@86 { + reg =3D <0x86>; + + xbar_asrc_in3_ep: endpoint { + remote-endpoint =3D <&asrc_in3_ep>; + }; + }; + + port@87 { + reg =3D <0x87>; + + xbar_asrc_out3_ep: endpoint { + remote-endpoint =3D <&asrc_out3_ep>; + }; + }; + + xbar_asrc_in4_port: port@88 { + reg =3D <0x88>; + + xbar_asrc_in4_ep: endpoint { + remote-endpoint =3D <&asrc_in4_ep>; + }; + }; + + port@89 { + reg =3D <0x89>; + + xbar_asrc_out4_ep: endpoint { + remote-endpoint =3D <&asrc_out4_ep>; + }; + }; + + xbar_asrc_in5_port: port@8a { + reg =3D <0x8a>; + + xbar_asrc_in5_ep: endpoint { + remote-endpoint =3D <&asrc_in5_ep>; + }; + }; + + port@8b { + reg =3D <0x8b>; + + xbar_asrc_out5_ep: endpoint { + remote-endpoint =3D <&asrc_out5_ep>; + }; + }; + + xbar_asrc_in6_port: port@8c { + reg =3D <0x8c>; + + xbar_asrc_in6_ep: endpoint { + remote-endpoint =3D <&asrc_in6_ep>; + }; + }; + + port@8d { + reg =3D <0x8d>; + + xbar_asrc_out6_ep: endpoint { + remote-endpoint =3D <&asrc_out6_ep>; + }; + }; + + xbar_asrc_in7_port: port@8e { + reg =3D <0x8e>; + + xbar_asrc_in7_ep: endpoint { + remote-endpoint =3D <&asrc_in7_ep>; + }; + }; + + xbar_ope1_in_port: port@8f { + reg =3D <0x8f>; + + xbar_ope1_in_ep: endpoint { + remote-endpoint =3D <&ope1_cif_in_ep>; + }; + }; + + port@90 { + reg =3D <0x90>; + + xbar_ope1_out_ep: endpoint { + remote-endpoint =3D <&ope1_cif_out_ep>; + }; + }; + }; + }; + + agic_page0: interrupt-controller@9960000 { + compatible =3D "nvidia,tegra264-agic", + "nvidia,tegra210-agic"; + #interrupt-cells =3D <3>; + interrupt-controller; + reg =3D <0x0 0x9961000 0x0 0x1000>, + <0x0 0x9962000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&bpmp TEGRA264_CLK_ADSP>; + clock-names =3D "clk"; + status =3D "disabled"; + }; + + agic_page1: interrupt-controller@9970000 { + compatible =3D "nvidia,tegra264-agic", + "nvidia,tegra210-agic"; + #interrupt-cells =3D <3>; + interrupt-controller; + reg =3D <0x0 0x9971000 0x0 0x1000>, + <0x0 0x9972000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&bpmp TEGRA264_CLK_ADSP>; + clock-names =3D "clk"; + status =3D "disabled"; + }; + + agic_page2: interrupt-controller@9980000 { + compatible =3D "nvidia,tegra264-agic", + "nvidia,tegra210-agic"; + #interrupt-cells =3D <3>; + interrupt-controller; + reg =3D <0x0 0x9981000 0x0 0x1000>, + <0x0 0x9982000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&bpmp TEGRA264_CLK_ADSP>; + clock-names =3D "clk"; + status =3D "disabled"; + }; + + agic_page3: interrupt-controller@9990000 { + compatible =3D "nvidia,tegra264-agic", + "nvidia,tegra210-agic"; + #interrupt-cells =3D <3>; + interrupt-controller; + reg =3D <0x0 0x9991000 0x0 0x1000>, + <0x0 0x9992000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&bpmp TEGRA264_CLK_ADSP>; + clock-names =3D "clk"; + status =3D "disabled"; + }; + + agic_page4: interrupt-controller@99a0000 { + compatible =3D "nvidia,tegra264-agic", + "nvidia,tegra210-agic"; + #interrupt-cells =3D <3>; + interrupt-controller; + reg =3D <0x0 0x99a1000 0x0 0x1000>, + <0x0 0x99a2000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&bpmp TEGRA264_CLK_ADSP>; + clock-names =3D "clk"; + status =3D "disabled"; + }; + + agic_page5: interrupt-controller@99b0000 { + compatible =3D "nvidia,tegra264-agic", + "nvidia,tegra210-agic"; + #interrupt-cells =3D <3>; + interrupt-controller; + reg =3D <0x0 0x99b1000 0x0 0x1000>, + <0x0 0x99b2000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&bpmp TEGRA264_CLK_ADSP>; + clock-names =3D "clk"; + status =3D "disabled"; + }; + }; + gpcdma: dma-controller@8400000 { compatible =3D "nvidia,tegra264-gpcdma", "nvidia,tegra186-gpcdma"; reg =3D <0x0 0x08400000 0x0 0x210000>; @@ -159,6 +3317,22 @@ pmc: pmc@c800000 { #interrupt-cells =3D <2>; interrupt-controller; }; + + hda@88090b0000 { + compatible =3D "nvidia,tegra264-hda"; + reg =3D <0x88 0x90b0000 0x0 0x10000>; + interrupts =3D ; + clocks =3D <&bpmp TEGRA264_CLK_AZA_2XBIT>; + clock-names =3D "hda"; + resets =3D <&bpmp TEGRA264_RESET_HDA>, + <&bpmp TEGRA264_RESET_HDACODEC>; + reset-names =3D "hda", "hda2codec_2x"; + interconnects =3D <&mc TEGRA264_MEMORY_CLIENT_HDAR &emc>, + <&mc TEGRA264_MEMORY_CLIENT_HDAW &emc>; + interconnect-names =3D "dma-mem", "write"; + iommus =3D <&smmu3 TEGRA264_SID_HDA>; + status =3D "disabled"; + }; }; =20 /* TOP_MMIO */ @@ -400,6 +3574,22 @@ psci { method =3D "smc"; }; =20 + sound { + compatible =3D "nvidia,tegra264-audio-graph-card"; + + clocks =3D <&bpmp TEGRA264_CLK_PLLA1>, + <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + clock-names =3D "pll_a", "plla_out0"; + assigned-clocks =3D <&bpmp TEGRA264_CLK_PLLA1>, + <&bpmp TEGRA264_CLK_PLLA1_OUT1>, + <&bpmp TEGRA264_CLK_AUD_MCLK>; + assigned-clock-parents =3D <0>, + <&bpmp TEGRA264_CLK_PLLA1>, + <&bpmp TEGRA264_CLK_PLLA1_OUT1>; + + status =3D "disabled"; + }; + timer { compatible =3D "arm,armv8-timer"; interrupts =3D , --=20 2.34.1