From nobody Thu Oct 2 10:39:54 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D40132E2DC1 for ; Thu, 18 Sep 2025 06:49:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758178162; cv=none; b=D6MXLNoqRdNjABpm24toTLmGnjlK5pNkDLuEhbvu9NUmN36pjRZzxGbX0ZJXT5sy+mV+2jF9LLqh3YrXMCW2I5T2fPdpldfKnWFEneaduyU3o6CoCsszj9+D8rhXVKFWGkBQmEm9NyLlgMxo3uvmtFVBHJujVUNrAVW7JibnQJU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758178162; c=relaxed/simple; bh=9tMx3D8608utTcEpPMnkdtIuK+d8YCm/4QGWcLPlEvU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jYm+OXqpQiz5sSJi+myH/dJHxfCXf6zInoATRu2vK07vUhM9EBH/SYBwnrBgQPcEG16dvQ8z7+JpvtHuUO6Mvjeq+h+us/t5xCwwWF+UdtCzEMbaIVaDQjCdnoh48iXYyzzjPhv0l9ktRe1CwKsS3o2POBKQcR9IzeIEJMRm6E8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=lpCRIwvr; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="lpCRIwvr" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 58I6eRES027113 for ; Thu, 18 Sep 2025 06:49:19 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=52JKwdjjF6T 43Z0oK2sV6asg8JQDNCAzfJwR0DaXYts=; b=lpCRIwvrlF5jvz5ky4P+wUYnUIm 9Sw7IR8bWV/rvlV0SZv8xj19g0/on0ieFVUWtkbZkqE+xjaZp9699ZulAueWDQxd c+ISZws0qItbnCa6v5IE+jMkfym5nCBYqMfhCzceEcT3Y9T2Ks48pJsn4zf9KcTE xMWxo6pRlMPjk9NUDg1R+Rea/1iB8eDlAFFgLJLc/H0YBSEZz1ynK71CkCHHlnlQ HQ1pAA07ImBLagn+PMTfhSa3VGgvPh/9BffDtb4blf8hWUEyaKia8zkhPFHBJMtA OSDJMRiTiTpsGBiKPBRXQULGKxkzqtcSvd3jtJoZApkWXppSz7REbUS/VNw== Received: from mail-pf1-f197.google.com (mail-pf1-f197.google.com [209.85.210.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 497v1jb7bm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Thu, 18 Sep 2025 06:49:19 +0000 (GMT) Received: by mail-pf1-f197.google.com with SMTP id d2e1a72fcca58-77b73bddbdcso743023b3a.1 for ; Wed, 17 Sep 2025 23:49:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758178158; x=1758782958; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=52JKwdjjF6T43Z0oK2sV6asg8JQDNCAzfJwR0DaXYts=; b=aFVD8SQ7nktPBi1wq0wKxP+TZrmzRNhbUQMFbqyiqm8j5B5SIvgcpiLERN3GqIcyV9 b/lqEPp21BGTVYrEHMlFWHcQ5poXjBTszpJ8KlHMGnnwvbVMdaSqu9sJYaXuPFflAZjp VqBCSUGXl7m5saFzSRom5mOTFKI8ulx+r6MJndbxxhcItUnfvn3eJGuSn6viPacZjt8/ GX8AwMetSukz52mGWZkvSiozA9cedBBeBU1TF1w/0kuCkef9F7SAtYjmfEVm9Cw47r2Z HmSYNE3AiuvVTtk5MZqtdofeJ0609WP7YOE7O8JtsXT4HP8qnWT5Er4wHhDSag9BSTIa U/uA== X-Forwarded-Encrypted: i=1; AJvYcCXN2njWVeUV4H6Y7mwyJumcT+pCmRw2KqRzNaZuJ+iy0/F4cjiOf9Z9Z10YPvDxA5i+453KBcGaq66zSp4=@vger.kernel.org X-Gm-Message-State: AOJu0YxiJWlF0RBpBWIx3MJY4VcYn7po53udi7AYt6OdW7Jq6E33EJGL bk3pvvQrFHYN9GxZZ9Zplb8CM+KgfV78pzwPHxmb7Pb4PveORJ+HWKsIxVH9i1AJoI5Qls8RDDU y+boPp8fBiVsmBtLPrUI+l5uXPX3huSiWwkrgqEooedE9ogQvArNyzeXKnGXWggx7fnw= X-Gm-Gg: ASbGncvwlU8NRjncvNd971tfOGeeOiETKK2T6e4AM/zoXfMKNtxEZbNanRp95nVOhWA 0Q6yMWUCQF964wBOxU6aboJaSQhYsvtzzGonGQtVMLjsi0Fi2VERceThYeMH2IPxk2pthamdC/Y nbP93QC7DvTXt3/29uvQHa38127gmYuT/+cLxlMGsWfCseWRJq8mQiVfylmVjWSU4F1vmvrDvmc tjD9tQBmJ+r2mJVJ269H/vt/OnjRxrFYLnOOmOz4tIY6U2iOEa+TihzyHABpPbu6QRPDjHQo/yk mpKniw+0v6U1taZlVs2uWPlu6+WOMzDCIPUeG1pKasKzkgUm+DCyF70R5Px5LUfg8PyrGBvjYOp G X-Received: by 2002:a05:6a00:1992:b0:772:736e:656c with SMTP id d2e1a72fcca58-77ce08f1da6mr2829219b3a.5.1758178158226; Wed, 17 Sep 2025 23:49:18 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF2kkg02uaYOUUhEq86hfNm5J/NW9T+ioVe19n0K9h1inWY8Fam9TzKjtqjjwIZa2L3rdigNg== X-Received: by 2002:a05:6a00:1992:b0:772:736e:656c with SMTP id d2e1a72fcca58-77ce08f1da6mr2829189b3a.5.1758178157749; Wed, 17 Sep 2025 23:49:17 -0700 (PDT) Received: from hu-vdadhani-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-77cff22bdb5sm1356789b3a.94.2025.09.17.23.49.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Sep 2025 23:49:17 -0700 (PDT) From: Viken Dadhaniya To: mkl@pengutronix.de, mani@kernel.org, thomas.kopp@microchip.com, mailhol.vincent@wanadoo.fr, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linus.walleij@linaro.org, brgl@bgdev.pl, linux-can@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: mukesh.savaliya@oss.qualcomm.com, anup.kulkarni@oss.qualcomm.com, Gregor Herburger , Viken Dadhaniya Subject: [PATCH v4 1/6] can: mcp251xfd: move chip sleep mode into runtime pm Date: Thu, 18 Sep 2025 12:18:58 +0530 Message-Id: <20250918064903.241372-2-viken.dadhaniya@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250918064903.241372-1-viken.dadhaniya@oss.qualcomm.com> References: <20250918064903.241372-1-viken.dadhaniya@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: rmAB6aFKQbIWER3WrkKrngKlDbQLEG-i X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTE3MDExMCBTYWx0ZWRfX3XpXsTt3a2cw 4cC4eGk5LOPnS+pvQfa9GQSB++jCxUqdU+jxx3NdmQIP3RewuHHLdiHJiPkXBd2Gghasm24DxG4 3ap3EnCG1sg7MtYrcMQ0GVKGZJMSJBAvM0pdpn8+LHsCDsTmKfj7M5deV49be1oc7y1bhnwRDUO 0SK1487N3zW+zdsPwdq9ogSeZg29c/hm6Y8Jme/8FCB40lixVIy6UokuT891uVbX12MNeHm963d Ww8inGaa3EgrFsn+DwS/ekIc5IYBRZfJtvWbP61FMlKpOjSFW5i0NgwWKS53jMoW7w6/ZaYmAEL YyOiP8sX5SPGXzACLhKACc7XorlLTxKzhQ/U1HEGcz+RkdfupvZwScROwrqOi9mhiRjz38MyWvu B/fC0Hj8 X-Authority-Analysis: v=2.4 cv=AeqxH2XG c=1 sm=1 tr=0 ts=68cbab6f cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=yJojWOMRYYMA:10 a=8f9FM25-AAAA:8 a=EUspDBNiAAAA:8 a=6KGlMJUpO0AhJANn3KQA:9 a=2VI0MkxyNR6bbpdq8BZq:22 a=uSNRK0Bqq4PXrUp6LDpb:22 X-Proofpoint-GUID: rmAB6aFKQbIWER3WrkKrngKlDbQLEG-i X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-17_01,2025-09-18_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 phishscore=0 suspectscore=0 adultscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509170110 Content-Type: text/plain; charset="utf-8" From: Marc Kleine-Budde This is a preparation patch to add GPIO support. Up to now, the Vdd regulator and the clocks have been managed by Runtime-PM (on systems without CONFIG_PM these remain permanently switched on). During the mcp251xfd_open() callback the mcp251xfd is powered, soft-reset and configured. In mcp251xfd_stop() the chip is shut down again. To support the on-chip GPIOs, the chip must be supplied with power while GPIOs are being requested, even if the networking interface is down. To support this, move the functions mcp251xfd_chip_softreset() and mcp251xfd_chip_clock_init() from mcp251xfd_chip_start() to mcp251xfd_runtime_resume(). Instead of setting the controller to sleep mode in mcp251xfd_chip_stop(), bring it into configuration mode. This way it doesn't take part in bus activity and doesn't enter sleep mode. Signed-off-by: Marc Kleine-Budde Signed-off-by: Gregor Herburger Tested-by: Viken Dadhaniya Signed-off-by: Viken Dadhaniya --- .../net/can/spi/mcp251xfd/mcp251xfd-core.c | 91 ++++++++++++------- 1 file changed, 57 insertions(+), 34 deletions(-) diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c b/drivers/net/c= an/spi/mcp251xfd/mcp251xfd-core.c index 7450ea42c1ea..f9eabb1810cf 100644 --- a/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c +++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c @@ -767,21 +767,13 @@ static void mcp251xfd_chip_stop(struct mcp251xfd_priv= *priv, mcp251xfd_chip_interrupts_disable(priv); mcp251xfd_chip_rx_int_disable(priv); mcp251xfd_timestamp_stop(priv); - mcp251xfd_chip_sleep(priv); + mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_CONFIG); } =20 static int mcp251xfd_chip_start(struct mcp251xfd_priv *priv) { int err; =20 - err =3D mcp251xfd_chip_softreset(priv); - if (err) - goto out_chip_stop; - - err =3D mcp251xfd_chip_clock_init(priv); - if (err) - goto out_chip_stop; - err =3D mcp251xfd_chip_timestamp_init(priv); if (err) goto out_chip_stop; @@ -1625,8 +1617,11 @@ static int mcp251xfd_open(struct net_device *ndev) return err; =20 err =3D pm_runtime_resume_and_get(ndev->dev.parent); - if (err) + if (err) { + if (err =3D=3D -ETIMEDOUT || err =3D=3D -ENODEV) + pm_runtime_set_suspended(ndev->dev.parent); goto out_close_candev; + } =20 err =3D mcp251xfd_ring_alloc(priv); if (err) @@ -1907,53 +1902,53 @@ static int mcp251xfd_register(struct mcp251xfd_priv= *priv) struct net_device *ndev =3D priv->ndev; int err; =20 + mcp251xfd_register_quirks(priv); + err =3D mcp251xfd_clks_and_vdd_enable(priv); if (err) return err; =20 - pm_runtime_get_noresume(ndev->dev.parent); - err =3D pm_runtime_set_active(ndev->dev.parent); - if (err) - goto out_runtime_put_noidle; - pm_runtime_enable(ndev->dev.parent); - - mcp251xfd_register_quirks(priv); - err =3D mcp251xfd_chip_softreset(priv); if (err =3D=3D -ENODEV) - goto out_runtime_disable; + goto out_clks_and_vdd_disable; if (err) goto out_chip_sleep; =20 err =3D mcp251xfd_chip_clock_init(priv); if (err =3D=3D -ENODEV) - goto out_runtime_disable; + goto out_clks_and_vdd_disable; if (err) goto out_chip_sleep; =20 + pm_runtime_get_noresume(ndev->dev.parent); + err =3D pm_runtime_set_active(ndev->dev.parent); + if (err) + goto out_runtime_put_noidle; + pm_runtime_enable(ndev->dev.parent); + err =3D mcp251xfd_register_chip_detect(priv); if (err) - goto out_chip_sleep; + goto out_runtime_disable; =20 err =3D mcp251xfd_register_check_rx_int(priv); if (err) - goto out_chip_sleep; + goto out_runtime_disable; =20 mcp251xfd_ethtool_init(priv); =20 err =3D register_candev(ndev); if (err) - goto out_chip_sleep; + goto out_runtime_disable; =20 err =3D mcp251xfd_register_done(priv); if (err) goto out_unregister_candev; =20 - /* Put controller into sleep mode and let pm_runtime_put() - * disable the clocks and vdd. If CONFIG_PM is not enabled, - * the clocks and vdd will stay powered. + /* Put controller into Config mode and let pm_runtime_put() + * put in sleep mode, disable the clocks and vdd. If CONFIG_PM + * is not enabled, the clocks and vdd will stay powered. */ - err =3D mcp251xfd_chip_sleep(priv); + err =3D mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_CONFIG); if (err) goto out_unregister_candev; =20 @@ -1963,12 +1958,13 @@ static int mcp251xfd_register(struct mcp251xfd_priv= *priv) =20 out_unregister_candev: unregister_candev(ndev); -out_chip_sleep: - mcp251xfd_chip_sleep(priv); out_runtime_disable: pm_runtime_disable(ndev->dev.parent); out_runtime_put_noidle: pm_runtime_put_noidle(ndev->dev.parent); +out_chip_sleep: + mcp251xfd_chip_sleep(priv); +out_clks_and_vdd_disable: mcp251xfd_clks_and_vdd_disable(priv); =20 return err; @@ -1980,10 +1976,12 @@ static inline void mcp251xfd_unregister(struct mcp2= 51xfd_priv *priv) =20 unregister_candev(ndev); =20 - if (pm_runtime_enabled(ndev->dev.parent)) + if (pm_runtime_enabled(ndev->dev.parent)) { pm_runtime_disable(ndev->dev.parent); - else + } else { + mcp251xfd_chip_sleep(priv); mcp251xfd_clks_and_vdd_disable(priv); + } } =20 static const struct of_device_id mcp251xfd_of_match[] =3D { @@ -2206,16 +2204,41 @@ static void mcp251xfd_remove(struct spi_device *spi) =20 static int __maybe_unused mcp251xfd_runtime_suspend(struct device *device) { - const struct mcp251xfd_priv *priv =3D dev_get_drvdata(device); + struct mcp251xfd_priv *priv =3D dev_get_drvdata(device); =20 + mcp251xfd_chip_sleep(priv); return mcp251xfd_clks_and_vdd_disable(priv); } =20 static int __maybe_unused mcp251xfd_runtime_resume(struct device *device) { - const struct mcp251xfd_priv *priv =3D dev_get_drvdata(device); + struct mcp251xfd_priv *priv =3D dev_get_drvdata(device); + int err; + + err =3D mcp251xfd_clks_and_vdd_enable(priv); + if (err) + return err; =20 - return mcp251xfd_clks_and_vdd_enable(priv); + err =3D mcp251xfd_chip_softreset(priv); + if (err =3D=3D -ENODEV) + goto out_clks_and_vdd_disable; + if (err) + goto out_chip_sleep; + + err =3D mcp251xfd_chip_clock_init(priv); + if (err =3D=3D -ENODEV) + goto out_clks_and_vdd_disable; + if (err) + goto out_chip_sleep; + + return 0; + +out_chip_sleep: + mcp251xfd_chip_sleep(priv); +out_clks_and_vdd_disable: + mcp251xfd_clks_and_vdd_disable(priv); + + return err; } =20 static const struct dev_pm_ops mcp251xfd_pm_ops =3D { --=20 2.34.1 From nobody Thu Oct 2 10:39:54 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D5C22E3AF2 for ; Thu, 18 Sep 2025 06:49:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758178168; cv=none; b=OfwhkwSr9pdMrJIfaroUYHk/7zZohk+faR7ZKlomnsxW5Psz4KszHeU4O0Rbq9k+YhsFL3ZOtD31N1U3v4BrKpIVvjQwiiUEco9KAqJ9ad5KsnpX/Pv7AOpIkV52y57lMlQvrVUx5dLNGdwvf6ZIqnSOUFJ5+f+D8KsUw63Q10A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758178168; c=relaxed/simple; bh=+IOLF0XPvUULiaKZhdl3sSn55zuFmc8DaivaubnewwY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=qgVZeDucU+uaScNGnPuHuRfB25bGCGCyAGMaPaczYe4uH+gCqLCuZ9qVYzMeG12WtHGwgVsutr5i1KTsIA+6RqYdYvsNXyUPFE+DGeVHp0elv6qhj0sRsnMdsWNMbdwcXTQzd6a9QbKoiZsGUxb6E5pEmW9PESdkqSyl49hQxLI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=A3XYrLCV; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="A3XYrLCV" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 58I0SaZ9003340 for ; Thu, 18 Sep 2025 06:49:25 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=QmS6oCHS+MH N39AhLGTMSeGEuEf2T3uv/XWwxaYqPAw=; b=A3XYrLCVG+VL82KO7BbccmXUYH5 b43GANxPmYdJhedIxu18nrKLC5d60hAJwdhFZjYNGxqiH7YM6CH/h5eYu9CEsrqc IC3Xs7DAMydACTSVQYnJ2YfRFe7heeGuOGIb2tEH8yhNcwGBgUPUurMx0MTzqojt Cv7Giieya2wzlWQfLsCLWddaKZ6A8538jxQAXxIifl/XK9q6iHaOj6LCcm2jJvD1 jmZ2RpyslYLpRuJu2GRm9ufXb0UjW0Dr+DZCALFSBzuQHUA0hrBPw/PIRaOM8pK+ EGT/P/S45SlIUSemKLuKwh/s7/7XGFWgtaOwE/HmzifRD4FvYVqIu3+HhXA== Received: from mail-pf1-f200.google.com (mail-pf1-f200.google.com [209.85.210.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 497wqgtth5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Thu, 18 Sep 2025 06:49:25 +0000 (GMT) Received: by mail-pf1-f200.google.com with SMTP id d2e1a72fcca58-77621c54731so854691b3a.3 for ; Wed, 17 Sep 2025 23:49:25 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758178164; x=1758782964; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QmS6oCHS+MHN39AhLGTMSeGEuEf2T3uv/XWwxaYqPAw=; b=n+LJnA+NHANSDz6S/WxIWr7w0zgCEhHcAAHMG9x/EhHIHTKrEEmnDvT5vBarJQ439D ebKsAGXcY7AiyAzTAXQmMxcVbtuxbyzqli0vI3cw1LJogYShYNHovxOeJzKAYe5Byonz 95DlNWTsO0YxKqRP9sllyJqtiGyG921VdLL1NQmGcq1U4LyxL85WeynF7/M38kxM0Fir ejZbBrfRmsRu3QCQTsr2Fi3A8uhMARHDoDgzveWCznH1Y80SwJ2OmQcddh1zIIzjvJCw ViepbhLizmWM0vSNDnqV2YVvYK4PUXIahsGUI/kipGWftAYkQjCpvbk3Upikwo7OjBQO qnGQ== X-Forwarded-Encrypted: i=1; AJvYcCVs2Ayn4Qfh8KdEkHtwlkobTANx2aqFj+UTg4qFbahXFCxrTnCS4fEXML4DZbc/+EEAdUu2OET6jGXQtww=@vger.kernel.org X-Gm-Message-State: AOJu0YyP5XAkJGbsfCbPfMm2LjIryY7hJcEIy8trLNLZdYPVmA3Cp4Y6 1fW31oEcWZXfYOyl49t+ozBTbyCco4+9DVilSkLGGyQwCrhRWHOJzBiopBs13LL0LErmfrp6/I+ SbRW24NE8ejhWP54vXKLNOymIhVZ7Q+npMB++jJCgFPYBS4CguCx4EZ7ZFP9mB0mAllY= X-Gm-Gg: ASbGncvtUVy4gkcXVBvNyisgQ7yImCHLK5BsNSAG51RRQR++KnfZPHJE+yQm8Ih8t6E FDC/5nDIZ3OoOwfyorL6Y6wl5yvuICaEbO+XwihhhtWDERmp1z7IfmxedFaXdhjrfiSIxvvZ+KA kXOiwml0m22oyqyng9CG2qcetcWJdOI5w25k9iNYfMf+LS5bbSrMqLSHCuLADZJPs0n9GBXVsQm UDmbxgpNmlMH3cnesURqmOvoorlsyk5Qlm0USShI55e0tUxtTUJBNUsBRYFmY6yjd33r4SnlV8/ XAWg+11ymCR28CM2f+RhDnO31X/SVL5qqhSECx6JqO3Iu26H8x70YjpQIATnmvXL7Xuz9diIbVY a X-Received: by 2002:a05:6a00:18a2:b0:776:2e3:a95b with SMTP id d2e1a72fcca58-77bf72cb98cmr5744825b3a.1.1758178164096; Wed, 17 Sep 2025 23:49:24 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEGukSBl0fOY+Q+OdY68Z3vITk6rVt7kdWoKiAb3EkNyvnFx81Fn4rVDEc00foqitvN18kvpw== X-Received: by 2002:a05:6a00:18a2:b0:776:2e3:a95b with SMTP id d2e1a72fcca58-77bf72cb98cmr5744803b3a.1.1758178163666; Wed, 17 Sep 2025 23:49:23 -0700 (PDT) Received: from hu-vdadhani-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-77cff22bdb5sm1356789b3a.94.2025.09.17.23.49.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Sep 2025 23:49:23 -0700 (PDT) From: Viken Dadhaniya To: mkl@pengutronix.de, mani@kernel.org, thomas.kopp@microchip.com, mailhol.vincent@wanadoo.fr, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linus.walleij@linaro.org, brgl@bgdev.pl, linux-can@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: mukesh.savaliya@oss.qualcomm.com, anup.kulkarni@oss.qualcomm.com, Gregor Herburger , Viken Dadhaniya Subject: [PATCH v4 2/6] can: mcp251xfd: utilize gather_write function for all non-CRC writes Date: Thu, 18 Sep 2025 12:18:59 +0530 Message-Id: <20250918064903.241372-3-viken.dadhaniya@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250918064903.241372-1-viken.dadhaniya@oss.qualcomm.com> References: <20250918064903.241372-1-viken.dadhaniya@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: k1qoDjefBgz2oVKkgDHHHxqIOsQO6HWS X-Authority-Analysis: v=2.4 cv=HITDFptv c=1 sm=1 tr=0 ts=68cbab75 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=yJojWOMRYYMA:10 a=8f9FM25-AAAA:8 a=EUspDBNiAAAA:8 a=lCqp9tVl3zhOgjhhuWQA:9 a=zc0IvFSfCIW2DFIPzwfm:22 a=uSNRK0Bqq4PXrUp6LDpb:22 X-Proofpoint-GUID: k1qoDjefBgz2oVKkgDHHHxqIOsQO6HWS X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTE3MDEyOCBTYWx0ZWRfX3e9zLVkPWpKu k444n21/P6A1TOlQG2awSTT8JkE8LbsQeOxvt63cV4fK1CbpLk5FHeMePZG1ys9/LmVlWNYMIH1 k1K7dDk977UgcSAjBka9gjEjcMHlTwVvx4oyYqmLho+hEbcuzCb5yJCfOPS330yi0kIiV+bLam8 1sBloWgBkP8h/M5epyHbaza66fI0Ekh21D7MABwFQkbXl874Ie55uaXI/Y8QPm6sVn7KrAtiWxb yKZPhXMagebnlTBmn/f3yka6QL4QD6lHfCtDKwJ5LmNd05y16kXMtO1GBYliFUWducQkivCIHKa wvlo3u44nrU4f/R3jqHlrQA7ffngyQHSjG4os4M7bhdpyp2CRJigg6tgRx1msPxhetZkhkPjwkr 5Yjx72s2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-17_01,2025-09-18_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 phishscore=0 adultscore=0 bulkscore=0 malwarescore=0 impostorscore=0 clxscore=1015 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509170128 Content-Type: text/plain; charset="utf-8" From: Gregor Herburger This is a preparation patch to add errata workaround for non crc writes. Currently for non-crc writes to the chip can go through the .gather_write, .write or the reg_update_bits callback. To allow the addition of the errata fix at a single location use mcp251xfd_regmap_nocrc_gather_write for all non-CRC write instructions, similar to the crc regmap. Signed-off-by: Gregor Herburger Tested-by: Viken Dadhaniya Signed-off-by: Viken Dadhaniya --- .../net/can/spi/mcp251xfd/mcp251xfd-regmap.c | 25 ++++++++++--------- 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c b/drivers/net= /can/spi/mcp251xfd/mcp251xfd-regmap.c index 8c5be8d1c519..e61cbd209955 100644 --- a/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c +++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c @@ -12,14 +12,6 @@ =20 static const struct regmap_config mcp251xfd_regmap_crc; =20 -static int -mcp251xfd_regmap_nocrc_write(void *context, const void *data, size_t count) -{ - struct spi_device *spi =3D context; - - return spi_write(spi, data, count); -} - static int mcp251xfd_regmap_nocrc_gather_write(void *context, const void *reg, size_t reg_len, @@ -47,6 +39,15 @@ mcp251xfd_regmap_nocrc_gather_write(void *context, return spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer)); } =20 +static int +mcp251xfd_regmap_nocrc_write(void *context, const void *data, size_t count) +{ + const size_t data_offset =3D sizeof(__be16); + + return mcp251xfd_regmap_nocrc_gather_write(context, data, data_offset, + data + data_offset, count - data_offset); +} + static inline bool mcp251xfd_update_bits_read_reg(const struct mcp251xfd_priv *priv, unsigned int reg) @@ -64,6 +65,7 @@ mcp251xfd_update_bits_read_reg(const struct mcp251xfd_pri= v *priv, case MCP251XFD_REG_CON: case MCP251XFD_REG_OSC: case MCP251XFD_REG_ECCCON: + case MCP251XFD_REG_IOCON: return true; default: mcp251xfd_for_each_rx_ring(priv, ring, n) { @@ -139,10 +141,9 @@ mcp251xfd_regmap_nocrc_update_bits(void *context, unsi= gned int reg, tmp_le32 =3D orig_le32 & ~mask_le32; tmp_le32 |=3D val_le32 & mask_le32; =20 - mcp251xfd_spi_cmd_write_nocrc(&buf_tx->cmd, reg + first_byte); - memcpy(buf_tx->data, &tmp_le32, len); - - return spi_write(spi, buf_tx, sizeof(buf_tx->cmd) + len); + reg +=3D first_byte; + mcp251xfd_spi_cmd_write_nocrc(&buf_tx->cmd, reg); + return mcp251xfd_regmap_nocrc_gather_write(context, &buf_tx->cmd, 2, &tmp= _le32, len); } =20 static int --=20 2.34.1 From nobody Thu Oct 2 10:39:54 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F6142E7621 for ; Thu, 18 Sep 2025 06:49:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758178173; cv=none; b=raCT+xJHpF8MYVnYB/jZt9lFlN5c+eBc6OgjHwuOS2iVdgCkObbYyCWa919BECb/gV6RH2eLJ3Fe0FFS3tpWaX+S1gCGFr0L0P0/EZUgNMsrPwWWeNWXwvxlLThNG5+hyjhP4qRsyKsXUOUQarnyLUyz65EYacm97UaO0zy9cdI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758178173; c=relaxed/simple; bh=/4kbUwnniL554GVUNwVLXBqnCaR/My4fabOkFQKK6oo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=mSMZuCbvLoO9WPPQzG3FSJeaIvZHoSTO99rGx+5LfmLd1xTBTCdsKlNJFkcgZveLvEMd+6QAam36ezL0PidZi5tR0AayXv3vYsfftWdJOIABlO10PrGJJ1SXYMrhkqEfcTln3OMYjdaJKESExHgWMp5Xsj2ZnhtD57RfkW8K8R4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=LRUsp5o2; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="LRUsp5o2" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 58I2wc3v019524 for ; Thu, 18 Sep 2025 06:49:31 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=NnvOmJJvaiJ dkdV0XAgXRx/iMwwsotajiWEilazX6Rg=; b=LRUsp5o21t5z1kKnrb/8bDIx+/B FQCTlxML4MLx7FQRYb3IUzPQ0K05ryQkcnHvCSA1EM2JDbp+DkM5FDlS/0WFycT5 jJEkD3urgo43Ayb/J+fAswFGcSkCon/ee1nTCrRLqv+QOIhnEppq8PmWGTAi8Kkb HFXZXiu5vKHNLZqWTh1M9wovWMeSzCAa2fBk6Z5JeIwVRHWLc1q0AgMjTcz8YC10 PGi6e5hvZcusXwpzykGo5r5NogSXQ0LgBu6AV4nVk8ETtCxXkV7fK9mqKy5OobNg r/EL2CtazimZ0UGKJlyRs/E8Y7XGrtpF1DvYhlfxhYR12Zs4yV+tZVTL59Q== Received: from mail-pf1-f198.google.com (mail-pf1-f198.google.com [209.85.210.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 497fy1wbnf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Thu, 18 Sep 2025 06:49:30 +0000 (GMT) Received: by mail-pf1-f198.google.com with SMTP id d2e1a72fcca58-7725b77b795so667425b3a.2 for ; Wed, 17 Sep 2025 23:49:30 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758178170; x=1758782970; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NnvOmJJvaiJdkdV0XAgXRx/iMwwsotajiWEilazX6Rg=; b=hVVXZBgypTpphKlGgMu+uAUGPJo9VZ8QdHas5KHppkcoHX4G3HYcE0TrOq2T9J2xlh 1FksPKhNlg26gSOHkr+BvFmCrNFZ+ZljukujDMDG+n56VbPvs6xUQ1wHevp5GRNiWxIx zUfMXSMowhUy+BNZrRiAKi/05oCSfHdLr4Zyh/xiZeDR/Hxhtl/AuxF/g6u6Npz7RkTv 3aEnRkhr20fiOPQoY8Bz+R11iwo0stfK9I/uTkPdu5gkmK4/llCpay7Xn8SCLkz5IaDd IvuYy9olsjc+A5WAz2B2SBjatyN7HNnfYX5oY/2xoGMsI5uwuVQnHU3Yhid2cCsPPUjl IBGA== X-Forwarded-Encrypted: i=1; AJvYcCUoUjanR6h5AZwTtkM3jTGNhJmtsGR6ltRDbEjOjidM+nsrb8ZXhZD6JIbpKmhZHk5wf9cPx5IdfdhqwhM=@vger.kernel.org X-Gm-Message-State: AOJu0Yy6ol6RAtWAWjnO0y7xQ2Xtl3ryLl0+VpSj6dL2dWJUFyArcHtI PsEGiaJiUGuvPIg/jaatbrvYIU8q8YfPJtfjpxhExO4MCQrHQE8YWkx4wAxNXqaY9CrVTvGeXht noNmC7WbZJb5puT8P/O4qoeCdCHy/Bx7Lt9tdVAjSYEHBi/IV4phWxGFgFnagklmMBhA= X-Gm-Gg: ASbGnctoN6oKKLDudN8JyZQkal3glVVoNYOS0o7BxWxpWtIubDUOQOI7zFTQkl8jryk 3CC3KH8NkB51nWkJmcASfpXjTKt2OAPfGFnOHgHkzXGxXe/rMDZBPk0wlVDoqMXc3rC9zftCjuK IHXZIRm5CCJfAnljUvMzG0RTN1fX1lruou3qa7PrvXvdPzdFoiwgpAfLJ9oWHnmPPO16wM8GO5M f1UkUc0OXW8sqy8UCyiQBj4z3Pd9Ber088ITyku50dpqNR2U9QhE4huIVOEEgHXn6j7NvtOww17 CUBmF48dHyvxLqaVPt9u1KUKBYzAQBkBgkSGKnWVGYvv1eb7kym5MHm0aZxu7W4dMAzOJuCgRIR B X-Received: by 2002:a05:6a00:a24:b0:76b:c9b9:a11b with SMTP id d2e1a72fcca58-77bf6fcf42amr4802542b3a.3.1758178169616; Wed, 17 Sep 2025 23:49:29 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG7sRaE02ggQe01SKwGhQlmhie7T/BAQTw4FIQVNZcr6uyfDFZZxhM/OJpvcp1IJ6Q2Ip3U1g== X-Received: by 2002:a05:6a00:a24:b0:76b:c9b9:a11b with SMTP id d2e1a72fcca58-77bf6fcf42amr4802516b3a.3.1758178169129; Wed, 17 Sep 2025 23:49:29 -0700 (PDT) Received: from hu-vdadhani-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-77cff22bdb5sm1356789b3a.94.2025.09.17.23.49.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Sep 2025 23:49:28 -0700 (PDT) From: Viken Dadhaniya To: mkl@pengutronix.de, mani@kernel.org, thomas.kopp@microchip.com, mailhol.vincent@wanadoo.fr, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linus.walleij@linaro.org, brgl@bgdev.pl, linux-can@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: mukesh.savaliya@oss.qualcomm.com, anup.kulkarni@oss.qualcomm.com, Gregor Herburger , Viken Dadhaniya Subject: [PATCH v4 3/6] can: mcp251xfd: add workaround for errata 5 Date: Thu, 18 Sep 2025 12:19:00 +0530 Message-Id: <20250918064903.241372-4-viken.dadhaniya@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250918064903.241372-1-viken.dadhaniya@oss.qualcomm.com> References: <20250918064903.241372-1-viken.dadhaniya@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: Sl5yKxwT1pTzCgJcFxTPGuQABan-nuGk X-Proofpoint-ORIG-GUID: Sl5yKxwT1pTzCgJcFxTPGuQABan-nuGk X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTE2MDIwMiBTYWx0ZWRfXxN8LwSG9omUD 0odDCsMyoSfI07H9tfB2MT/aEJHNhLYO+nrNKrTItseNEPCFI7i6+V1WurJNhFes2wAS0nWzlcF Cj1QHlYsuESJHSSJBXoRDTQZkry6T11suHOxnhq1zj8d/Tk3Gcj0Wp54wxZPafoBENdxsUGd8Rd o/47DBkdGhfygOfc/TaLQoD5qvK+3kaWyTHrsVuGMVlkRzcNZT3FS0+rJ/QFEVY6vlW3vJRJktJ 1ucfjPAoJDugWrDXuqZMf385+FdV0PCT0VVG+FXZfFxd7usMCHKRi8+lzHlkjyBVC9YDxkaaJgO FVZhnc7D8DTr8SlQCXGDMFhZNndrf+lU6lhYbLCHAgFK1ISZWE3Bg7g3tIcCSfBEcCIAt7UQGXP 4nhDdrvk X-Authority-Analysis: v=2.4 cv=cf7SrmDM c=1 sm=1 tr=0 ts=68cbab7b cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=yJojWOMRYYMA:10 a=8f9FM25-AAAA:8 a=EUspDBNiAAAA:8 a=-2jKClcn1S1UO4fOL_0A:9 a=IoOABgeZipijB_acs4fv:22 a=uSNRK0Bqq4PXrUp6LDpb:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-17_01,2025-09-18_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 adultscore=0 bulkscore=0 priorityscore=1501 spamscore=0 phishscore=0 impostorscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509160202 Content-Type: text/plain; charset="utf-8" From: Gregor Herburger According to Errata DS80000789E 5 writing IOCON register using one SPI write command clears LAT0/LAT1. Errata Fix/Work Around suggests to write registers with single byte write instructions. However, it seems that every write to the second byte causes the overwrite of LAT0/LAT1. Never write byte 2 of IOCON register to avoid clearing of LAT0/LAT1. Signed-off-by: Gregor Herburger Tested-by: Viken Dadhaniya Signed-off-by: Viken Dadhaniya --- .../net/can/spi/mcp251xfd/mcp251xfd-regmap.c | 89 +++++++++++++++++-- 1 file changed, 83 insertions(+), 6 deletions(-) diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c b/drivers/net= /can/spi/mcp251xfd/mcp251xfd-regmap.c index e61cbd209955..bc24a837bcd0 100644 --- a/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c +++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd-regmap.c @@ -13,9 +13,9 @@ static const struct regmap_config mcp251xfd_regmap_crc; =20 static int -mcp251xfd_regmap_nocrc_gather_write(void *context, - const void *reg, size_t reg_len, - const void *val, size_t val_len) +_mcp251xfd_regmap_nocrc_gather_write(void *context, + const void *reg, size_t reg_len, + const void *val, size_t val_len) { struct spi_device *spi =3D context; struct mcp251xfd_priv *priv =3D spi_get_drvdata(spi); @@ -39,6 +39,45 @@ mcp251xfd_regmap_nocrc_gather_write(void *context, return spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer)); } =20 +static int +mcp251xfd_regmap_nocrc_gather_write(void *context, + const void *reg_p, size_t reg_len, + const void *val, size_t val_len) +{ + const u16 byte_exclude =3D MCP251XFD_REG_IOCON + + mcp251xfd_first_byte_set(MCP251XFD_REG_IOCON_GPIO_MASK); + u16 reg =3D be16_to_cpu(*(u16 *)reg_p) & MCP251XFD_SPI_ADDRESS_MASK; + int ret; + + /* Never write to bits 16..23 of IOCON register to avoid clearing of LAT0= /LAT1 + * + * According to MCP2518FD Errata DS80000789E 5 writing IOCON register usi= ng one + * SPI write command clears LAT0/LAT1. + * + * Errata Fix/Work Around suggests to write registers with single byte + * write instructions. However, it seems that the byte at 0xe06(IOCON[23:= 16]) + * is for read-only access and writing to it causes the clearing of LAT0/= LAT1. + */ + if (reg <=3D byte_exclude && reg + val_len > byte_exclude) { + size_t len =3D byte_exclude - reg; + + /* Write up to 0xe05 */ + ret =3D _mcp251xfd_regmap_nocrc_gather_write(context, reg_p, reg_len, va= l, len); + if (ret) + return ret; + + /* Write from 0xe07 on */ + reg +=3D len + 1; + reg =3D cpu_to_be16(MCP251XFD_SPI_INSTRUCTION_WRITE | reg); + return _mcp251xfd_regmap_nocrc_gather_write(context, ®, reg_len, + val + len + 1, + val_len - len - 1); + } + + return _mcp251xfd_regmap_nocrc_gather_write(context, reg_p, reg_len, + val, val_len); +} + static int mcp251xfd_regmap_nocrc_write(void *context, const void *data, size_t count) { @@ -197,9 +236,9 @@ mcp251xfd_regmap_nocrc_read(void *context, } =20 static int -mcp251xfd_regmap_crc_gather_write(void *context, - const void *reg_p, size_t reg_len, - const void *val, size_t val_len) +_mcp251xfd_regmap_crc_gather_write(void *context, + const void *reg_p, size_t reg_len, + const void *val, size_t val_len) { struct spi_device *spi =3D context; struct mcp251xfd_priv *priv =3D spi_get_drvdata(spi); @@ -230,6 +269,44 @@ mcp251xfd_regmap_crc_gather_write(void *context, return spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer)); } =20 +static int +mcp251xfd_regmap_crc_gather_write(void *context, + const void *reg_p, size_t reg_len, + const void *val, size_t val_len) +{ + const u16 byte_exclude =3D MCP251XFD_REG_IOCON + + mcp251xfd_first_byte_set(MCP251XFD_REG_IOCON_GPIO_MASK); + u16 reg =3D *(u16 *)reg_p; + int ret; + + /* Never write to bits 16..23 of IOCON register to avoid clearing of LAT0= /LAT1 + * + * According to MCP2518FD Errata DS80000789E 5 writing IOCON register usi= ng one + * SPI write command clears LAT0/LAT1. + * + * Errata Fix/Work Around suggests to write registers with single byte + * write instructions. However, it seems that the byte at 0xe06(IOCON[23:= 16]) + * is for read-only access and writing to it causes the clearing of LAT0/= LAT1. + */ + if (reg <=3D byte_exclude && reg + val_len > byte_exclude) { + size_t len =3D byte_exclude - reg; + + /* Write up to 0xe05 */ + ret =3D _mcp251xfd_regmap_crc_gather_write(context, ®, reg_len, val, = len); + if (ret) + return ret; + + /* Write from 0xe07 on */ + reg +=3D len + 1; + return _mcp251xfd_regmap_crc_gather_write(context, ®, reg_len, + val + len + 1, + val_len - len - 1); + } + + return _mcp251xfd_regmap_crc_gather_write(context, reg_p, reg_len, + val, val_len); +} + static int mcp251xfd_regmap_crc_write(void *context, const void *data, size_t count) --=20 2.34.1 From nobody Thu Oct 2 10:39:54 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AED842E7651 for ; Thu, 18 Sep 2025 06:49:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758178178; cv=none; b=Y/XQkX+Uqj8mvoXRJDdAKGlDhxyiDTc/8WWk2kqAd3W51AZ4WjEvRNAia47DP2OM0/sV2RrnI4cTl9JSg3SXjKS3F4MBp0oFKzQrq4EWlUPpfAgN9SCvwIhuK7d5z65UekDn/F4ZqKeymJrkWUjM0fyJMBq9qPk65uAN1fT/6ik= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758178178; c=relaxed/simple; bh=fk0TNQn7BAcvjE7TYECp7NGF/xF5QIeAzGhAHgip9EU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fQ9QWhgKV40kxHljdxmnjCImo7f58zNABxFPlUc+iyiJ+yq7sqINyCAFu/FoZGlqpcYV6qPtOXzyGD5uFR7dKnwgjZuD8yuRR+vm3lMYbhuJOwuyOS/04Lj9l9TO4U0WsTXnm403Q7HKvdKgFgkbXUOYURS1vMgImEVLCdkxBUc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=d9BfRA69; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="d9BfRA69" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 58I3GNNJ032456 for ; Thu, 18 Sep 2025 06:49:36 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=fAG+r6LmnpS +c29A06CpnJf3DtWoAPxQEN6FpwdQPUk=; b=d9BfRA692SB+8TNxXbttaf9BHiN ZUUVcpCjH8U+uRDEsNOuw1hcbZYKGBuI1OX5rTeo+/nRAq8+A+h1z41HQaKdZMgX W4XaLwXuKNGKL4wd+adRS9jzZqImRNWVRnzlHRQ5Qt1fJ+bO/3XdbKQOzgfNmSsc DPxVl5yR/QiJ0m7blSCRD8bjS6p+XHpQGhPItGIB68TAeKZ7nk6+o4rUqeKKGtM0 AUlfNywzxCxxs/uCNcZ6pWYDU3b5eXZ8BaIsOA0xuNezpisovgz1DAO+yuN5yLrH cGlZgVMMi/bj6P8d/FMEDfd1F2mJmC3BMNNf8WSF2HXvo//D9deYeVro2Tw== Received: from mail-pf1-f199.google.com (mail-pf1-f199.google.com [209.85.210.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 497fxyn8f7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Thu, 18 Sep 2025 06:49:35 +0000 (GMT) Received: by mail-pf1-f199.google.com with SMTP id d2e1a72fcca58-7779219ccc2so823347b3a.1 for ; Wed, 17 Sep 2025 23:49:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758178175; x=1758782975; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fAG+r6LmnpS+c29A06CpnJf3DtWoAPxQEN6FpwdQPUk=; b=Ly05qkibfyh/R68a2BM6+LOwRoqJdI/wQyYMl9hbwRY7OEl8l1AGOmaG28e3NsUvyN 57QtBg+WQrbHzohYW3UUKuAhFW0gd/o3gEpk3MlZ1eGBDj6U0HMqEiWy80RVP0jetloR TyMVulfA6zv5r7Y55BvRB4KSIkpirbLh7l0SfPHqxwJhlU43GxbA1EkwX3Ph+NH5OGKN BZGL5Jj5SUJvq+o2RupshevGDqYm/QZgL6Z7C5eZwwlZykA9Bqi9aUlrGebqUNAOC73E 3iG6rY80F3zcMJxVz/AS3xJEpo4kMxMrAW+uzXUT14ZXCKeeoF6nXkUEWia/iylv79dA V48Q== X-Forwarded-Encrypted: i=1; AJvYcCWebpFrkgEuIN8NUz3YeGkh4PDX38OPJpXwk46TmguxfGiA6Kmh3GSWs+LTOG12gVxtScO13VIgKgYcGhc=@vger.kernel.org X-Gm-Message-State: AOJu0YwgUoqrmUswmQvAlG3R/ck8wB8xJchfnmQKSP8XjUvWj1KcSgNJ ffmvZFNFQBBBO7N1TaHUjUgPWMhY3vNn8f9eGmFA31X8J8NwfeOYvkxPjLzys7fQYY8Jwk3y7FL VIAJiS7q1zYhrJQEZX5weWZQcGj16GshKbcPdP5LUNLA2ETULkX1rbrvYq7S6rbNrjqI= X-Gm-Gg: ASbGncuVt5N6CqF9DrISfhiXmToWxenTBA3ocSXTbii7yQfBdRLIebuuKkUGQ4EX4i8 XFvZUpgW9Lqdag9Jg/VMvlMjau4UHM6fhNo5sAym5c8d8aqW+SoniXThd0KLq7jdDfYgU1glPyz i7/T3SvdhiabZlFIapCp+Y+B587mfaoPyzeJX77RDFyMTZ5lpgsqrQa9c+dEExFl6NbFYLid3mb 5Umz0yiv0aRncfu+ZUISKGMuX1vob+iSrg3lALwW7UHLamT3TOCYuanKiZ4BciesGfq/k8H9DBg YWpC4qmHL9+ZC7b15jMhJ4Aro5ppz73By8CexCuyGOuqXsIeMQNgOkMqPiOta1tNZ6Jmj3klyeZ m X-Received: by 2002:a05:6a21:339f:b0:262:c083:bb3a with SMTP id adf61e73a8af0-27aacc777ddmr7314908637.60.1758178175025; Wed, 17 Sep 2025 23:49:35 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFwmQHzJp7VE8ev7s4YG3cL5g9fuuOf9VLXesHRyVN7cCsWP8urp7NG7z6HzTDcRNqhM1WC+A== X-Received: by 2002:a05:6a21:339f:b0:262:c083:bb3a with SMTP id adf61e73a8af0-27aacc777ddmr7314870637.60.1758178174617; Wed, 17 Sep 2025 23:49:34 -0700 (PDT) Received: from hu-vdadhani-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-77cff22bdb5sm1356789b3a.94.2025.09.17.23.49.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Sep 2025 23:49:34 -0700 (PDT) From: Viken Dadhaniya To: mkl@pengutronix.de, mani@kernel.org, thomas.kopp@microchip.com, mailhol.vincent@wanadoo.fr, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linus.walleij@linaro.org, brgl@bgdev.pl, linux-can@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: mukesh.savaliya@oss.qualcomm.com, anup.kulkarni@oss.qualcomm.com, Gregor Herburger , Viken Dadhaniya Subject: [PATCH v4 4/6] can: mcp251xfd: only configure PIN1 when rx_int is set Date: Thu, 18 Sep 2025 12:19:01 +0530 Message-Id: <20250918064903.241372-5-viken.dadhaniya@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250918064903.241372-1-viken.dadhaniya@oss.qualcomm.com> References: <20250918064903.241372-1-viken.dadhaniya@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=e50GSbp/ c=1 sm=1 tr=0 ts=68cbab80 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=yJojWOMRYYMA:10 a=8f9FM25-AAAA:8 a=EUspDBNiAAAA:8 a=Zr3td6iJmGh5AMeZqZgA:9 a=OpyuDcXvxspvyRM73sMx:22 a=uSNRK0Bqq4PXrUp6LDpb:22 X-Proofpoint-GUID: fw1MrJjM1mAAUVIC_gHBLEN1jwOmC67B X-Proofpoint-ORIG-GUID: fw1MrJjM1mAAUVIC_gHBLEN1jwOmC67B X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTE2MDIwMiBTYWx0ZWRfX9hHDIywV7I2V 6nJMng3BgF9x02nkmvn8oMKOjBU0Rm50vaoZZGsOT+I0TtEW+wK1KRhkXvWv0AzIh8oa0/TZLSk 6o0D1n/V4J3CTUaxctq8GsTZD0PeBtnbAPsW4HahFqZLaUojijkpRtrto3HsAsXdCNveOXG/fG8 oumx09CSVzZuRcF7eDBu307utQX9L3RVNTj3vlOpxk7GhSnVUAnAKp7UM2trubis8Pv+PAr3hZX 0JD2P94v/vt1k8/onnfnNk0bbCXUTLTwblrGZiAWnH9UXsdyAEjfT4Noj1cKTCPL7l6xtJd1OPb gAZtlXjfnLRtzu2DiRYHCvbolTL4bdU2GRrlbfoU41wyvkBFKySvyQinEKwRklBkuhLgvsW7VWL HPhcJPc0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-17_01,2025-09-18_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 clxscore=1015 spamscore=0 priorityscore=1501 phishscore=0 malwarescore=0 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509160202 Content-Type: text/plain; charset="utf-8" From: Gregor Herburger When rx_int is used th mcp251xfd_chip_rx_int_enable and mcp251xfd_chip_rx_int_disable function configure both PIN0 and PIN1. To prepare the support of the GPIOS only configure PIN1 with regmap_update_bits. This way PIN0 can be used as GPIO while PIN1 is used as rx_int interrupt. Signed-off-by: Gregor Herburger Tested-by: Viken Dadhaniya Signed-off-by: Viken Dadhaniya --- .../net/can/spi/mcp251xfd/mcp251xfd-core.c | 22 +++++++------------ drivers/net/can/spi/mcp251xfd/mcp251xfd.h | 6 +++++ 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c b/drivers/net/c= an/spi/mcp251xfd/mcp251xfd-core.c index f9eabb1810cf..ea41f04ae1a6 100644 --- a/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c +++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c @@ -608,23 +608,21 @@ static int mcp251xfd_set_bittiming(const struct mcp25= 1xfd_priv *priv) =20 static int mcp251xfd_chip_rx_int_enable(const struct mcp251xfd_priv *priv) { - u32 val; + u32 val, mask; =20 if (!priv->rx_int) return 0; =20 - /* Configure GPIOs: - * - PIN0: GPIO Input - * - PIN1: GPIO Input/RX Interrupt + /* Configure PIN1 as RX Interrupt: * * PIN1 must be Input, otherwise there is a glitch on the * rx-INT line. It happens between setting the PIN as output * (in the first byte of the SPI transfer) and configuring the * PIN as interrupt (in the last byte of the SPI transfer). */ - val =3D MCP251XFD_REG_IOCON_PM0 | MCP251XFD_REG_IOCON_TRIS1 | - MCP251XFD_REG_IOCON_TRIS0; - return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val); + val =3D MCP251XFD_REG_IOCON_TRIS(1); + mask =3D MCP251XFD_REG_IOCON_TRIS(1) | MCP251XFD_REG_IOCON_PM(1); + return regmap_update_bits(priv->map_reg, MCP251XFD_REG_IOCON, mask, val); } =20 static int mcp251xfd_chip_rx_int_disable(const struct mcp251xfd_priv *priv) @@ -634,13 +632,9 @@ static int mcp251xfd_chip_rx_int_disable(const struct = mcp251xfd_priv *priv) if (!priv->rx_int) return 0; =20 - /* Configure GPIOs: - * - PIN0: GPIO Input - * - PIN1: GPIO Input - */ - val =3D MCP251XFD_REG_IOCON_PM1 | MCP251XFD_REG_IOCON_PM0 | - MCP251XFD_REG_IOCON_TRIS1 | MCP251XFD_REG_IOCON_TRIS0; - return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val); + /* Configure PIN1 as GPIO Input */ + val =3D MCP251XFD_REG_IOCON_PM(1) | MCP251XFD_REG_IOCON_TRIS(1); + return regmap_update_bits(priv->map_reg, MCP251XFD_REG_IOCON, val, val); } =20 static int mcp251xfd_chip_ecc_init(struct mcp251xfd_priv *priv) diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd.h b/drivers/net/can/sp= i/mcp251xfd/mcp251xfd.h index dcbbd2b2fae8..bd28510a6583 100644 --- a/drivers/net/can/spi/mcp251xfd/mcp251xfd.h +++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd.h @@ -335,13 +335,19 @@ #define MCP251XFD_REG_IOCON_TXCANOD BIT(28) #define MCP251XFD_REG_IOCON_PM1 BIT(25) #define MCP251XFD_REG_IOCON_PM0 BIT(24) +#define MCP251XFD_REG_IOCON_PM(n) (MCP251XFD_REG_IOCON_PM0 << (n)) #define MCP251XFD_REG_IOCON_GPIO1 BIT(17) #define MCP251XFD_REG_IOCON_GPIO0 BIT(16) +#define MCP251XFD_REG_IOCON_GPIO(n) (MCP251XFD_REG_IOCON_GPIO0 << (n)) +#define MCP251XFD_REG_IOCON_GPIO_MASK GENMASK(17, 16) #define MCP251XFD_REG_IOCON_LAT1 BIT(9) #define MCP251XFD_REG_IOCON_LAT0 BIT(8) +#define MCP251XFD_REG_IOCON_LAT(n) (MCP251XFD_REG_IOCON_LAT0 << (n)) +#define MCP251XFD_REG_IOCON_LAT_MASK GENMASK(9, 8) #define MCP251XFD_REG_IOCON_XSTBYEN BIT(6) #define MCP251XFD_REG_IOCON_TRIS1 BIT(1) #define MCP251XFD_REG_IOCON_TRIS0 BIT(0) +#define MCP251XFD_REG_IOCON_TRIS(n) (MCP251XFD_REG_IOCON_TRIS0 << (n)) =20 #define MCP251XFD_REG_CRC 0xe08 #define MCP251XFD_REG_CRC_FERRIE BIT(25) --=20 2.34.1 From nobody Thu Oct 2 10:39:54 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCF742EA48F for ; Thu, 18 Sep 2025 06:49:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758178184; cv=none; b=oYW75p3CrfgQnh6ADCinAYRnNNb2apYaO/4OJCe8s5xzMk3+rkpMksRRQX3r3d7bwKG39qz2zU5Y6pbwXu/U1eaMU4JhkKZBMTr3mvV33mYfaXaq/bmDg74iStrJxqz25x6dUS3XpOpMuqEC/beEVy4i2+g34xtC5EpfYgwe+9Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758178184; c=relaxed/simple; bh=XIJvWvHW265ZfnWJtSD3436SgEvIMakFTAgcB9nrvZ8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=LLYvFhT5/c0YWQgwnhD/lJ5w5CiVsRB0hu6J+AJRTeHmCLulhNeY3JnVe1+P54wjPkoPkQVd1u/zkvxRjmm12oayX+S1wu4nBd1AZjWc/Ae3o6izlVamczDNAjUNUWUX4Q4mw+3Gr1x7+5jNqTsEm3mUGYh3FKIbBEsvUP9BZRg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=CZHo36Yx; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="CZHo36Yx" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 58I3l8pV021420 for ; Thu, 18 Sep 2025 06:49:42 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=EjJ+nnIxrqR 5U0oBFkYaeQwZN8leUg0wI1FoS7e/7j8=; b=CZHo36YxDNt8oUP8IW9a5qXsH2L GlCj8YQMU/hCXAybjfUkQP+zi1Ab3YpRqW/BeifoPYvcC4WP2Uz81fbSCtq6Ag0K 8fGFrT3fubWzX0BJWk/R6ksv8XmywqnB8JyclZeqiTJ9hkymBnZXs7ozVPePUWwK /60/OCLaE/HbfoaYJCK8FO7WYAtK6dF2FHoaYCNQu/L5kct1mzBFNQAMZcbWYKmF Rjt+9jrRl2OyfFnBAe4PCKaI64pATICbZPSunAxFKoXU2YT922HRmlTp65zAYk5h N288XdndfnKFzVr2YxPqYTtOEO8g6oNr5Kog6k7KlhH9EKy+xNchkvWh8eA== Received: from mail-pf1-f200.google.com (mail-pf1-f200.google.com [209.85.210.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 497fy5d91t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Thu, 18 Sep 2025 06:49:41 +0000 (GMT) Received: by mail-pf1-f200.google.com with SMTP id d2e1a72fcca58-77cd58a9939so631824b3a.0 for ; Wed, 17 Sep 2025 23:49:41 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758178180; x=1758782980; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EjJ+nnIxrqR5U0oBFkYaeQwZN8leUg0wI1FoS7e/7j8=; b=S4hui/NLMKcnXhHHkzh2qOit/yMNfF57hPjOHzDokZgCPPvdSBz6JZlqDvvxHMYtaV eXAnX19RVweNFvuETDs+Og2WKaIOgcZGBo2yCTUMxnQ/pdefLlj/h2YuKHMNzzBs1Y2V NVKl7ruWPGfSOLRCC0fcYp9yYkT/8VysVBOAsr5e/HUQgilUcmO/OLQ4i16pKMsZVArS kxooPBglfErb7goB1SwJqEwRHjJnVf+rMj4oqz5M8qO5SuKwn5Hxfhu0WEw4lmsBz6t4 IUrRgDLOtCSds8CpIvtmQ50Kl1wOqGNzk0ydGlUpUk41IeWGhVc07zenfmn9gq32iUL0 aTvg== X-Forwarded-Encrypted: i=1; AJvYcCUYbwPWlXdWu9VaCFfTEjPeRJdSAMHZ9fHGNyRN6dPG50/pLz0NoYEvqQKYT1RdDXTQJ8/CIbwwzZ3FTh4=@vger.kernel.org X-Gm-Message-State: AOJu0YzYj7Di8o/ASTwZ0U7p/ZuqIzWs0pqRj9mtIMxZPLLuTmVm5+4/ Um0oxxb4ilp1TiNPj0KisJNzGIYaUIKIWlzY5bufXOgOYV0Y9ZqX16O7YUqCwr00HxCkLA0p7rq 5EScjda97JicZ4JN/zHpstS8rVrK0HtEkeyU1zYtRcWlglPZWvV9Eel3eFxZmz7mi35I= X-Gm-Gg: ASbGncvUJ1Hxkg62w/9mfojKfAbtkAnUV63lymeoe1Bac4Kuy+q0Ye+zhrGUNKGGwvh 06z60e9/yCn9ciKPLaIkIDVVUiZ5ALrPwdfmp1XMT5HgrTeOmRZRt1iWCrj/1cMOHQr9n+Iis7V Vi6tpHTnBFZebLC2sh1ToecdVqDIE++ecE63wB+GfzX/giKxJJEOm8k5F4wxoC6n8AV+VTWESxK fyD3Yoeqg3M+/gOv44mHcDYiCi42igPKSXBjUj6iIqndoU2XyNTTWVhxk2Emv8mvdbBiDtidr6Y hgyinURigiEgxXJG1i5o+vGDaHS31im+bhAx7qkSka9UBHYweL/mjiHv3YdRWm5d1BKfRxb4K5L f X-Received: by 2002:a05:6a00:8708:b0:772:348b:8883 with SMTP id d2e1a72fcca58-77ce2166ec6mr1811614b3a.13.1758178180496; Wed, 17 Sep 2025 23:49:40 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHCn+8s4q7iimDMW0J/cJw8W6sXaW8w/rvJ/tsR4OfgkpNVdbOMi9w5wb9ge8YKF8CbH3WuYQ== X-Received: by 2002:a05:6a00:8708:b0:772:348b:8883 with SMTP id d2e1a72fcca58-77ce2166ec6mr1811587b3a.13.1758178180013; Wed, 17 Sep 2025 23:49:40 -0700 (PDT) Received: from hu-vdadhani-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-77cff22bdb5sm1356789b3a.94.2025.09.17.23.49.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Sep 2025 23:49:39 -0700 (PDT) From: Viken Dadhaniya To: mkl@pengutronix.de, mani@kernel.org, thomas.kopp@microchip.com, mailhol.vincent@wanadoo.fr, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linus.walleij@linaro.org, brgl@bgdev.pl, linux-can@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: mukesh.savaliya@oss.qualcomm.com, anup.kulkarni@oss.qualcomm.com, Gregor Herburger , Viken Dadhaniya Subject: [PATCH v4 5/6] can: mcp251xfd: add gpio functionality Date: Thu, 18 Sep 2025 12:19:02 +0530 Message-Id: <20250918064903.241372-6-viken.dadhaniya@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250918064903.241372-1-viken.dadhaniya@oss.qualcomm.com> References: <20250918064903.241372-1-viken.dadhaniya@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: uuxIrRcfRc1LqUqBKKBNzC7kaVVYBDw9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTE2MDIwMiBTYWx0ZWRfX3RKqm35UR/sY RWeF+eqSO5Sc7MdoflEJKv7jZtBShVkVdPZq7Ulv60rr/ahXfhoralOudagOCJTYlf4S0t8jvnC HqitMIIHkpGYy5hWHDTxRJ7AtvjK7GLQjs000Q4Nct7Yc3dCuwdf7Az1wQOXbum/7Qbv8BwBI47 tI1S/tOWlB4thk2pacUPOukv3GAojDMi7K0TzxhHUHnAYVmTnmUDSeIx8ppdya9nQk4Q7ZXbqG4 +6+qFg3GmKhJUnU7XIMsGEbtwgpBxaHE428CQfau+cxZ0qMlFeaEvH1sOqV5645b9C+xKDoLuiD 3ltDJ6sFOQr+H4hjyZarvuqE4bCJlO7kjSTdpSQ6bYm70NA6/XljN+QoKDq7q/tBJPk+i9XaKN6 1LGNKRBg X-Authority-Analysis: v=2.4 cv=Y+f4sgeN c=1 sm=1 tr=0 ts=68cbab85 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=yJojWOMRYYMA:10 a=8f9FM25-AAAA:8 a=EUspDBNiAAAA:8 a=tLDx1KCooYQGmN993QAA:9 a=zc0IvFSfCIW2DFIPzwfm:22 a=uSNRK0Bqq4PXrUp6LDpb:22 X-Proofpoint-ORIG-GUID: uuxIrRcfRc1LqUqBKKBNzC7kaVVYBDw9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-17_01,2025-09-18_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 impostorscore=0 phishscore=0 adultscore=0 malwarescore=0 bulkscore=0 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509160202 Content-Type: text/plain; charset="utf-8" From: Gregor Herburger The mcp251xfd devices allow two pins to be configured as gpio. Add this functionality to driver. Signed-off-by: Gregor Herburger Tested-by: Viken Dadhaniya Signed-off-by: Viken Dadhaniya --- .../net/can/spi/mcp251xfd/mcp251xfd-core.c | 179 ++++++++++++++++++ drivers/net/can/spi/mcp251xfd/mcp251xfd.h | 4 + 2 files changed, 183 insertions(+) diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c b/drivers/net/c= an/spi/mcp251xfd/mcp251xfd-core.c index ea41f04ae1a6..8c253091f498 100644 --- a/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c +++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -1797,6 +1798,178 @@ static int mcp251xfd_register_check_rx_int(struct m= cp251xfd_priv *priv) return 0; } =20 +#ifdef CONFIG_GPIOLIB +static const char * const mcp251xfd_gpio_names[] =3D { "GPIO0", "GPIO1" }; + +static int mcp251xfd_gpio_request(struct gpio_chip *chip, unsigned int off= set) +{ + struct mcp251xfd_priv *priv =3D gpiochip_get_data(chip); + u32 pin_mask =3D MCP251XFD_REG_IOCON_PM(offset); + int ret; + + if (priv->rx_int && offset =3D=3D 1) { + netdev_err(priv->ndev, "Can't use GPIO 1 with RX-INT!\n"); + return -EINVAL; + } + + ret =3D pm_runtime_resume_and_get(priv->ndev->dev.parent); + if (ret) + return ret; + + return regmap_update_bits(priv->map_reg, MCP251XFD_REG_IOCON, + pin_mask, pin_mask); +} + +static void mcp251xfd_gpio_free(struct gpio_chip *chip, unsigned int offse= t) +{ + struct mcp251xfd_priv *priv =3D gpiochip_get_data(chip); + + pm_runtime_put(priv->ndev->dev.parent); +} + +static int mcp251xfd_gpio_get_direction(struct gpio_chip *chip, + unsigned int offset) +{ + struct mcp251xfd_priv *priv =3D gpiochip_get_data(chip); + u32 mask =3D MCP251XFD_REG_IOCON_TRIS(offset); + u32 val; + int ret; + + ret =3D regmap_read(priv->map_reg, MCP251XFD_REG_IOCON, &val); + if (ret) + return ret; + + if (mask & val) + return GPIO_LINE_DIRECTION_IN; + + return GPIO_LINE_DIRECTION_OUT; +} + +static int mcp251xfd_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct mcp251xfd_priv *priv =3D gpiochip_get_data(chip); + u32 mask =3D MCP251XFD_REG_IOCON_GPIO(offset); + u32 val; + int ret; + + ret =3D regmap_read(priv->map_reg, MCP251XFD_REG_IOCON, &val); + if (ret) + return ret; + + return !!(mask & val); +} + +static int mcp251xfd_gpio_get_multiple(struct gpio_chip *chip, unsigned lo= ng *mask, + unsigned long *bit) +{ + struct mcp251xfd_priv *priv =3D gpiochip_get_data(chip); + u32 val; + int ret; + + ret =3D regmap_read(priv->map_reg, MCP251XFD_REG_IOCON, &val); + if (ret) + return ret; + + *bit =3D FIELD_GET(MCP251XFD_REG_IOCON_GPIO_MASK, val) & *mask; + + return 0; +} + +static int mcp251xfd_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct mcp251xfd_priv *priv =3D gpiochip_get_data(chip); + u32 dir_mask =3D MCP251XFD_REG_IOCON_TRIS(offset); + u32 val_mask =3D MCP251XFD_REG_IOCON_LAT(offset); + u32 val; + + if (value) + val =3D val_mask; + else + val =3D 0; + + return regmap_update_bits(priv->map_reg, MCP251XFD_REG_IOCON, + dir_mask | val_mask, val); +} + +static int mcp251xfd_gpio_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + struct mcp251xfd_priv *priv =3D gpiochip_get_data(chip); + u32 dir_mask =3D MCP251XFD_REG_IOCON_TRIS(offset); + + return regmap_update_bits(priv->map_reg, MCP251XFD_REG_IOCON, + dir_mask, dir_mask); +} + +static void mcp251xfd_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + struct mcp251xfd_priv *priv =3D gpiochip_get_data(chip); + u32 val_mask =3D MCP251XFD_REG_IOCON_LAT(offset); + u32 val; + int ret; + + if (value) + val =3D val_mask; + else + val =3D 0; + + ret =3D regmap_update_bits(priv->map_reg, MCP251XFD_REG_IOCON, + val_mask, val); + if (ret) + dev_err(&priv->spi->dev, "Failed to set GPIO %u: %d\n", + offset, ret); +} + +static void mcp251xfd_gpio_set_multiple(struct gpio_chip *chip, unsigned l= ong *mask, + unsigned long *bits) +{ + struct mcp251xfd_priv *priv =3D gpiochip_get_data(chip); + u32 val; + int ret; + + val =3D FIELD_PREP(MCP251XFD_REG_IOCON_LAT_MASK, *bits); + + ret =3D regmap_update_bits(priv->map_reg, MCP251XFD_REG_IOCON, + MCP251XFD_REG_IOCON_LAT_MASK, val); + if (ret) + dev_err(&priv->spi->dev, "Failed to set GPIOs %d\n", ret); +} + +static int mcp251fdx_gpio_setup(struct mcp251xfd_priv *priv) +{ + struct gpio_chip *gc =3D &priv->gc; + + if (!device_property_present(&priv->spi->dev, "gpio-controller")) + return 0; + + gc->label =3D dev_name(&priv->spi->dev); + gc->parent =3D &priv->spi->dev; + gc->owner =3D THIS_MODULE; + gc->request =3D mcp251xfd_gpio_request; + gc->free =3D mcp251xfd_gpio_free; + gc->get_direction =3D mcp251xfd_gpio_get_direction; + gc->direction_output =3D mcp251xfd_gpio_direction_output; + gc->direction_input =3D mcp251xfd_gpio_direction_input; + gc->get =3D mcp251xfd_gpio_get; + gc->get_multiple =3D mcp251xfd_gpio_get_multiple; + gc->set =3D mcp251xfd_gpio_set; + gc->set_multiple =3D mcp251xfd_gpio_set_multiple; + gc->base =3D -1; + gc->can_sleep =3D true; + gc->ngpio =3D ARRAY_SIZE(mcp251xfd_gpio_names); + gc->names =3D mcp251xfd_gpio_names; + + return devm_gpiochip_add_data(&priv->spi->dev, gc, priv); +} +#else +static inline int mcp251fdx_gpio_setup(struct mcp251xfd_priv *priv) +{ + return 0; +} +#endif + static int mcp251xfd_register_get_dev_id(const struct mcp251xfd_priv *priv, u32 *dev_= id, u32 *effective_speed_hz_slow, @@ -1930,6 +2103,12 @@ static int mcp251xfd_register(struct mcp251xfd_priv = *priv) =20 mcp251xfd_ethtool_init(priv); =20 + err =3D mcp251fdx_gpio_setup(priv); + if (err) { + dev_err_probe(&priv->spi->dev, err, "Failed to register gpio-controller.= \n"); + goto out_runtime_disable; + } + err =3D register_candev(ndev); if (err) goto out_runtime_disable; diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd.h b/drivers/net/can/sp= i/mcp251xfd/mcp251xfd.h index bd28510a6583..fd9e005708e4 100644 --- a/drivers/net/can/spi/mcp251xfd/mcp251xfd.h +++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd.h @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -676,6 +677,9 @@ struct mcp251xfd_priv { =20 struct mcp251xfd_devtype_data devtype_data; struct can_berr_counter bec; +#ifdef CONFIG_GPIOLIB + struct gpio_chip gc; +#endif }; =20 #define MCP251XFD_IS(_model) \ --=20 2.34.1 From nobody Thu Oct 2 10:39:54 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5170E2D7DFE for ; Thu, 18 Sep 2025 06:49:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758178189; cv=none; b=BMqqP2+OU+BUQ0b/yJ7VdGZvlTLGdk8qc+iAKrs363EPTXooUn895ba63MSMDuFxTO2sVDqUECAGWKDF2kJxTtx0OXWVqvMi4LDfDEdt/Gdi137xcLNnnUdBJkNRHr4U6ctSK2dG4uO12lcCth7RZL0sN6uN4echOyGQmkIYW7U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758178189; c=relaxed/simple; bh=EDxK0JAECJqknU7nyBNM/XjceytGlGUL11eBwTOLESE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=KoklQaaGDSoWLBGnaoveUHEnlXD1fJsEliKMlwovkwwipDx3wQ3iPCPmDKq9YX2ZnXmfJxQtS7CGR31ylL89/M9jx02pJ37XBFIVZyVxX/W5sHxCd18nNvntbi84Hsi6SXzGRd5/zbR4BwtTKcpO/kw5+jU7jxS9pnJqpoeZsaY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=cENixNJJ; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="cENixNJJ" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 58I3V96s010769 for ; Thu, 18 Sep 2025 06:49:47 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=dzJS/eOWAno Hpfft1/dBeRGBEhv7bksVWKJ4cITaZw8=; b=cENixNJJK/h9/M/2CyV2djLyEcm PWAfS6nYBYj4IM1o5HhaYZ7RqgOVdD3V9tz72prPrBo+yIxsm+XL3r1hzrNMsmpL MQBSGImqqtEniqctJt5uYVSfxIKFcp4TVDGDZHvbAiFlbd8k/aXJDhd1MYmiTA7/ cnBjJDtn8qSnuJCODaiOAcbcbpTQQ1W55vZvwZc8aQpgYWoEQOuq0O4L2pMxEDb8 0zWSZteX6riJnKbwpkCAGyk3q3O6CWKt3NHm1LjQtT62AVoIy0cR6s2bT9pVMjwm MXKL2kt8moqOIjuxqRTuWAnZdx0EEg3gHAAc+GCKtSne2cGKZ5vqDm7BY7g== Received: from mail-pf1-f198.google.com (mail-pf1-f198.google.com [209.85.210.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 497fxxw88j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Thu, 18 Sep 2025 06:49:47 +0000 (GMT) Received: by mail-pf1-f198.google.com with SMTP id d2e1a72fcca58-77267239591so1077943b3a.2 for ; Wed, 17 Sep 2025 23:49:47 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1758178187; x=1758782987; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dzJS/eOWAnoHpfft1/dBeRGBEhv7bksVWKJ4cITaZw8=; b=SeEL7Whax9uHx68rm7vcL6hrPui9PrdzK024vaj4783iLUf6GkmpEth91DuRJbnsX6 paRZ1MsVrtU4llyZvhjgxDSdy4X+wYz1jrVYAcijB1xIOvvIsZ1aQwpcx5H3GaPw8DX/ gwMS+1nKSPKOCGpcg5WRE3RnadXw9L5LxjpZ3LdSLBmuoYrLxjZzlKM2AaESnja14Sat Cwn5k1kvyZbJnJq04WP8JX5iy92bFCK05vL0xHxJg+yIjwVXc75wfMEYg1KoZbdfC1G+ rYk4C10mOpKTERFnF4YyUkFPtpN39Mi1WzXNNNZ3yR2wsKD4yyorwoS5uJ7Ug5Hi1fGY Xc3w== X-Forwarded-Encrypted: i=1; AJvYcCXjxzyJfo+rFlZdMDBdnCOx9ANMqDjnMiJZagiH7STiwYp+27PQ7O0GkbpxPFjFy3zw2LGp1b11BsIcRek=@vger.kernel.org X-Gm-Message-State: AOJu0Yz3Uq4creZwWao8qY1KZadTyH0fBSeC6vXx52B8ValOeowIrYc+ n8v10nuxW0G4Jgf/6aPXhDP8Ndi8QDBzpw/C8nOgPATm/aTF1rzcwZTpxNfHBtAGKttFz6IUSy/ RloM81Y183HNmyMtC7P6y9Rkhb5Wto1Mit3nxvuCqAd0EvGwfQjMZKP/ScenOumrbBqQ= X-Gm-Gg: ASbGnctrFX2txhAcvta3GQvQvhAUrkJTcnw8z5sqo8wy+8VxxSgpnttm6JoiSxFP+kI k9ZsScoNXsDXUxA//zJrXqRyCkq3n3J2aXw4RLJgQutyWc/f9SmAvFBdiMHziteFiH2MlsK5BwQ a7XW/GWUNHeNgjDvnssQIW+WiW69SSyfO9IiLFbOQoWF227WRxfboCaHpcDKqf/MajydHxjmZfV BGK88LNF0zvvAN+RyXAoynkmx3YMTyUnJt32jb0u5rIQzmVHMVPPdvIgtQR2ukR4p0JwrJ//TYa QcQ7+6RCnQ+esTbWwy6klutguzlyuzqXE6WOx5pjgadutG+bAorAwTfkIJplq2Vqwqdux+V7nsf o X-Received: by 2002:a05:6a00:39a3:b0:771:e3d7:4320 with SMTP id d2e1a72fcca58-77bf9c4ee61mr5751223b3a.19.1758178186657; Wed, 17 Sep 2025 23:49:46 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHY0H1OHgZXTD07nw2+cuSZdMjUSSXrxm4zMX8TS1uckPmlzXEVaCFUKW165uUvcbg/3u2M9g== X-Received: by 2002:a05:6a00:39a3:b0:771:e3d7:4320 with SMTP id d2e1a72fcca58-77bf9c4ee61mr5751194b3a.19.1758178186193; Wed, 17 Sep 2025 23:49:46 -0700 (PDT) Received: from hu-vdadhani-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-77cff22bdb5sm1356789b3a.94.2025.09.17.23.49.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Sep 2025 23:49:45 -0700 (PDT) From: Viken Dadhaniya To: mkl@pengutronix.de, mani@kernel.org, thomas.kopp@microchip.com, mailhol.vincent@wanadoo.fr, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linus.walleij@linaro.org, brgl@bgdev.pl, linux-can@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: mukesh.savaliya@oss.qualcomm.com, anup.kulkarni@oss.qualcomm.com, Gregor Herburger , Krzysztof Kozlowski , Viken Dadhaniya Subject: [PATCH v4 6/6] dt-bindings: can: mcp251xfd: add gpio-controller property Date: Thu, 18 Sep 2025 12:19:03 +0530 Message-Id: <20250918064903.241372-7-viken.dadhaniya@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250918064903.241372-1-viken.dadhaniya@oss.qualcomm.com> References: <20250918064903.241372-1-viken.dadhaniya@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTE2MDIwMiBTYWx0ZWRfX3sq4zJIIR0SL h8pGq4L3nAG3tC1iUFjZUHhkP8DDnbvVZ1ckDxaDo+yAicFWsbCfP20OoJVydLvmeYpoLoZszYQ j1HV2gDDWwoMQxtELXVYI6t6BxYxtU88MryHrZE+0wweRFpArgJ0nagmjp2KZZdPX8ycYLj5VXk 8PqK3xFvpjvQxy3dgQKC8/vM7Ko+CQECEwKhcAFdJNFtpIqJqUDA+oEA8upPoTIK1SaEdauJH2T KyOw3DRVqHtA19Zuw+YbO2F8AnpvIW8pcnr6NlOKnG9+O9xNdRjO0u+202LJPdBJhBykxbRVX1p hzXH8XGYNPOqIe/IenTzzjXz4tinptIDJ6DaY3yc2git/LT6aZ8M3XxwCk0Y55H4n+vkHvavyic esxKlPZ9 X-Proofpoint-ORIG-GUID: NtmrWM8wPflqV6WROlJQandLmz6Uhkow X-Authority-Analysis: v=2.4 cv=KJZaDEFo c=1 sm=1 tr=0 ts=68cbab8b cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=yJojWOMRYYMA:10 a=8f9FM25-AAAA:8 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=ubk9sFcynENsk3o0iIUA:9 a=IoOABgeZipijB_acs4fv:22 a=uSNRK0Bqq4PXrUp6LDpb:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: NtmrWM8wPflqV6WROlJQandLmz6Uhkow X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-17_01,2025-09-18_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 bulkscore=0 adultscore=0 impostorscore=0 suspectscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509160202 Content-Type: text/plain; charset="utf-8" From: Gregor Herburger The mcp251xfd has two pins that can be used as gpio. Add gpio-controller property to binding description. Acked-by: Krzysztof Kozlowski Signed-off-by: Gregor Herburger Signed-off-by: Viken Dadhaniya --- .../devicetree/bindings/net/can/microchip,mcp251xfd.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/net/can/microchip,mcp251xfd.= yaml b/Documentation/devicetree/bindings/net/can/microchip,mcp251xfd.yaml index c155c9c6db39..2d13638ebc6a 100644 --- a/Documentation/devicetree/bindings/net/can/microchip,mcp251xfd.yaml +++ b/Documentation/devicetree/bindings/net/can/microchip,mcp251xfd.yaml @@ -49,6 +49,11 @@ properties: Must be half or less of "clocks" frequency. maximum: 20000000 =20 + gpio-controller: true + + "#gpio-cells": + const: 2 + required: - compatible - reg --=20 2.34.1