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Thu, 18 Sep 2025 06:29:48 -0700 (PDT) From: Jun Nie Date: Thu, 18 Sep 2025 21:28:58 +0800 Subject: [PATCH v16 06/10] drm/msm/dpu: Use dedicated WB number definition Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250918-v6-16-rc2-quad-pipe-upstream-4-v16-6-ff6232e3472f@linaro.org> References: <20250918-v6-16-rc2-quad-pipe-upstream-4-v16-0-ff6232e3472f@linaro.org> In-Reply-To: <20250918-v6-16-rc2-quad-pipe-upstream-4-v16-0-ff6232e3472f@linaro.org> To: Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Rob Clark , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie , Jessica Zhang , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758202147; l=1716; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=PRJ+au3DI7HiuWEGK005K0r17ABM8j6SQDUJwlnMCMI=; b=LCib+BVV8wTLxZd2X7O64JU7UwWu9AMDspmPEKtl2onfR7RP0tAEONojfQ5IvOsin/POXyC4Y Ua4gKxQopuLDEQAr5K4RUIKczTuh4iGAR4E1AoEZREolcmSf0bb7Cd9 X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Currently MAX_CHANNELS_PER_ENC is defined as 2, because 2 channels are supported at most in one encoder. The case of 4 channels per encoder is to be added. To avoid breaking current WB usage case, use dedicated WB definition before 4 WB usage case is supported in future. Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index 1318f9e63ef1e7bab078ae17e39d9ed19c04f465..55b83ba6102d38a9ec97bc4d12a= d31810e4b261a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -56,6 +56,7 @@ (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES) =20 #define MAX_CHANNELS_PER_ENC 2 +#define MAX_CWB_PER_ENC 2 =20 #define IDLE_SHORT_TIMEOUT 1 =20 @@ -182,7 +183,7 @@ struct dpu_encoder_virt { struct dpu_encoder_phys *cur_master; struct dpu_encoder_phys *cur_slave; struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; - struct dpu_hw_cwb *hw_cwb[MAX_CHANNELS_PER_ENC]; + struct dpu_hw_cwb *hw_cwb[MAX_CWB_PER_ENC]; struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; =20 unsigned int dsc_mask; @@ -2389,7 +2390,7 @@ void dpu_encoder_helper_phys_setup_cwb(struct dpu_enc= oder_phys *phys_enc, */ cwb_cfg.input =3D INPUT_MODE_LM_OUT; =20 - for (int i =3D 0; i < MAX_CHANNELS_PER_ENC; i++) { + for (int i =3D 0; i < MAX_CWB_PER_ENC; i++) { hw_cwb =3D dpu_enc->hw_cwb[i]; if (!hw_cwb) continue; --=20 2.34.1