From nobody Thu Oct 2 09:22:10 2025 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35DDF1C5486 for ; Thu, 18 Sep 2025 12:19:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758197999; cv=none; b=VahbK3pqfU54MYKw3mnjD3hL1eblwMT883sBE2S+VptRGE2spQ9jyb40rZxmIqk0yFWPAsiHTz8jXclnfqCLhvXT99KHcyfGQA2RTFb82CS0s0p3+g20dkp563Cnk6oMrc1lvoL1FFAWVdrW8r2SOVjlfiYGbdBvoLT+8oKOfzw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758197999; c=relaxed/simple; bh=fGRUWSeNNcgeqcHRkuxbrMGDyokBFOMlHiqs3FwB0qs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WGcsAMCuQ7F/gP6EIqZlfQM67dok2sIU+n6IOTkVLeRXWHc3I1LxkcRAwPxKCxr27DX7iNNrq0gWNTfMFr3hRBgqDBiTPbM+8JNw0CsXGIozh+qiWqpLFWdLjCVuvVkVV3GXUF9FfDYdaf3UyUdHYgMajh0kRDPDEQix/lMOa3o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from dude04.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::ac]) by metis.whiteo.stw.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1uzDc7-0006mw-CD; Thu, 18 Sep 2025 14:19:51 +0200 From: Jonas Rebmann Date: Thu, 18 Sep 2025 14:19:44 +0200 Subject: [PATCH v2 1/3] dt-bindings: net: dsa: nxp,sja1105: Add reset-gpios property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250918-imx8mp-prt8ml-v2-1-3d84b4fe53de@pengutronix.de> References: <20250918-imx8mp-prt8ml-v2-0-3d84b4fe53de@pengutronix.de> In-Reply-To: <20250918-imx8mp-prt8ml-v2-0-3d84b4fe53de@pengutronix.de> To: Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown , Shengjiu Wang , Shawn Guo , Sascha Hauer , Fabio Estevam , Pengutronix Kernel Team Cc: Vladimir Oltean , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sound@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Jonas Rebmann X-Mailer: b4 0.15-dev-7abec X-Developer-Signature: v=1; a=openpgp-sha256; l=1177; i=jre@pengutronix.de; h=from:subject:message-id; bh=fGRUWSeNNcgeqcHRkuxbrMGDyokBFOMlHiqs3FwB0qs=; b=owGbwMvMwCV2ZcYT3onnbjcwnlZLYsg4/ePJrkCxDh6hXAdHxx22zupJIW+iUxpya/46RTQfr +u0UKzvKGVhEONikBVTZIlVk1MQMva/blZpFwszh5UJZAgDF6cATGTDR4Z/luKnlwbwz5fb5SOh e1Tnz7ZTM2f9W2miMmvFrPgnytPu2TEyLNvzs7Xl2NYFV//06C19WJVYvFAi10dd6nqkhkC5VCE nMwA= X-Developer-Key: i=jre@pengutronix.de; a=openpgp; fpr=0B7B750D5D3CD21B3B130DE8B61515E135CD49B5 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::ac X-SA-Exim-Mail-From: jre@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Both the nxp,sja1105 and the nxp,sja1110 series feature an active-low reset pin, rendering reset-gpios a valid property for all of the nxp,sja1105 family. Signed-off-by: Jonas Rebmann Acked-by: Vladimir Oltean Reviewed-by: Frank Li Reviewed-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml b/D= ocumentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml index 9432565f4f5d..e9dd914b0734 100644 --- a/Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml +++ b/Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml @@ -32,6 +32,15 @@ properties: reg: maxItems: 1 =20 + reset-gpios: + description: + A GPIO connected to the active-low RST_N pin of the SJA1105. Note th= at + reset of this chip is performed via SPI and the RST_N pin must be wi= red + to satisfy the power-up sequence documented in "SJA1105PQRS Applicat= ion + Hints" (AH1704) sec. 2.4.4. Connecting the SJA1105 RST_N pin to a GP= IO is + therefore discouraged. + maxItems: 1 + spi-cpha: true spi-cpol: true =20 --=20 2.51.0.178.g2462961280 From nobody Thu Oct 2 09:22:10 2025 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B747618BBB9 for ; Thu, 18 Sep 2025 12:19:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758197999; cv=none; b=oMcwPQQEEa2q8rYHC4jR5QLYF0w3DkHTf3waESpBS9G9Od43p7xZ42dqCHNav35WnTPmUr8YODCuZK43mkmpI7HHAXU2Ozdu+tgQZyVFTH4Qtun+z6qXD86zpuzSspDxXfL2hnwl55p/EqQgn+YfhU0ijjk/yJQzhKKhTy53BQM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758197999; c=relaxed/simple; bh=XlKfsKtW3FVkpMAoRTgKAJoNasJl5xeOqrWbpeh/7Nk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mmJLLWc6Q5+F+EyROWFpcrloH7/R3MTnXogv4iUqSf9qXLYeOAd4uiXxWhiCbQua6n+xFW0O/P2ReWSfwMrfdby3sDsxIuoinJs4xk1X1ajU4HkAhZMNQclwTOWsQP7mXxMVIg8sC1idhDjfN9536l62KBiqcW4jLewwoGG6Uwg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from dude04.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::ac]) by metis.whiteo.stw.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1uzDc7-0006mw-Ea; Thu, 18 Sep 2025 14:19:51 +0200 From: Jonas Rebmann Date: Thu, 18 Sep 2025 14:19:45 +0200 Subject: [PATCH v2 2/3] dt-bindings: arm: fsl: Add Protonic PRT8ML Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250918-imx8mp-prt8ml-v2-2-3d84b4fe53de@pengutronix.de> References: <20250918-imx8mp-prt8ml-v2-0-3d84b4fe53de@pengutronix.de> In-Reply-To: <20250918-imx8mp-prt8ml-v2-0-3d84b4fe53de@pengutronix.de> To: Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown , Shengjiu Wang , Shawn Guo , Sascha Hauer , Fabio Estevam , Pengutronix Kernel Team Cc: Vladimir Oltean , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sound@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Jonas Rebmann X-Mailer: b4 0.15-dev-7abec X-Developer-Signature: v=1; a=openpgp-sha256; l=1127; i=jre@pengutronix.de; h=from:subject:message-id; bh=XlKfsKtW3FVkpMAoRTgKAJoNasJl5xeOqrWbpeh/7Nk=; b=owGbwMvMwCV2ZcYT3onnbjcwnlZLYsg4/ePp/KRtal9yvstzSXKnz2T0jinkzbz275fRjr+9V TG2cbOmdJSyMIhxMciKKbLEqskpCBn7XzertIuFmcPKBDKEgYtTACYS9Zzhf/rny0fZquQF5//X 5OST7ba63RJ30pPl7pfsX/MLtJo6Qxj+RxQeWxFhv/H2meBX+mvWr1azqr3+zUIi5MvE+J3h3Ja n2AE= X-Developer-Key: i=jre@pengutronix.de; a=openpgp; fpr=0B7B750D5D3CD21B3B130DE8B61515E135CD49B5 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::ac X-SA-Exim-Mail-From: jre@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Add DT compatible string for Protonic PRT8ML board. Acked-by: Rob Herring (Arm) Signed-off-by: Jonas Rebmann --- Documentation/devicetree/bindings/arm/fsl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation= /devicetree/bindings/arm/fsl.yaml index 00cdf490b062..b135f6360733 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1106,6 +1106,7 @@ properties: - gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board - gateworks,imx8mp-gw82xx-2x # i.MX8MP Gateworks Board - gocontroll,moduline-display # GOcontroll Moduline Display = controller + - prt,prt8ml # Protonic PRT8ML - skov,imx8mp-skov-basic # SKOV i.MX8MP baseboard without fr= ontplate - skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control = without panel - skov,imx8mp-skov-revb-lt6 # SKOV i.MX8MP climate control w= ith 7=E2=80=9D panel --=20 2.51.0.178.g2462961280 From nobody Thu Oct 2 09:22:10 2025 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 893482206AC for ; Thu, 18 Sep 2025 12:19:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758198001; cv=none; b=eWbEXI6JqOUEUtk2s8TMuI77Yw1aknskwcSh6QqP6C0tuWYloVtffth4XcKr/gvK23zwen+a86DahpE7Wu7rkXpcI3EKtaMyeN5AE4+gQbcJCoOWwO1ljn/uwnty6wLsJIsOFZjt4ido6bT9SR+Jd3GHMeu9SLqLlNzEASDCJMA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758198001; c=relaxed/simple; bh=kyNMoQ/EnwvMC9d8Qt93p2u59Ov5jx8DHLAs2kk92as=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RhRQmGsFISigPMw88hUplgtENxF9faWshzeto9ONR1ZI5gBDg5cwQyv+y1xHYSrP2VsWdJMNu1HS2CqafLS1eifUs+B+VmIKdsmpNay21pXqk68qpMZ0SIFbOvoVD8j9hPnyrjtKMJXhu134zaIFGm9XkH5tVPuwwy2bnaxwcgY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from dude04.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::ac]) by metis.whiteo.stw.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1uzDc7-0006mw-HD; Thu, 18 Sep 2025 14:19:51 +0200 From: Jonas Rebmann Date: Thu, 18 Sep 2025 14:19:46 +0200 Subject: [PATCH v2 3/3] arm64: dts: add Protonic PRT8ML board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250918-imx8mp-prt8ml-v2-3-3d84b4fe53de@pengutronix.de> References: <20250918-imx8mp-prt8ml-v2-0-3d84b4fe53de@pengutronix.de> In-Reply-To: <20250918-imx8mp-prt8ml-v2-0-3d84b4fe53de@pengutronix.de> To: Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown , Shengjiu Wang , Shawn Guo , Sascha Hauer , Fabio Estevam , Pengutronix Kernel Team Cc: Vladimir Oltean , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sound@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Jonas Rebmann , David Jander , Lucas Stach , Oleksij Rempel X-Mailer: b4 0.15-dev-7abec X-Developer-Signature: v=1; a=openpgp-sha256; l=13608; i=jre@pengutronix.de; h=from:subject:message-id; bh=kyNMoQ/EnwvMC9d8Qt93p2u59Ov5jx8DHLAs2kk92as=; b=owGbwMvMwCV2ZcYT3onnbjcwnlZLYsg4/eOp9zzTXc+soy+o+75RDZ5/PMlhnWz2vLPPc4+89 9/MmvL8XUcpC4MYF4OsmCJLrJqcgpCx/3WzSrtYmDmsTCBDGLg4BWAifPsZ/gefbp555gDPuh7W zl9936fZ3Ip5szP1yOMlK1Yf4phleXILwz+Ddy1/pQ/dudtg+Pdqa4DrvgOeYpymNRyztsw9Y3U xxo0RAA== X-Developer-Key: i=jre@pengutronix.de; a=openpgp; fpr=0B7B750D5D3CD21B3B130DE8B61515E135CD49B5 X-SA-Exim-Connect-IP: 2a0a:edc0:0:1101:1d::ac X-SA-Exim-Mail-From: jre@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Add devicetree for the Protonic PRT8ML. The board is similar to the Protonic PRT8MM but i.MX8MP based. Some features have been removed as the drivers haven't been mainlined yet or other issues where encountered: - Stepper motors to be controlled using motion control subsystem - MIPI/DSI to eDP USB alt-mode - Onboard T1 ethernet (10BASE-T1L+PoDL, 100BASE-T1+PoDL, 1000BASE-T1) Signed-off-by: David Jander Signed-off-by: Lucas Stach Signed-off-by: Oleksij Rempel Signed-off-by: Jonas Rebmann --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/imx8mp-prt8ml.dts | 500 ++++++++++++++++++++= ++++ 2 files changed, 501 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 525ef180481d..0c9abfa8d23d 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -228,6 +228,7 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-nitrogen-smarc-unive= rsal-board.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-phyboard-pollux-rdk.dtb imx8mp-phyboard-pollux-rdk-no-eth-dtbs +=3D imx8mp-phyboard-pollux-rdk.dtb= imx8mp-phycore-no-eth.dtbo dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-phyboard-pollux-rdk-no-eth.dtb +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-prt8ml.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-skov-basic.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-skov-revb-hdmi.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8mp-skov-revb-lt6.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-prt8ml.dts b/arch/arm64/b= oot/dts/freescale/imx8mp-prt8ml.dts new file mode 100644 index 000000000000..5d3b5d114804 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-prt8ml.dts @@ -0,0 +1,500 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 Protonic Holland + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8mp.dtsi" + +/ { + model =3D "Protonic PRT8ML"; + compatible =3D "prt,prt8ml", "fsl,imx8mp"; + + chosen { + stdout-path =3D &uart4; + }; + + pcie_refclk: pcie0-refclk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <100000000>; + }; + + pcie_refclk_oe: pcie0-refclk-oe { + compatible =3D "gpio-gate-clock"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pcie_refclk>; + clocks =3D <&pcie_refclk>; + #clock-cells =3D <0>; + enable-gpios =3D <&gpio5 23 GPIO_ACTIVE_HIGH>; + }; +}; + +&A53_0 { + cpu-supply =3D <&fan53555>; +}; + +&A53_1 { + cpu-supply =3D <&fan53555>; +}; + +&A53_2 { + cpu-supply =3D <&fan53555>; +}; + +&A53_3 { + cpu-supply =3D <&fan53555>; +}; + +&a53_opp_table { + opp-1200000000 { + opp-microvolt =3D <900000>; + }; + + opp-1600000000 { + opp-microvolt =3D <980000>; + }; + + /delete-node/ opp-1800000000; +}; + +&ecspi2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ecspi2>; + cs-gpios =3D <&gpio5 13 GPIO_ACTIVE_HIGH>; + /delete-property/ dmas; + /delete-property/ dma-names; + status =3D "okay"; + + switch@0 { + compatible =3D "nxp,sja1105q"; + reg =3D <0>; + reset-gpios =3D <&gpio_exp_1 4 GPIO_ACTIVE_LOW>; + spi-cpha; + spi-max-frequency =3D <4000000>; + spi-rx-delay-us =3D <1>; + spi-tx-delay-us =3D <1>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@3 { + reg =3D <3>; + label =3D "rj45"; + phy-handle =3D <&rj45_phy>; + phy-mode =3D "rgmii-id"; + }; + + port@4 { + reg =3D <4>; + ethernet =3D <&fec>; + label =3D "cpu"; + phy-mode =3D "rgmii-id"; + rx-internal-delay-ps =3D <2000>; + tx-internal-delay-ps =3D <2000>; + + fixed-link { + full-duplex; + speed =3D <100>; + }; + }; + }; + }; +}; + +&fec { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_fec>; + phy-mode =3D "rgmii"; /* switch inserts delay */ + rx-internal-delay-ps =3D <0>; + tx-internal-delay-ps =3D <0>; + status =3D "okay"; + + fixed-link { + full-duplex; + speed =3D <100>; + }; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + rj45_phy: ethernet-phy@2 { + reg =3D <2>; + reset-gpios =3D <&gpio_exp_1 1 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <10000>; + reset-deassert-us =3D <80000>; + }; + }; +}; + +&flexcan1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan1>; + status =3D "okay"; +}; + +&flexcan2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_flexcan2>; + status =3D "okay"; +}; + +&i2c1 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c1>; + status =3D "okay"; + + ak5558: codec@10 { + compatible =3D "asahi-kasei,ak5558"; + reg =3D <0x10>; + reset-gpios =3D <&gpio_exp_1 2 GPIO_ACTIVE_LOW>; + }; + + gpio_exp_1: gpio@25 { + compatible =3D "nxp,pca9571"; + reg =3D <0x25>; + gpio-controller; + #gpio-cells =3D <2>; + }; +}; + +&i2c2 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c2>; + status =3D "okay"; + + tps65987ddh_0: usb-pd@20 { + compatible =3D "ti,tps6598x"; + reg =3D <0x20>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_tps65987ddh_0>; + interrupts-extended =3D <&gpio1 12 IRQ_TYPE_LEVEL_LOW>; + }; + + gpio_exp_2: gpio@25 { + compatible =3D "nxp,pca9571"; + reg =3D <0x25>; + gpio-controller; + #gpio-cells =3D <2>; + + c0-hreset-hog { + gpio-hog; + gpios =3D <7 GPIO_ACTIVE_LOW>; + line-name =3D "c0-hreset"; + output-low; + }; + + c1-hreset-hog { + gpio-hog; + gpios =3D <6 GPIO_ACTIVE_LOW>; + line-name =3D "c1-hreset"; + output-low; + }; + }; + + fan53555: regulator@60 { + compatible =3D "fcs,fan53555"; + reg =3D <0x60>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_fan53555>; + regulator-name =3D "fan53555"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <980000>; + regulator-always-on; + regulator-boot-on; + fcs,suspend-voltage-selector =3D <1>; + }; +}; + +&i2c3 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c3>; + status =3D "okay"; + + ak4458: codec@11 { + compatible =3D "asahi-kasei,ak4458"; + reg =3D <0x11>; + #sound-dai-cells =3D <0>; + reset-gpios =3D <&gpio_exp_2 5 GPIO_ACTIVE_LOW>; + }; + + tps65987ddh_1: usb-pd@20 { + compatible =3D "ti,tps6598x"; + reg =3D <0x20>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_tps65987ddh_1>; + interrupts-extended =3D <&gpio1 15 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&lcdif1 { + status =3D "okay"; +}; + +&snvs_pwrkey { + status =3D "okay"; +}; + +&uart4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart4>; + status =3D "okay"; +}; + +&usb3_0 { + status =3D "okay"; +}; + +&usb3_1 { + status =3D "okay"; +}; + +&usb3_phy0 { + status =3D "okay"; +}; + +&usb3_phy1 { + status =3D "okay"; +}; + +&usb_dwc3_0 { + dr_mode =3D "host"; + status =3D "okay"; +}; + +&usb_dwc3_1 { + dr_mode =3D "host"; + status =3D "okay"; +}; + +&usdhc2 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + assigned-clocks =3D <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates =3D <100000000>; + bus-width =3D <4>; + cd-gpios =3D <&gpio2 12 GPIO_ACTIVE_LOW>; + no-1-8-v; + sd-uhs-sdr12; + sd-uhs-sdr25; + status =3D "okay"; +}; + +&usdhc3 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc3>; + pinctrl-1 =3D <&pinctrl_usdhc3_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc3_200mhz>; + assigned-clocks =3D <&clk IMX8MP_CLK_USDHC3_ROOT>; + assigned-clock-rates =3D <400000000>; + bus-width =3D <8>; + non-removable; + no-sdio; + no-sd; + status =3D "okay"; +}; + +&wdog1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_wdog>; + fsl,ext-reset-output; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_ecspi2: ecspi2grp { + fsl,pins =3D < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x154 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x154 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x154 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x154 + >; + }; + + pinctrl_fan53555: fan53555grp { + fsl,pins =3D < + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x114 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins =3D < + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins =3D < + MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x154 + MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x154 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins =3D < + MX8MP_IOMUXC_ECSPI1_SCLK__I2C1_SCL 0x400000c3 + MX8MP_IOMUXC_ECSPI1_MOSI__I2C1_SDA 0x400000c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400000c3 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400000c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins =3D < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400000c3 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400000c3 + >; + }; + + pinctrl_pcie_refclk: pcierefclkgrp { + fsl,pins =3D < + MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0xc6 + >; + }; + + pinctrl_tps65987ddh_0: tps65987ddh_0grp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x1d0 + >; + }; + + pinctrl_tps65987ddh_1: tps65987ddh_1grp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1d0 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins =3D < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x040 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x040 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins =3D < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0d4 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins =3D < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins =3D < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins =3D < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins =3D < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 + >; + }; +}; --=20 2.51.0.178.g2462961280