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Introduce new LDOs & SMPSs under them (PMIC5 subtype 530 for both). For these new LDOs support a new optimum power mode(OPM). In this mode LDO will automatically switch between high power mode (HPM) and low power mode (LPM) based on the real-time LDO load current. Its operation is analogous to SMPS AUTO mode. Reviewed-by: Dmitry Baryshkov Co-developed-by: Jishnu Prakash Signed-off-by: Jishnu Prakash Signed-off-by: Kamal Wadhwa --- drivers/regulator/qcom-rpmh-regulator.c | 188 ++++++++++++++++++++++++++++= +++- 1 file changed, 187 insertions(+), 1 deletion(-) diff --git a/drivers/regulator/qcom-rpmh-regulator.c b/drivers/regulator/qc= om-rpmh-regulator.c index dfb5bf5b72a1ee0a9a87b72c7baabd52779819a3..0a561f1d94523bf479f48e8c206= 2f79cf64f5b5f 100644 --- a/drivers/regulator/qcom-rpmh-regulator.c +++ b/drivers/regulator/qcom-rpmh-regulator.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 // Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. -// Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. +// Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. =20 #define pr_fmt(fmt) "%s: " fmt, __func__ =20 @@ -92,6 +92,11 @@ static const struct resource_name_formats vreg_rsc_name_= lookup[NUM_REGULATOR_TYP #define PMIC5_BOB_MODE_AUTO 6 #define PMIC5_BOB_MODE_PWM 7 =20 +#define PMIC530_LDO_MODE_RETENTION 3 +#define PMIC530_LDO_MODE_LPM 4 +#define PMIC530_LDO_MODE_OPM 5 +#define PMIC530_LDO_MODE_HPM 7 + #define PMIC_ID_LEN 4 /** * struct rpmh_vreg_hw_data - RPMh regulator hardware configurations @@ -557,6 +562,14 @@ static const int pmic_mode_map_pmic5_ldo_hpm[REGULATOR= _MODE_STANDBY + 1] =3D { [REGULATOR_MODE_FAST] =3D -EINVAL, }; =20 +static const int pmic_mode_map_pmic530_ldo[REGULATOR_MODE_STANDBY + 1] =3D= { + [REGULATOR_MODE_INVALID] =3D -EINVAL, + [REGULATOR_MODE_STANDBY] =3D PMIC530_LDO_MODE_RETENTION, + [REGULATOR_MODE_IDLE] =3D PMIC530_LDO_MODE_LPM, + [REGULATOR_MODE_NORMAL] =3D PMIC530_LDO_MODE_OPM, + [REGULATOR_MODE_FAST] =3D PMIC530_LDO_MODE_HPM, +}; + static unsigned int rpmh_regulator_pmic4_ldo_of_map_mode(unsigned int rpmh= _mode) { unsigned int mode; @@ -579,6 +592,30 @@ static unsigned int rpmh_regulator_pmic4_ldo_of_map_mo= de(unsigned int rpmh_mode) return mode; } =20 +static unsigned int rpmh_regulator_pmic530_ldo_of_map_mode(unsigned int rp= mh_mode) +{ + unsigned int mode; + + switch (rpmh_mode) { + case RPMH_REGULATOR_MODE_HPM: + mode =3D REGULATOR_MODE_FAST; + break; + case RPMH_REGULATOR_MODE_AUTO: + mode =3D REGULATOR_MODE_NORMAL; + break; + case RPMH_REGULATOR_MODE_LPM: + mode =3D REGULATOR_MODE_IDLE; + break; + case RPMH_REGULATOR_MODE_RET: + mode =3D REGULATOR_MODE_STANDBY; + break; + default: + mode =3D REGULATOR_MODE_INVALID; + break; + } + return mode; +} + static const int pmic_mode_map_pmic4_smps[REGULATOR_MODE_STANDBY + 1] =3D { [REGULATOR_MODE_INVALID] =3D -EINVAL, [REGULATOR_MODE_STANDBY] =3D PMIC4_SMPS_MODE_RETENTION, @@ -942,6 +979,71 @@ static const struct rpmh_vreg_hw_data pmic5_bob =3D { .of_map_mode =3D rpmh_regulator_pmic4_bob_of_map_mode, }; =20 +static const struct rpmh_vreg_hw_data pmic5_nldo530 =3D { + .regulator_type =3D VRM, + .ops =3D &rpmh_regulator_vrm_drms_ops, + .voltage_ranges =3D (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(320000, 0, 210, 8000), + }, + .n_linear_ranges =3D 1, + .n_voltages =3D 211, + .hpm_min_load_uA =3D 30000, + .pmic_mode_map =3D pmic_mode_map_pmic530_ldo, + .of_map_mode =3D rpmh_regulator_pmic530_ldo_of_map_mode, +}; + +static const struct rpmh_vreg_hw_data pmic5_pldo530_mvp150 =3D { + .regulator_type =3D VRM, + .ops =3D &rpmh_regulator_vrm_drms_ops, + .voltage_ranges =3D (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(1504000, 0, 255, 8000), + }, + .n_linear_ranges =3D 1, + .n_voltages =3D 256, + .hpm_min_load_uA =3D 10000, + .pmic_mode_map =3D pmic_mode_map_pmic530_ldo, + .of_map_mode =3D rpmh_regulator_pmic530_ldo_of_map_mode, +}; + +static const struct rpmh_vreg_hw_data pmic5_pldo530_mvp300 =3D { + .regulator_type =3D VRM, + .ops =3D &rpmh_regulator_vrm_drms_ops, + .voltage_ranges =3D (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(1504000, 0, 255, 8000), + }, + .n_linear_ranges =3D 1, + .n_voltages =3D 256, + .hpm_min_load_uA =3D 20000, + .pmic_mode_map =3D pmic_mode_map_pmic530_ldo, + .of_map_mode =3D rpmh_regulator_pmic530_ldo_of_map_mode, +}; + +static const struct rpmh_vreg_hw_data pmic5_pldo530_mvp600 =3D { + .regulator_type =3D VRM, + .ops =3D &rpmh_regulator_vrm_drms_ops, + .voltage_ranges =3D (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(1504000, 0, 255, 8000), + }, + .n_linear_ranges =3D 1, + .n_voltages =3D 256, + .hpm_min_load_uA =3D 40000, + .pmic_mode_map =3D pmic_mode_map_pmic530_ldo, + .of_map_mode =3D rpmh_regulator_pmic530_ldo_of_map_mode, +}; + +static const struct rpmh_vreg_hw_data pmic5_ftsmps530 =3D { + .regulator_type =3D VRM, + .ops =3D &rpmh_regulator_vrm_ops, + .voltage_ranges =3D (struct linear_range[]) { + REGULATOR_LINEAR_RANGE(252000, 0, 305, 4000), + REGULATOR_LINEAR_RANGE(1480000, 306, 464, 8000), + }, + .n_linear_ranges =3D 2, + .n_voltages =3D 465, + .pmic_mode_map =3D pmic_mode_map_pmic5_smps, + .of_map_mode =3D rpmh_regulator_pmic4_smps_of_map_mode, +}; + #define RPMH_VREG(_name, _vreg_hw_type, _index, _hw_data, _supply_name) \ { \ .name =3D _name, \ @@ -1376,6 +1478,74 @@ static const struct rpmh_vreg_init_data pm6350_vreg_= data[] =3D { RPMH_VREG("ldo22", LDO, 22, &pmic5_nldo, NULL), }; =20 +static const struct rpmh_vreg_init_data pmcx0102_vreg_data[] =3D { + RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps530, "vdd-s1"), + RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps530, "vdd-s2"), + RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps530, "vdd-s3"), + RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps530, "vdd-s4"), + RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps530, "vdd-s5"), + RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps530, "vdd-s6"), + RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps530, "vdd-s7"), + RPMH_VREG("smps8", SMPS, 8, &pmic5_ftsmps530, "vdd-s8"), + RPMH_VREG("smps9", SMPS, 9, &pmic5_ftsmps530, "vdd-s9"), + RPMH_VREG("smps10", SMPS, 10, &pmic5_ftsmps530, "vdd-s10"), + RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo530, "vdd-l1"), + RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo530, "vdd-l2"), + RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo530, "vdd-l3"), + RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo530, "vdd-l4"), + {} +}; + +static const struct rpmh_vreg_init_data pmh0101_vreg_data[] =3D { + RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo530, "vdd-l1-l4-l10"), + RPMH_VREG("ldo2", LDO, 2, &pmic5_pldo530_mvp300, "vdd-l2-l13-l14"= ), + RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo530, "vdd-l3-l11"), + RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo530, "vdd-l1-l4-l10"), + RPMH_VREG("ldo5", LDO, 5, &pmic5_pldo530_mvp150, "vdd-l5-l16"), + RPMH_VREG("ldo6", LDO, 6, &pmic5_pldo530_mvp300, "vdd-l6-l7"), + RPMH_VREG("ldo7", LDO, 7, &pmic5_pldo530_mvp300, "vdd-l6-l7"), + RPMH_VREG("ldo8", LDO, 8, &pmic5_pldo530_mvp150, "vdd-l8-l9"), + RPMH_VREG("ldo9", LDO, 9, &pmic5_pldo515_mv, "vdd-l8-l9"), + RPMH_VREG("ldo10", LDO, 10, &pmic5_nldo530, "vdd-l1-l4-l10"), + RPMH_VREG("ldo11", LDO, 11, &pmic5_nldo530, "vdd-l3-l11"), + RPMH_VREG("ldo12", LDO, 12, &pmic5_nldo530, "vdd-l12"), + RPMH_VREG("ldo13", LDO, 13, &pmic5_pldo530_mvp150, "vdd-l2-l13-l14"), + RPMH_VREG("ldo14", LDO, 14, &pmic5_pldo530_mvp150, "vdd-l2-l13-l14"), + RPMH_VREG("ldo15", LDO, 15, &pmic5_nldo530, "vdd-l15"), + RPMH_VREG("ldo16", LDO, 15, &pmic5_pldo530_mvp600, "vdd-l5-l16"), + RPMH_VREG("ldo17", LDO, 17, &pmic5_pldo515_mv, "vdd-l17"), + RPMH_VREG("ldo18", LDO, 18, &pmic5_nldo530, "vdd-l18"), + RPMH_VREG("bob1", BOB, 1, &pmic5_bob, "vdd-bob1"), + RPMH_VREG("bob2", BOB, 2, &pmic5_bob, "vdd-bob2"), + {} +}; + +static const struct rpmh_vreg_init_data pmh0104_vreg_data[] =3D { + RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps530, "vdd-s1"), + RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps530, "vdd-s2"), + RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps530, "vdd-s3"), + RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps530, "vdd-s4"), + {} +}; + +static const struct rpmh_vreg_init_data pmh0110_vreg_data[] =3D { + RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps530, "vdd-s1"), + RPMH_VREG("smps2", SMPS, 2, &pmic5_ftsmps530, "vdd-s2"), + RPMH_VREG("smps3", SMPS, 3, &pmic5_ftsmps530, "vdd-s3"), + RPMH_VREG("smps4", SMPS, 4, &pmic5_ftsmps530, "vdd-s4"), + RPMH_VREG("smps5", SMPS, 5, &pmic5_ftsmps530, "vdd-s5"), + RPMH_VREG("smps6", SMPS, 6, &pmic5_ftsmps530, "vdd-s6"), + RPMH_VREG("smps7", SMPS, 7, &pmic5_ftsmps530, "vdd-s7"), + RPMH_VREG("smps8", SMPS, 8, &pmic5_ftsmps530, "vdd-s8"), + RPMH_VREG("smps9", SMPS, 9, &pmic5_ftsmps530, "vdd-s9"), + RPMH_VREG("smps10", SMPS, 10, &pmic5_ftsmps530, "vdd-s10"), + RPMH_VREG("ldo1", LDO, 1, &pmic5_nldo530, "vdd-l1"), + RPMH_VREG("ldo2", LDO, 2, &pmic5_nldo530, "vdd-l2"), + RPMH_VREG("ldo3", LDO, 3, &pmic5_nldo530, "vdd-l3"), + RPMH_VREG("ldo4", LDO, 4, &pmic5_nldo530, "vdd-l4"), + {} +}; + static const struct rpmh_vreg_init_data pmx55_vreg_data[] =3D { RPMH_VREG("smps1", SMPS, 1, &pmic5_ftsmps510, "vdd-s1"), RPMH_VREG("smps2", SMPS, 2, &pmic5_hfsmps510, "vdd-s2"), @@ -1728,6 +1898,22 @@ static const struct of_device_id __maybe_unused rpmh= _regulator_match_table[] =3D { .compatible =3D "qcom,pmc8380-rpmh-regulators", .data =3D pmc8380_vreg_data, }, + { + .compatible =3D "qcom,pmcx0102-rpmh-regulators", + .data =3D pmcx0102_vreg_data, + }, + { + .compatible =3D "qcom,pmh0101-rpmh-regulators", + .data =3D pmh0101_vreg_data, + }, + { + .compatible =3D "qcom,pmh0104-rpmh-regulators", + .data =3D pmh0104_vreg_data, + }, + { + .compatible =3D "qcom,pmh0110-rpmh-regulators", + .data =3D pmh0110_vreg_data, + }, { .compatible =3D "qcom,pmm8155au-rpmh-regulators", .data =3D pmm8155au_vreg_data, --=20 2.25.1