From nobody Thu Oct 2 10:55:17 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68C092F0696; Thu, 18 Sep 2025 15:09:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758208151; cv=none; b=VFSh76Kqfqm7MAkBcUX28g9vHHlTyKVWfFM/+kL9aJCv2uQae3B2dd8kj9LF0eXu1LiEToMiIFSP/Ee7FCusSIHOEACP6hedp3FU1h8cmK4v/S5R/zKcekVStJWeTc+7eic/8z1em3m1eLkTP7gL41DJoHAeRmpcpBs0LRIfU5w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758208151; c=relaxed/simple; bh=o9AvCqe1RapLzw4aumy2aAH7frFxWhYPrfFn5/14nH4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=PBT7b2i49c7auxUfvxTCZbX84a8Pr14MG44NK9+Nj0C5rhIppUGdGm3gyGaboweq20Zpsjo26XpdhxysUmK0MJ8EigUnBiMBG/wIE1AzJIoYUEkgwiajjSZR2YyDeJzW2s6FL17M57vi1G0u6lXeI9ykOpoiK+ZVRohTR8dhYzs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=L2wc/UaE; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="L2wc/UaE" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1758208150; x=1789744150; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=o9AvCqe1RapLzw4aumy2aAH7frFxWhYPrfFn5/14nH4=; b=L2wc/UaEF3AN+vCU9QkJ2/rqFP4HHGT2/Mqgwe4RfzxfyhyjGT/ZRpFw BsIkucTJi0FnMdpUERh1xpK0HCCRVMGrZ9HYlmMhc1LW0Zpl4cBjxAJlQ 3Z8vOwyncIIAj09R+zHtWu4+16uYXVgiSzvIEIULtBiPHObvkPn3U8gT2 FNyb7F+jfiHImJF0J9Dr8aF8t7mLuJgVNXm0UvjH9szGENxxWMvk5sBQH EBe9Bmk1ZqdmXWvdXkxmPr0FMCk5wNs7CpDCARQCLgAtB4Hme8vxNC1C9 l5I6unLyIy58CPJnVio0TYikK6FV5/BC8zjKt6FObV8Sgsu8gRbYWTtlV Q==; X-CSE-ConnectionGUID: ugeKBCocT/GeJhh6l5hQPQ== X-CSE-MsgGUID: kDOUUt5uSPa92sro8bHbOg== X-IronPort-AV: E=Sophos;i="6.18,275,1751266800"; d="scan'208";a="47215035" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 18 Sep 2025 08:09:02 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Thu, 18 Sep 2025 08:08:28 -0700 Received: from ROU-LL-M19942.mpu32.int (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Thu, 18 Sep 2025 08:08:25 -0700 From: Cyrille Pitchen Date: Thu, 18 Sep 2025 17:07:35 +0200 Subject: [PATCH v2 1/5] dt-bindings: gpu: add bindings for the Microchip GFX2D GPU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250918-cpitchen-mainline_gfx2d-v2-1-6cfac9d56612@microchip.com> References: <20250918-cpitchen-mainline_gfx2d-v2-0-6cfac9d56612@microchip.com> In-Reply-To: <20250918-cpitchen-mainline_gfx2d-v2-0-6cfac9d56612@microchip.com> To: David Airlie , Simona Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nicolas Ferre , "Alexandre Belloni" , Claudiu Beznea , Russell King CC: , , , , Cyrille Pitchen X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1718; i=cyrille.pitchen@microchip.com; h=from:subject:message-id; bh=o9AvCqe1RapLzw4aumy2aAH7frFxWhYPrfFn5/14nH4=; b=owGbwMvMwCXmf6yzKqEsVIbxtFoSQ8YZheT2tDWp024cqN/DOynw3Mrw28r/3d1Y8h9J1r/JE 5r6Ia+mo5SFQYyLQVZMkeXQm629mcdfPbZ7JSoFM4eVCWQIAxenAExkXgLDP0v9VT6llRvmXlx8 apO47DfWmyqmJ6WaU7S1z9WIM/8+8oGRYVrqtquZ9p+2rFA/paq4L+q03NqXU9ZMZl5+59TpTmX dIEYA X-Developer-Key: i=cyrille.pitchen@microchip.com; a=openpgp; fpr=7A21115D7D6026585D0E183E0EF12AA1BFAC073D The Microchip GFX2D GPU is embedded in the SAM9X60 and SAM9X7 SoC family. Describe how the GFX2D GPU is integrated in these SoCs, including register space, interrupt and clock. Signed-off-by: Cyrille Pitchen Acked-by: Conor Dooley --- .../bindings/gpu/microchip,sam9x60-gfx2d.yaml | 46 ++++++++++++++++++= ++++ 1 file changed, 46 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/microchip,sam9x60-gfx2d.= yaml b/Documentation/devicetree/bindings/gpu/microchip,sam9x60-gfx2d.yaml new file mode 100644 index 0000000000000000000000000000000000000000..0f223ddda694e7edbc9f25c68d1= 7ef01897a55a1 --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/microchip,sam9x60-gfx2d.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpu/microchip,sam9x60-gfx2d.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip GFX2D GPU + +maintainers: + - Cyrille Pitchen + +properties: + compatible: + enum: + - microchip,sam9x60-gfx2d + - microchip,sam9x7-gfx2d + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + gpu@f0018000 { + compatible =3D "microchip,sam9x60-gfx2d"; + reg =3D <0xf0018000 0x4000>; + interrupts =3D <36 IRQ_TYPE_LEVEL_HIGH 0>; + clocks =3D <&pmc PMC_TYPE_PERIPHERAL 36>; + }; + +... --=20 2.48.1