From nobody Thu Oct 2 10:53:49 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id ACD353397C6; Wed, 17 Sep 2025 14:56:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758120990; cv=none; b=XsfCoblHokZ7/Jrdgn0ohzpbkmLTvcms06QyDqhFtlqyYtxknbJwLCedQQ915IpoqNj+1VcfWQqOPy7s1CYIZf7OQkoE7Rd3orKqWHKI9LD1dusc9P+feGZXhRHjzuGbgFBDL4peD5bPyqa59E0mYoVY9hR6XH9UKTjqzD8YxgU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758120990; c=relaxed/simple; bh=GZS8B5riWrRAALkBlvJ27EMS9EH/NTGI1JAuqMGKfoY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ajcET2uH8ivgraFUNAc1Bo2akIBKog8UtM9J9HasIfVnj1mfPfGvwtr5WD0EXzv1du+cYJ05NYGpMxCqJyZb2/0asHhSpOX2KtTzKLNySwEKGXiTHdsD7SZw5x8/7Rb/89MlS0E9cS++0zDjuGDEPZgFVqFRh5PuL2SgO/FHNMM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CA8BA2696; Wed, 17 Sep 2025 07:56:19 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7A2C63F66E; Wed, 17 Sep 2025 07:56:24 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org, oliver.upton@linux.dev, anshuman.khandual@arm.com, robh@kernel.org, james.morse@arm.com, mark.rutland@arm.com, joey.gouly@arm.com, Dave.Martin@arm.com, ahmed.genidi@arm.com, kevin.brodsky@arm.com, scott@os.amperecomputing.com, mbenes@suse.cz, james.clark@linaro.org, frederic@kernel.org, rafael@kernel.org, pavel@kernel.org, ryan.roberts@arm.com, suzuki.poulose@arm.com, maz@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvmarm@lists.linux.dev, Yeoreum Yun Subject: [PATCH v5 1/6] arm64: make SCTLR2_EL1 accessible Date: Wed, 17 Sep 2025 15:56:13 +0100 Message-Id: <20250917145618.1232329-2-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250917145618.1232329-1-yeoreum.yun@arm.com> References: <20250917145618.1232329-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When the kernel runs at EL1, and yet is booted at EL2, HCRX_EL2.SCTLR2En must be set to avoid trapping SCTLR2_EL1 accesses from EL1 to EL2. Ensure this bit is set at the point of initialising EL2. Signed-off-by: Yeoreum Yun Reviewed-by: Marc Zyngier --- arch/arm64/include/asm/el2_setup.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el= 2_setup.h index 46033027510c..d9529dfc4783 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -57,10 +57,16 @@ /* Enable GCS if supported */ mrs_s x1, SYS_ID_AA64PFR1_EL1 ubfx x1, x1, #ID_AA64PFR1_EL1_GCS_SHIFT, #4 - cbz x1, .Lset_hcrx_\@ + cbz x1, .Lskip_hcrx_GCSEn_\@ orr x0, x0, #HCRX_EL2_GCSEn =20 -.Lset_hcrx_\@: +.Lskip_hcrx_GCSEn_\@: + mrs_s x1, SYS_ID_AA64MMFR3_EL1 + ubfx x1, x1, #ID_AA64MMFR3_EL1_SCTLRX_SHIFT, #4 + cbz x1, .Lskip_hcrx_SCTLR2En\@ + orr x0, x0, #HCRX_EL2_SCTLR2En + +.Lskip_hcrx_SCTLR2En\@: msr_s SYS_HCRX_EL2, x0 .Lskip_hcrx_\@: .endm --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Thu Oct 2 10:53:49 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6BE0D330D2A; Wed, 17 Sep 2025 14:56:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758120995; cv=none; b=Yvtt1VulOxLlHrTOfLGbtLIgxy7uw5rSoXXA0yQZ6yBE7d4Xgmy5ghRfj2Hag7ODsx8kIQ0TLE6DFkIwHOwnC8xytGSl8eJynswCg9pcx1Tf4inFmmp4qJjZQVa0HxsIjnGEB+90mKAXm5np1cmbmoQQ/AEh1GsmW8AVLYCJcG4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758120995; c=relaxed/simple; bh=zulPOX+mTVrJzGPMkGhEtoknSVygaW01iNtXdp3oCQ4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=OyikBeOtNxrNdSPfTaCumTNqXiVVd+wH93iF8k1J28HapU/BjPbXf5yTRlGdJqZXd5DSZU+kGTiHxrsP7f2Lw1FHJe/KATQA+6OI8WN19E0m6s5nGl0polrbmMBT3ib6fPaQo9tZLPsTpzukJCaKGEvxGxgh2kz68XYnHrmXWkI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9BCF3267F; Wed, 17 Sep 2025 07:56:23 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 546EC3F66E; Wed, 17 Sep 2025 07:56:28 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org, oliver.upton@linux.dev, anshuman.khandual@arm.com, robh@kernel.org, james.morse@arm.com, mark.rutland@arm.com, joey.gouly@arm.com, Dave.Martin@arm.com, ahmed.genidi@arm.com, kevin.brodsky@arm.com, scott@os.amperecomputing.com, mbenes@suse.cz, james.clark@linaro.org, frederic@kernel.org, rafael@kernel.org, pavel@kernel.org, ryan.roberts@arm.com, suzuki.poulose@arm.com, maz@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvmarm@lists.linux.dev, Yeoreum Yun Subject: [PATCH v5 2/6] arm64: initialise SCTLR2_ELx register at boot time Date: Wed, 17 Sep 2025 15:56:14 +0100 Message-Id: <20250917145618.1232329-3-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250917145618.1232329-1-yeoreum.yun@arm.com> References: <20250917145618.1232329-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The value of the SCTLR2_ELx register is UNKNOWN after reset. If the firmware initializes these registers properly, no additional initialization is required. However, in cases where they are not initialized correctly, initialize the SCTLR2_ELx registers during CPU/vCPU boot to prevent unexpected system behavior caused by invalid values. Signed-off-by: Yeoreum Yun --- arch/arm64/include/asm/assembler.h | 15 +++++++++++++++ arch/arm64/include/asm/el2_setup.h | 7 +++++++ arch/arm64/include/asm/sysreg.h | 5 +++++ arch/arm64/kernel/head.S | 5 +++++ arch/arm64/kernel/hyp-stub.S | 13 +++++++++++++ arch/arm64/kvm/hyp/nvhe/psci-relay.c | 3 +++ 6 files changed, 48 insertions(+) diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/as= sembler.h index 23be85d93348..c25c2aed5125 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -738,6 +738,21 @@ alternative_endif set_sctlr sctlr_el2, \reg .endm =20 +/* Set SCTLR2_ELx to the @reg value. */ +.macro set_sctlr2_elx, el, reg, tmp + mrs_s \tmp, SYS_ID_AA64MMFR3_EL1 + ubfx \tmp, \tmp, #ID_AA64MMFR3_EL1_SCTLRX_SHIFT, #4 + cbz \tmp, .Lskip_sctlr2_\@ + .if \el =3D=3D 2 + msr_s SYS_SCTLR2_EL2, \reg + .elseif \el =3D=3D 12 + msr_s SYS_SCTLR2_EL12, \reg + .else + msr_s SYS_SCTLR2_EL1, \reg + .endif +.Lskip_sctlr2_\@: +.endm + /* * Check whether asm code should yield as soon as it is able. This is * the case if we are currently running in task context, and the diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el= 2_setup.h index d9529dfc4783..2addf7c096fc 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -48,6 +48,12 @@ isb .endm =20 +.macro __init_sctlr2_el2 + mov_q x0, INIT_SCTLR2_EL2 + set_sctlr2_elx 2, x0, x1 + isb +.endm + .macro __init_el2_hcrx mrs x0, id_aa64mmfr1_el1 ubfx x0, x0, #ID_AA64MMFR1_EL1_HCX_SHIFT, #4 @@ -411,6 +417,7 @@ */ .macro init_el2_state __init_el2_sctlr + __init_sctlr2_el2 __init_el2_hcrx __init_el2_timers __init_el2_debug diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index 6604fd6f33f4..8cf489d38724 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -868,6 +868,8 @@ #define INIT_SCTLR_EL2_MMU_OFF \ (SCTLR_EL2_RES1 | ENDIAN_SET_EL2) =20 +#define INIT_SCTLR2_EL2 UL(0) + /* SCTLR_EL1 specific flags. */ #ifdef CONFIG_CPU_BIG_ENDIAN #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE) @@ -888,6 +890,8 @@ SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | SCTLR_EL1_EIS | \ SCTLR_EL1_TSCXT | SCTLR_EL1_EOS) =20 +#define INIT_SCTLR2_EL1 UL(0) + /* MAIR_ELx memory attributes (used by Linux) */ #define MAIR_ATTR_DEVICE_nGnRnE UL(0x00) #define MAIR_ATTR_DEVICE_nGnRE UL(0x04) @@ -1161,6 +1165,7 @@ msr hcr_el2, \reg #endif .endm + #else =20 #include diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index ca04b338cb0d..e42664246e15 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -276,6 +276,8 @@ SYM_INNER_LABEL(init_el1, SYM_L_LOCAL) mov_q x0, INIT_SCTLR_EL1_MMU_OFF pre_disable_mmu_workaround msr sctlr_el1, x0 + mov_q x0, INIT_SCTLR2_EL1 + set_sctlr2_elx 1, x0, x1 isb mov_q x0, INIT_PSTATE_EL1 msr spsr_el1, x0 @@ -308,6 +310,7 @@ SYM_INNER_LABEL(init_el2, SYM_L_LOCAL) isb =20 mov_q x1, INIT_SCTLR_EL1_MMU_OFF + mov_q x2, INIT_SCTLR2_EL1 =20 mrs x0, hcr_el2 and x0, x0, #HCR_E2H @@ -315,11 +318,13 @@ SYM_INNER_LABEL(init_el2, SYM_L_LOCAL) =20 /* Set a sane SCTLR_EL1, the VHE way */ msr_s SYS_SCTLR_EL12, x1 + set_sctlr2_elx 12, x2, x0 mov x2, #BOOT_CPU_FLAG_E2H b 3f =20 2: msr sctlr_el1, x1 + set_sctlr2_elx 1, x2, x0 mov x2, xzr 3: mov x0, #INIT_PSTATE_EL1 diff --git a/arch/arm64/kernel/hyp-stub.S b/arch/arm64/kernel/hyp-stub.S index 36e2d26b54f5..7a59725fdbb6 100644 --- a/arch/arm64/kernel/hyp-stub.S +++ b/arch/arm64/kernel/hyp-stub.S @@ -178,6 +178,19 @@ SYM_CODE_START_LOCAL(enter_vhe) mov_q x0, INIT_SCTLR_EL1_MMU_OFF msr_s SYS_SCTLR_EL12, x0 =20 + mrs_s x0, SYS_ID_AA64MMFR3_EL1 + ubfx x0, x0, #ID_AA64MMFR3_EL1_SCTLRX_SHIFT, #4 + cbz x0, .Lskip_sctlr2 + + // setup SCTLR2_EL2 from EL1 + mrs_s x0, SYS_SCTLR2_EL12 + msr_s SYS_SCTLR2_EL1, x0 + + // clean SCTLR2_EL1 + mov_q x0, INIT_SCTLR2_EL1 + msr_s SYS_SCTLR2_EL12, x0 + +.Lskip_sctlr2: mov x0, xzr =20 eret diff --git a/arch/arm64/kvm/hyp/nvhe/psci-relay.c b/arch/arm64/kvm/hyp/nvhe= /psci-relay.c index c3e196fb8b18..df1180cad7f8 100644 --- a/arch/arm64/kvm/hyp/nvhe/psci-relay.c +++ b/arch/arm64/kvm/hyp/nvhe/psci-relay.c @@ -4,6 +4,7 @@ * Author: David Brazdil */ =20 +#include #include #include #include @@ -219,6 +220,8 @@ asmlinkage void __noreturn __kvm_host_psci_cpu_entry(bo= ol is_cpu_on) release_boot_args(boot_args); =20 write_sysreg_el1(INIT_SCTLR_EL1_MMU_OFF, SYS_SCTLR); + if (cpus_have_final_cap(ARM64_HAS_SCTLR2)) + write_sysreg_el1(INIT_SCTLR2_EL1, SYS_SCTLR2); write_sysreg(INIT_PSTATE_EL1, SPSR_EL2); =20 __host_enter(host_ctxt); --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Thu Oct 2 10:53:49 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0994E33AE92; Wed, 17 Sep 2025 14:56:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758120997; cv=none; b=dPBx2fElsqPXu62UwSi+sFijelz8RFANHdy00fYzpdjuPusra20wmenbEwH+Py/0uRGduI4gWH4O++idETDqoT/CrHNzb5EBgtcKyPp7cZ60rt+oVOZMSzbtts99qSE4I08lWT9i0gn8GhzqOjBqIWwDUPqjxf2gEedf+kvdh7A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758120997; c=relaxed/simple; bh=aM07tPTmulbFpd+C+lCNUoWkh3IHAjAlwjQKMQQd3ew=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=WMfiW/oD5cI27lnA5vLCsHMruRWOmMOZIAbj+y9PAExYVpHnMpFzLP9RLZRPmYHoHra9bAT+DcqHCCWAoSHvU2SFHa/NGcJQJu6WJz85hRtLbTUhvQDu5BcUA5Yj8CaIqAA+V2ytFc+D3WkqI200skn/VwsVbhuFt9GZIYLuipQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6A7152696; Wed, 17 Sep 2025 07:56:27 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 259753F66E; Wed, 17 Sep 2025 07:56:32 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org, oliver.upton@linux.dev, anshuman.khandual@arm.com, robh@kernel.org, james.morse@arm.com, mark.rutland@arm.com, joey.gouly@arm.com, Dave.Martin@arm.com, ahmed.genidi@arm.com, kevin.brodsky@arm.com, scott@os.amperecomputing.com, mbenes@suse.cz, james.clark@linaro.org, frederic@kernel.org, rafael@kernel.org, pavel@kernel.org, ryan.roberts@arm.com, suzuki.poulose@arm.com, maz@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvmarm@lists.linux.dev, Yeoreum Yun Subject: [PATCH v5 3/6] arm64: save/restore SCTLR2_EL1 when cpu_suspend()/resume() Date: Wed, 17 Sep 2025 15:56:15 +0100 Message-Id: <20250917145618.1232329-4-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250917145618.1232329-1-yeoreum.yun@arm.com> References: <20250917145618.1232329-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Save and restore the SCTLR2_EL1 value during cpu_suspend()/resume(), ensuring that the configured value remains consistent across suspend and resume. Signed-off-by: Yeoreum Yun --- arch/arm64/include/asm/suspend.h | 2 +- arch/arm64/mm/proc.S | 24 ++++++++++++++++-------- 2 files changed, 17 insertions(+), 9 deletions(-) diff --git a/arch/arm64/include/asm/suspend.h b/arch/arm64/include/asm/susp= end.h index 0cde2f473971..eb60c9735553 100644 --- a/arch/arm64/include/asm/suspend.h +++ b/arch/arm64/include/asm/suspend.h @@ -2,7 +2,7 @@ #ifndef __ASM_SUSPEND_H #define __ASM_SUSPEND_H =20 -#define NR_CTX_REGS 13 +#define NR_CTX_REGS 14 #define NR_CALLEE_SAVED_REGS 12 =20 /* diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 8c75965afc9e..a330d828270f 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -87,8 +87,12 @@ SYM_FUNC_START(cpu_do_suspend) mrs x9, mdscr_el1 mrs x10, oslsr_el1 mrs x11, sctlr_el1 - get_this_cpu_offset x12 - mrs x13, sp_el0 +alternative_if ARM64_HAS_SCTLR2 + mrs_s x12, SYS_SCTLR2_EL1 +alternative_else_nop_endif + get_this_cpu_offset x13 + mrs x14, sp_el0 + stp x2, x3, [x0] stp x4, x5, [x0, #16] stp x6, x7, [x0, #32] @@ -99,7 +103,7 @@ SYM_FUNC_START(cpu_do_suspend) * Save x18 as it may be used as a platform register, e.g. by shadow * call stack. */ - str x18, [x0, #96] + stp x14, x18, [x0, #96] ret SYM_FUNC_END(cpu_do_suspend) =20 @@ -120,8 +124,8 @@ SYM_FUNC_START(cpu_do_resume) * the buffer to minimize the risk of exposure when used for shadow * call stack. */ - ldr x18, [x0, #96] - str xzr, [x0, #96] + ldp x15, x18, [x0, #96] + str xzr, [x0, #104] msr tpidr_el0, x2 msr tpidrro_el0, x3 msr contextidr_el1, x4 @@ -136,8 +140,12 @@ SYM_FUNC_START(cpu_do_resume) msr mdscr_el1, x10 =20 msr sctlr_el1, x12 - set_this_cpu_offset x13 - msr sp_el0, x14 +alternative_if ARM64_HAS_SCTLR2 + msr_s SYS_SCTLR2_EL1, x13 +alternative_else_nop_endif + + set_this_cpu_offset x14 + msr sp_el0, x15 /* * Restore oslsr_el1 by writing oslar_el1 */ @@ -151,7 +159,7 @@ alternative_if ARM64_HAS_RAS_EXTN msr_s SYS_DISR_EL1, xzr alternative_else_nop_endif =20 - ptrauth_keys_install_kernel_nosync x14, x1, x2, x3 + ptrauth_keys_install_kernel_nosync x15, x1, x2, x3 isb ret SYM_FUNC_END(cpu_do_resume) --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Thu Oct 2 10:53:49 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 22B5A3195F1; Wed, 17 Sep 2025 14:56:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758121001; cv=none; b=RdAnEexcuOXjcsmjucHX6R+1F6uhsmyRN0heNX01zVDXVrjkBCdj9p2i4NoPlqNxYKFSlyd5/qzmIW3RgtAcjApSVrjSlx6nXo/4KnAuWtykutzFDrmyO9NrRTuXPm6163PFmpvKRwRBg/nFx6ixNBhOTOQH72dW7fV5ddnOouQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758121001; c=relaxed/simple; bh=aITkWGOBS37TSRZ45joX1KaJcqBbWgQMFBXQ/ZLns4I=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Mqt2yIw+3gOIm4vFV9WFpxFM1+7thy/djb7sNHqcHYAmBS1v4bFUbU90a5eEry9WPcGssS4yl4zBhJN8zVm6ZHyPvb6iyPo0tfxbqoakdzHe3egqOcqnEGeJK89b7p/TGMyf7+04yMPILCwYlrjtiEcg4uSVHXqwpViRKCyoNvo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 484E3267F; Wed, 17 Sep 2025 07:56:31 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id EBAAE3F66E; Wed, 17 Sep 2025 07:56:35 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org, oliver.upton@linux.dev, anshuman.khandual@arm.com, robh@kernel.org, james.morse@arm.com, mark.rutland@arm.com, joey.gouly@arm.com, Dave.Martin@arm.com, ahmed.genidi@arm.com, kevin.brodsky@arm.com, scott@os.amperecomputing.com, mbenes@suse.cz, james.clark@linaro.org, frederic@kernel.org, rafael@kernel.org, pavel@kernel.org, ryan.roberts@arm.com, suzuki.poulose@arm.com, maz@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvmarm@lists.linux.dev, Yeoreum Yun Subject: [PATCH v5 4/6] arm64: initialise SCTLR2_EL1 at cpu_soft_restart() Date: Wed, 17 Sep 2025 15:56:16 +0100 Message-Id: <20250917145618.1232329-5-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250917145618.1232329-1-yeoreum.yun@arm.com> References: <20250917145618.1232329-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Explicitly initialize the SCTLR2_ELx register before launching a new kernel via kexec() to avoid leaving SCTLR2_ELx with an arbitrary value when the new kernel runs. Signed-off-by: Yeoreum Yun --- arch/arm64/kernel/cpu-reset.S | 3 +++ arch/arm64/kvm/hyp/nvhe/hyp-init.S | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/arm64/kernel/cpu-reset.S b/arch/arm64/kernel/cpu-reset.S index c87445dde674..e2abc8f8c067 100644 --- a/arch/arm64/kernel/cpu-reset.S +++ b/arch/arm64/kernel/cpu-reset.S @@ -30,6 +30,9 @@ * flat identity mapping. */ SYM_TYPED_FUNC_START(cpu_soft_restart) + mov_q x12, INIT_SCTLR2_EL1 + set_sctlr2_elx 1, x12, x8 + mov_q x12, INIT_SCTLR_EL1_MMU_OFF pre_disable_mmu_workaround /* diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-init.S b/arch/arm64/kvm/hyp/nvhe/h= yp-init.S index aada42522e7b..cc569656fe35 100644 --- a/arch/arm64/kvm/hyp/nvhe/hyp-init.S +++ b/arch/arm64/kvm/hyp/nvhe/hyp-init.S @@ -255,6 +255,9 @@ SYM_CODE_START(__kvm_handle_stub_hvc) mov x0, xzr reset: /* Reset kvm back to the hyp stub. */ + mov_q x5, INIT_SCTLR2_EL2 + set_sctlr2_elx 2, x5, x4 + mov_q x5, INIT_SCTLR_EL2_MMU_OFF pre_disable_mmu_workaround msr sctlr_el2, x5 --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Thu Oct 2 10:53:49 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D2A9533AEB7; Wed, 17 Sep 2025 14:56:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758121005; cv=none; b=SGNaDkVBzM9fpYBo9iPGmuaYP4/8IVddHVu151hzOb03Tu7G24q2IgW/z6QRDVJbw878hXmCXzKbe/NmNqG6XbGAIe6Xixlzk1m+efPmDffBOLZ/WLLdkOnMg0yub+7y+VzdfjUzBl/52nCtghEnKWQ3tzcqxA6WTd0LTCmtAVM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758121005; c=relaxed/simple; bh=jpG4OioajyvO9e69rzujynWFs3I89Xv/VGW/yDdnHLY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=JSE3VGRDHrmi9dK2bL/CY+d38VjER+UBF11H3kjBEcuNeYcmeGXTfpY2EU7/ZPzo0PKnk3jCvFarABb8htlbcwIsqfcLnYzzNwIlh/Fi0kgpBzG/lRkaVzSqxa0A8sK7boCah/IZAuXXy62Sqbmq39Vx2T48qaXHrq6DjfDlJ/0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1A134267F; Wed, 17 Sep 2025 07:56:35 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C6D8D3F66E; Wed, 17 Sep 2025 07:56:39 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org, oliver.upton@linux.dev, anshuman.khandual@arm.com, robh@kernel.org, james.morse@arm.com, mark.rutland@arm.com, joey.gouly@arm.com, Dave.Martin@arm.com, ahmed.genidi@arm.com, kevin.brodsky@arm.com, scott@os.amperecomputing.com, mbenes@suse.cz, james.clark@linaro.org, frederic@kernel.org, rafael@kernel.org, pavel@kernel.org, ryan.roberts@arm.com, suzuki.poulose@arm.com, maz@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvmarm@lists.linux.dev, Yeoreum Yun Subject: [PATCH v5 5/6] arm64: make the per-task SCTLR2_EL1 Date: Wed, 17 Sep 2025 15:56:17 +0100 Message-Id: <20250917145618.1232329-6-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250917145618.1232329-1-yeoreum.yun@arm.com> References: <20250917145618.1232329-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some bits in SCTLR2_EL1 that control system behavior can be configured on a per-task basis (e.g., fields related to FEAT_CPA2). To support future use of these fields, SCTLR2_EL1 is maintained per task. On platforms without FEAT_SCTLR2 support, there is no functional change and only minimal performance overhead. Signed-off-by: Yeoreum Yun --- arch/arm64/include/asm/processor.h | 3 +++ arch/arm64/kernel/process.c | 9 +++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/pr= ocessor.h index 61d62bfd5a7b..e066116735c6 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -184,6 +184,7 @@ struct thread_struct { u64 mte_ctrl; #endif u64 sctlr_user; + u64 sctlr2_user; u64 svcr; u64 tpidr2_el0; u64 por_el0; @@ -258,6 +259,8 @@ static inline void task_set_sve_vl_onexec(struct task_s= truct *task, (SCTLR_ELx_ENIA | SCTLR_ELx_ENIB | SCTLR_ELx_ENDA | SCTLR_ELx_ENDB | \ SCTLR_EL1_TCF0_MASK) =20 +#define SCTLR2_USER_MASK (0) + static inline void arch_thread_struct_whitelist(unsigned long *offset, unsigned long *size) { diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 96482a1412c6..e54f192c0629 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -698,6 +698,11 @@ void update_sctlr_el1(u64 sctlr) isb(); } =20 +static void update_sctlr2_el1(u64 sctlr2) +{ + sysreg_clear_set_s(SYS_SCTLR2_EL1, SCTLR2_USER_MASK, sctlr2); +} + /* * Thread switching. */ @@ -737,6 +742,10 @@ struct task_struct *__switch_to(struct task_struct *pr= ev, if (prev->thread.sctlr_user !=3D next->thread.sctlr_user) update_sctlr_el1(next->thread.sctlr_user); =20 + if (alternative_has_cap_unlikely(ARM64_HAS_SCTLR2) && + prev->thread.sctlr2_user !=3D next->thread.sctlr2_user) + update_sctlr2_el1(next->thread.sctlr2_user); + /* the actual thread switch */ last =3D cpu_switch_to(prev, next); =20 --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Thu Oct 2 10:53:49 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C6E073705A1; Wed, 17 Sep 2025 14:56:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758121009; cv=none; b=EzBHwSL+nfYRvxQYyRNEXkAEcyvtCZIN8eWwRMv6gO2hxSw1188l/fie1dfrHhhOontKtNjP0t8lpreQ7uYEeSNMZDfF7RbvG6Fvzqeq0ZlgLhZPH/Osf4GRBo1COX5KP+Ylfcvr44TqerhaRf8TxTTsCJGh+BszuB2vdPvd5j4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758121009; c=relaxed/simple; bh=N8YLYPkl4tKVv6OcchZf05oQ0VXHePRCzLklXY2vJXk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=HWtArjlyw0D/TWyYZpmMX6deUnVVy4Z7rzUv8GT2NygSsV5RlGZdABwYm2Q6DjnjhGALZG+JSiKFI3d8ynFZKsnJ5lJRoTOFvTkEaUJrFDyVtTuJjDE3y4/RVLBQUCu/UMVZptrFp8+58cnw/SFMKAJhd0eM/j4pn8sWFTz245U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E05F3267F; Wed, 17 Sep 2025 07:56:38 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 98C6C3F66E; Wed, 17 Sep 2025 07:56:43 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org, oliver.upton@linux.dev, anshuman.khandual@arm.com, robh@kernel.org, james.morse@arm.com, mark.rutland@arm.com, joey.gouly@arm.com, Dave.Martin@arm.com, ahmed.genidi@arm.com, kevin.brodsky@arm.com, scott@os.amperecomputing.com, mbenes@suse.cz, james.clark@linaro.org, frederic@kernel.org, rafael@kernel.org, pavel@kernel.org, ryan.roberts@arm.com, suzuki.poulose@arm.com, maz@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvmarm@lists.linux.dev, Yeoreum Yun Subject: [PATCH v5 6/6] docs: arm64: Document booting requirements for FEAT_SCTLR2 Date: Wed, 17 Sep 2025 15:56:18 +0100 Message-Id: <20250917145618.1232329-7-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250917145618.1232329-1-yeoreum.yun@arm.com> References: <20250917145618.1232329-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Dave Martin Support for FEAT_SCTLR2 imposes some requirments on the configuration of traps at exception levels above the level at which the kernel is booted. Document them. For now, don't document requirements on the initial state of SCTLR2_ELx at the kernel boot exception level. The general wording under "System registers" appiles. (SCTLR_ELx is similarly undocumented.) Signed-off-by: Dave Martin Reviewed-by: Yeoreum Yun Signed-off-by: Yeoreum Yun --- Documentation/arch/arm64/booting.rst | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm6= 4/booting.rst index 2f666a7c303c..e8fe1b2023a9 100644 --- a/Documentation/arch/arm64/booting.rst +++ b/Documentation/arch/arm64/booting.rst @@ -545,6 +545,16 @@ Before jumping into the kernel, the following conditio= ns must be met: =20 - MDCR_EL3.TPM (bit 6) must be initialized to 0b0 =20 + For CPUs with the SCTLR2_ELx registers (FEAT_SCTLR2): + + - If EL3 is present: + + - SCR_EL3.SCTLR2En (bit 44) must be initialised to 0b1. + + - If the kernel is entered at EL1 and EL2 is present: + + - HCRX_EL2.SCTLR2En (bit 15) must be initialised to 0b1. + The requirements described above for CPU mode, caches, MMUs, architected timers, coherency and system registers apply to all CPUs. All CPUs must enter the kernel in the same exception level. Where the values documented --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}