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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Sep 2025 13:36:19.3324 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f547864f-0dc7-43d2-4461-08ddf5ef2f2a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000F0E3.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7669 Content-Type: text/plain; charset="utf-8" Remove the restrictive idle check in xilinx_dma_start_transfer() that prevented new transfers from being queued when the channel was busy. Additionally, only update the CURDESC register when the active list is empty to avoid interfering with transfers already in progress. When the active list contains transfers, the hardware tail pointer extension mechanism handles chaining automatically. Signed-off-by: Suraj Gupta Tested-by: Folker Schwesinger --- drivers/dma/xilinx/xilinx_dma.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dm= a.c index 9f416eae33d0..7211c394cdca 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -1548,9 +1548,6 @@ static void xilinx_dma_start_transfer(struct xilinx_d= ma_chan *chan) if (list_empty(&chan->pending_list)) return; =20 - if (!chan->idle) - return; - head_desc =3D list_first_entry(&chan->pending_list, struct xilinx_dma_tx_descriptor, node); tail_desc =3D list_last_entry(&chan->pending_list, @@ -1567,7 +1564,7 @@ static void xilinx_dma_start_transfer(struct xilinx_d= ma_chan *chan) dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); } =20 - if (chan->has_sg) + if (chan->has_sg && list_empty(&chan->active_list)) xilinx_write(chan, XILINX_DMA_REG_CURDESC, head_desc->async_tx.phys); reg &=3D ~XILINX_DMA_CR_DELAY_MAX; --=20 2.25.1