From nobody Thu Oct 2 10:49:37 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A92B2333AB9; Wed, 17 Sep 2025 13:07:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758114444; cv=none; b=O5WE74chClpH+8Ll8kbX6Sjw2A/LR21MyeO35IXabCxikDVheG/farnYOXgBUkD5P7rpDLrFduaeSOphOCFfEYSx/qsaQOHdzD49SErqelI2xk2PrtRSmTQLzSbZ7MJtSl/Fc4Jm/UKacS4SdhPCOUNmoO43hhyz/NKmUtD/gMI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758114444; c=relaxed/simple; bh=zr9iWxQSXUWALae1CDQbywJAgN7uLcn+2p2B+N1bym0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ibsFzHUQIMM8LYLU4IBU3ANDKiREd0xjQxXxamTFw6UltOBKYAp75wMhfOSIouG0sVbDf5T0MWAgeA0WyKbA4vMhO1TPh+a3d0Z/hgkYn/rpdap9w3GmGsagSiFb99Dv8vr+IUS4kOpUCf1+OZ8HT66/ocPeGI5EOH+s3Jvi3eM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=n/MXVBAU; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="n/MXVBAU" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 58HCGSvN009462; Wed, 17 Sep 2025 13:07:12 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= nfDF8r/0C7OOgeJ7IcjUgs+7X24oq7h60D8kYnff45A=; b=n/MXVBAUKctwmCfR gF2aeWBFaCKF7G8JCv4d+QBChMtzP2D3i6/QlwtpVdETbW/CtA3i/dpeTZJUnF+F xV5U7H/hnjheL2lvpKaWLCXXWERGCitZ+pX6/3riJP3SnLqj+fyzpTwaierrySnB dP8fEtekVsr9iVKrjgiGrirPCjUChQ/g6DIyPT9kFIhVSsae0SXJbCj8P1XZOqaH am92TnOE/WrxiRNIRxQ1CiVfN9vWhVIdev0bGeKSMBYP4mkrwTcCDy0FaSSyU3Me ldXpYPZlKCQZstHTyRWzlVOP+/3VqOE/WMq48zbK0SuwLGa7Kl3lhyskHFDoGTtC rJI6Fg== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 497fy1tejm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 17 Sep 2025 13:07:12 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 58HD7Bdo030936 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 17 Sep 2025 13:07:11 GMT Received: from hu-vikramsa-hyd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.24; Wed, 17 Sep 2025 06:07:05 -0700 From: Vikram Sharma To: , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH v3 1/3] dt-bindings: i2c: qcom-cci: Document qcs8300 compatible Date: Wed, 17 Sep 2025 18:36:45 +0530 Message-ID: <20250917130647.1701883-2-quic_vikramsa@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250917130647.1701883-1-quic_vikramsa@quicinc.com> References: <20250917130647.1701883-1-quic_vikramsa@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: gJLrzyL47G45hq9PvGeGxtOFMJTCmCaa X-Proofpoint-ORIG-GUID: gJLrzyL47G45hq9PvGeGxtOFMJTCmCaa X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTE2MDIwMiBTYWx0ZWRfX0b9ZkYmGyWBs b9jFw5YGDv09lWrhoUWXNlw6riyBi33YIt/bmD0XqFdlU84Pyf36xRGx+UrHy8DyiCRRDwn2EcD E5DvlCzplrfchXQNxUKfE3fEvLNTtGZTVD/jvPLzObr4YtCKmtmoxIP/z6lgFDuKuFilALHcnao LWJyl2B3VzClw1YVGl15imvDrmUluvev8DwPE9DHVga0XLoiZWUiqnjuhtLmk0gIH8UsERfx9Ah oCJ/gHxQMvCri3rB3OPYIJugbJG+ym/e4y9HIPIF0J7Ri2tEVGlU4DN3WkQbElfny1iM9nzSMMo CJXRLBa0U0pGW52qAnmY1+P7QfjjgvKlj2FGmrLJkQCXo4al4CoClUGfYEwNdtJXrJaJ9AnknvF 7dH4Rqzx X-Authority-Analysis: v=2.4 cv=cf7SrmDM c=1 sm=1 tr=0 ts=68cab280 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=yJojWOMRYYMA:10 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=phzA4CzYhpZqrDFsW3YA:9 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-17_01,2025-09-17_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 adultscore=0 bulkscore=0 priorityscore=1501 spamscore=0 phishscore=0 impostorscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509160202 Content-Type: text/plain; charset="utf-8" From: Nihal Kumar Gupta The three instances of CCI found on the QCS8300 are functionally the same as on a number of existing Qualcomm SoCs. Introduce a new SoC-specific compatible string "qcom,qcs8300-cci" with a common fallback. Signed-off-by: Nihal Kumar Gupta Signed-off-by: Vikram Sharma Reviewed-by: Bryan O'Donoghue Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Docu= mentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml index 9bc99d736343..5604ce43928d 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml @@ -26,6 +26,7 @@ properties: - items: - enum: - qcom,qcm2290-cci + - qcom,qcs8300-cci - qcom,sa8775p-cci - qcom,sc7280-cci - qcom,sc8280xp-cci @@ -242,6 +243,7 @@ allOf: compatible: contains: enum: + - qcom,qcs8300-cci - qcom,sa8775p-cci - qcom,sm8550-cci - qcom,sm8650-cci --=20 2.25.1 From nobody Thu Oct 2 10:49:37 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73E19302CA6; Wed, 17 Sep 2025 13:07:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758114450; cv=none; b=GP2hJTbO8QqxsmPqE1aplvuFiu/oLpfiiVvCmDhvxx7NI5ql6N6kAhuA+yFbXXjuqw1Vol3HJuBxzv5KmnUq6ulxEx9UKlh+FPwWkXHZ9xRYaXTXlcQhTkgRwfpliL8aInxuCMjl5fu8d8nTH2Q//gALmMRq29nDR1GFvi4+zds= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758114450; c=relaxed/simple; bh=Odn4KbLgXi2qmz80sK9P6a5Yz8yrU2lXepsudfRgyes=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=VfdkAKy5xa2P0Lw6NReA6byk5FnKE3LRpuz4f7ebkwe8CcbXQ8pnEatHSv6YmNkWproAQcW/xADDZ38sZjishJwKZWNMOTWf1O+J8ucn3wCuis6T3nPYj1gb1U0SOXn8xuUsI4/zgfYEnLO+kPfv714WmfQOy4/KVN0nqcFOPQY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=RaYbckQK; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="RaYbckQK" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 58H8Xep2029923; Wed, 17 Sep 2025 13:07:18 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= JLQSjlaxfhs8H3RUg7K68wFtHdRZ05xl1G6Ui8qgGuE=; b=RaYbckQKoPWsZ1UY ZG6/NaUXZecngGxZQMgUOs/iX4oJaD8FSGXDrmMGPvcP6tLr7oYIR5TDY5YwGinY aGJjxa5jQahIpImkEveHIJZrnH/hNTeoyxRS2mtACGjYtq3rXxSKTQlaZc4xoPjc XwGtESr+tLG/MCtJLkpiwN7GA0baNUjgWbVilrE0+UlYtdqxJTIXGgU50rG89a+Y TPqMEt+fycA4cjA+2fnhsM+JY9rzFgg7IXYY5DVNS8d/n8psntSqs5wRgVwQ/bMw dNzzHBdzgOBfLDinEger9R0E4lqWvvCLAq2LZGXl1pN07wFY4ov2pUnNSNpTaDKz jMXFaQ== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 497fxxjf1w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 17 Sep 2025 13:07:18 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 58HD7HaK012000 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 17 Sep 2025 13:07:17 GMT Received: from hu-vikramsa-hyd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.24; Wed, 17 Sep 2025 06:07:11 -0700 From: Vikram Sharma To: , , , , , , , , , , , CC: , , , , , , , , Ravi Shankar , Vishal Verma Subject: [PATCH v3 2/3] arm64: dts: qcom: qcs8300: Add CCI definitions Date: Wed, 17 Sep 2025 18:36:46 +0530 Message-ID: <20250917130647.1701883-3-quic_vikramsa@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250917130647.1701883-1-quic_vikramsa@quicinc.com> References: <20250917130647.1701883-1-quic_vikramsa@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTE2MDIwMiBTYWx0ZWRfX2/S/+RRzAgsd 0UG6cQ/fHSautYhUotf1kCZm7YLEPcg2cXnQMsjdwiUYlnv3GkvkT3sQA55cEwJD8GwlSl5UywT RLxrBQip6hEe6ktNkqhQh0Q5pHAlf5pEoBsnqIPSz5eyFlgr5P/+cPXVreBu8PKADvaSp/4fAn1 CGoKu3TsrshGxqF0op0Y29Ulwe/y8crG90zhtNzM927VHhoGl5em76pmjXpTkkQSbEy7DR2KTnI yjpwCRRH3+kv3rAl0zElHm3OKP5LR6d2oOREZTUpSBjecYYJeEoTE370REzx/F2alWX+PHKmY0Q IbN1AYxmjc6LGN37agcA9uK3bbe2SBLuIKrMVxbnIAl2QTkezIXpt3RkLGrI8BB5Vrh6F9juh2+ ZZ5hhyGy X-Authority-Analysis: v=2.4 cv=MMFgmNZl c=1 sm=1 tr=0 ts=68cab286 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=yJojWOMRYYMA:10 a=COk6AnOGAAAA:8 a=gaqhTMJvxmpqOjxg6FoA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: lgI2NsERue8c0CqoB3Nc7LFyi-3QS1JH X-Proofpoint-GUID: lgI2NsERue8c0CqoB3Nc7LFyi-3QS1JH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-17_01,2025-09-17_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 suspectscore=0 bulkscore=0 spamscore=0 malwarescore=0 phishscore=0 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509160202 Content-Type: text/plain; charset="utf-8" From: Nihal Kumar Gupta Qualcomm QCS8300 SoC contains 3 Camera Control Interface (CCI). Compared to lemans, the key difference is in SDA/SCL GPIO assignments and number of CCIs. Co-developed-by: Ravi Shankar Signed-off-by: Ravi Shankar Co-developed-by: Vishal Verma Signed-off-by: Vishal Verma Co-developed-by: Suresh Vankadara Signed-off-by: Suresh Vankadara Signed-off-by: Nihal Kumar Gupta Signed-off-by: Vikram Sharma --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 309 ++++++++++++++++++++++++++ 1 file changed, 309 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qc= om/qcs8300.dtsi index a248e269d72d..a69719e291ea 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -4681,6 +4681,123 @@ videocc: clock-controller@abf0000 { #power-domain-cells =3D <1>; }; =20 + cci0: cci@ac13000 { + compatible =3D "qcom,qcs8300-cci", "qcom,msm8996-cci"; + reg =3D <0x0 0x0ac13000 0x0 0x1000>; + + interrupts =3D ; + + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>; + clock-names =3D "camnoc_axi", + "cpas_ahb", + "cci"; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 =3D <&cci0_i2c0_default &cci0_i2c1_default>; + pinctrl-1 =3D <&cci0_i2c0_sleep &cci0_i2c1_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci1: cci@ac14000 { + compatible =3D "qcom,qcs8300-cci", "qcom,msm8996-cci"; + reg =3D <0x0 0x0ac14000 0x0 0x1000>; + + interrupts =3D ; + + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>; + clock-names =3D "camnoc_axi", + "cpas_ahb", + "cci"; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 =3D <&cci1_i2c0_default &cci1_i2c1_default>; + pinctrl-1 =3D <&cci1_i2c0_sleep &cci1_i2c1_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + + cci2: cci@ac15000 { + compatible =3D "qcom,qcs8300-cci", "qcom,msm8996-cci"; + reg =3D <0x0 0x0ac15000 0x0 0x1000>; + + interrupts =3D ; + + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_2_CLK>; + clock-names =3D "camnoc_axi", + "cpas_ahb", + "cci"; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + pinctrl-0 =3D <&cci2_i2c0_default &cci2_i2c1_default>; + pinctrl-1 =3D <&cci2_i2c0_sleep &cci2_i2c1_sleep>; + pinctrl-names =3D "default", "sleep"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + cci2_i2c0: i2c-bus@0 { + reg =3D <0>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + cci2_i2c1: i2c-bus@1 { + reg =3D <1>; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + }; + camss: isp@ac78000 { compatible =3D "qcom,qcs8300-camss"; =20 @@ -4975,6 +5092,198 @@ tlmm: pinctrl@f100000 { #interrupt-cells =3D <2>; wakeup-parent =3D <&pdc>; =20 + cci0_i2c0_default: cci0-0-default-state { + sda-pins { + pins =3D "gpio57"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + scl-pins { + pins =3D "gpio58"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + }; + + cci0_i2c0_sleep: cci0-0-sleep-state { + sda-pins { + pins =3D "gpio57"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio58"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci0_i2c1_default: cci0-1-default-state { + sda-pins { + pins =3D "gpio29"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + scl-pins { + pins =3D "gpio30"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + }; + + cci0_i2c1_sleep: cci0-1-sleep-state { + sda-pins { + pins =3D "gpio29"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio30"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci1_i2c0_default: cci1-0-default-state { + sda-pins { + pins =3D "gpio59"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + scl-pins { + pins =3D "gpio60"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + }; + + cci1_i2c0_sleep: cci1-0-sleep-state { + sda-pins { + pins =3D "gpio59"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio60"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci1_i2c1_default: cci1-1-default-state { + sda-pins { + pins =3D "gpio31"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + scl-pins { + pins =3D "gpio32"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + }; + + cci1_i2c1_sleep: cci1-1-sleep-state { + sda-pins { + pins =3D "gpio31"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio32"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci2_i2c0_default: cci2-0-default-state { + sda-pins { + pins =3D "gpio61"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + scl-pins { + pins =3D "gpio62"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + }; + + cci2_i2c0_sleep: cci2-0-sleep-state { + sda-pins { + pins =3D "gpio61"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio62"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + + cci2_i2c1_default: cci2-1-default-state { + sda-pins { + pins =3D "gpio54"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + scl-pins { + pins =3D "gpio55"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + }; + + cci2_i2c1_sleep: cci2-1-sleep-state { + sda-pins { + pins =3D "gpio54"; + function =3D "cci_i2c_sda"; + drive-strength =3D <2>; + bias-pull-down; + }; + + scl-pins { + pins =3D "gpio55"; + function =3D "cci_i2c_scl"; + drive-strength =3D <2>; + bias-pull-down; + }; + }; + hs0_mi2s_active: hs0-mi2s-active-state { pins =3D "gpio106", "gpio107", "gpio108", "gpio109"; function =3D "hs0_mi2s"; --=20 2.25.1 From nobody Thu Oct 2 10:49:37 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0852533AEAF; Wed, 17 Sep 2025 13:07:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758114456; cv=none; b=QnYtw7Sp85plT9letAeAvlIu6apTOifaZyYY3gQFernUk9ZRX8E6J5xIvB8BGlmciE6/LBjTt175mkyrloTWWiafFXUXYqOOJ6G4pVo4+mVaBYfVuKEogtbTXGuBokqbzJ1GU3+zyfXvSc2Iw6pl/KCuVmVny23JAoN2W+mzf+M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758114456; c=relaxed/simple; bh=7KR6HrHJU7oRu+YQt01RqrfJssPhbl8TlOcX5J3670s=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PTaAIC0xI4UU+/LSERT4vg/8axEeBZKjQEnRYqwX8gVxBTw7INXwHgj+5xdQ34JCja8KXrDo7SJc9n3ZlSX6WqQimlxNb6U5VBpcNys0yuw4nNwXvlVH4jzeZblb/MVtCmc50+p8/pVxQvRFZC1ycpnL+IbLPoUEplLwA1BVAZQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=oB8OIlq/; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="oB8OIlq/" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 58HBLAi4027129; Wed, 17 Sep 2025 13:07:24 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= nwMW5r0Tc8149DtyycM8Duh/W1fGQFMGOMvWssNqYbM=; b=oB8OIlq/kMwcVH6s X337WFCS9N13+W27lw/sqZ4lrSToAmeeYnGCHxZp9bF50ozv9F+hZTN13ECJiXMt p51aMeYzVqu7fZuFr+/7Fne4fPeZiCxwdU16i7uxE5MtXBZHOkeCP0Y2DLUcAxZ6 m4W94AEjU/+A1wvSrYV7xs3bAFLBO7l5uAEhOxF58DYvx8zTj2/eviok+ZmBkZia CmGeqARPvOm/iZ0BHadT8pOIXLQJm1NCW6dcBiAzmiyi8oQa7d1Je8Ef+LOBB28x QeNK+npgGMkZBwlJRmIclyJOtcrKMjXv0i9Goh3dpw5gfe9+3n97LrbBI0hOg5Vm /Tcocg== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 497v1j8art-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 17 Sep 2025 13:07:24 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 58HD7NKH008032 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 17 Sep 2025 13:07:23 GMT Received: from hu-vikramsa-hyd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.24; Wed, 17 Sep 2025 06:07:17 -0700 From: Vikram Sharma To: , , , , , , , , , , , CC: , , , , , , , , Ravi Shankar , Vishal Verma Subject: [PATCH v3 3/3] arm64: dts: qcom: monaco-evk-camera: Add DT overlay Date: Wed, 17 Sep 2025 18:36:47 +0530 Message-ID: <20250917130647.1701883-4-quic_vikramsa@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250917130647.1701883-1-quic_vikramsa@quicinc.com> References: <20250917130647.1701883-1-quic_vikramsa@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: DLneAGEA5Bdg85siExV5C3Jmz5VFva9V X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTE3MDExMCBTYWx0ZWRfX3YEGM3htj0LF 05ZQ8cmtDag0xyywqn25UdgZXA8BxG8Emm5bsJUrkJq2aXQ/3iYYPmPHEjrDlzWATgwXdYJ5gDg gRBUcgVZ/5gc8Ps99TberWV3ZT7NoKz83a3ArQLICQbeL/XdOs3AWSi3SAJh72eH6AAfSLHvF/w yzX46KFmvYIJxyH5Zc7B+DrEqJ7o6FY3M0fggHbKNRtWBBYteQylWsrTMxXs8ZBn/ajOCx/Y3Zr RderuWYUpA2Y4D6D405hcF5K5wvI/j8b0qef6AyZ69DLySGTABUx98IMptjC7C0XgQYlKOzoEAx eIUbc8OkYDy2HoLHjWF1U5n3xyOIOYncUILIMSu1FJ3EDfy4zIWt/uV46T+YvZgTuMKOCvzYhbx cxGb09HV X-Authority-Analysis: v=2.4 cv=AeqxH2XG c=1 sm=1 tr=0 ts=68cab28c cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=yJojWOMRYYMA:10 a=COk6AnOGAAAA:8 a=1o0OAiIl6arAuPHRMUsA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: DLneAGEA5Bdg85siExV5C3Jmz5VFva9V X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-17_01,2025-09-17_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 phishscore=0 suspectscore=0 adultscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509170110 Content-Type: text/plain; charset="utf-8" From: Nihal Kumar Gupta Monaco EVK board does not include a camera sensor in its default hardware configuration. Introducing a device tree overlay to support optional integration of the IMX577 sensor via CSIPHY1. Camera reset is handled through an I2C expander, and power is enabled via TLMM GPIO74. An example media-ctl pipeline for the imx577 is: media-ctl --reset media-ctl -V '"imx577 3-001a":0[fmt:SRGGB10/4056x3040 field:none]' media-ctl -V '"msm_csiphy1":0[fmt:SRGGB10/4056x3040]' media-ctl -V '"msm_csid0":0[fmt:SRGGB10/4056x3040]' media-ctl -V '"msm_vfe0_rdi0":0[fmt:SRGGB10/4056x3040]' media-ctl -l '"msm_csiphy1":1->"msm_csid0":0[1]' media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]' yavta -B capture-mplane -c -I -n 5 -f SRGGB10P -s 4056x3040 -F /dev/video1 Co-developed-by: Ravi Shankar Signed-off-by: Ravi Shankar Co-developed-by: Vishal Verma Signed-off-by: Vishal Verma Signed-off-by: Nihal Kumar Gupta Signed-off-by: Vikram Sharma --- arch/arm64/boot/dts/qcom/Makefile | 4 + .../dts/qcom/monaco-evk-camera-imx577.dtso | 96 +++++++++++++++++++ 2 files changed, 100 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/monaco-evk-camera-imx577.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 5b52f9e4e5f3..1c32c54ed841 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -31,6 +31,10 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp453.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp454.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D lemans-evk.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D monaco-evk.dtb + +monaco-evk-camera-imx577-dtbs :=3D monaco-evk.dtb monaco-evk-camera-imx577= .dtbo + +dtb-$(CONFIG_ARCH_QCOM) +=3D monaco-evk-camera-imx577.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8216-samsung-fortuna3g.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-alcatel-idol347.dtb diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-camera-imx577.dtso b/arch/= arm64/boot/dts/qcom/monaco-evk-camera-imx577.dtso new file mode 100644 index 000000000000..2237f0fc4a14 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-evk-camera-imx577.dtso @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + vreg_cam1_2p8: vreg-cam1-2p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_cam1_2p8"; + startup-delay-us =3D <10000>; + enable-active-high; + gpio =3D <&tlmm 74 GPIO_ACTIVE_HIGH>; + }; +}; + +&camss { + vdda-phy-supply =3D <&vreg_l4a>; + vdda-pll-supply =3D <&vreg_l5a>; + + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@1 { + reg =3D <1>; + + csiphy1_ep: endpoint { + clock-lanes =3D <7>; + data-lanes =3D <0 1 2 3>; + remote-endpoint =3D <&imx577_ep1>; + }; + }; + }; +}; + +&cci1 { + pinctrl-0 =3D <&cci1_i2c0_default>; + pinctrl-1 =3D <&cci1_i2c0_sleep>; + + status =3D "okay"; +}; + +&cci1_i2c0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + camera@1a { + compatible =3D "sony,imx577"; + reg =3D <0x1a>; + + reset-gpios =3D <&expander2 1 GPIO_ACTIVE_LOW>; + pinctrl-0 =3D <&cam1_default>; + pinctrl-names =3D "default"; + + clocks =3D <&camcc CAM_CC_MCLK1_CLK>; + assigned-clocks =3D <&camcc CAM_CC_MCLK1_CLK>; + assigned-clock-rates =3D <24000000>; + + avdd-supply =3D <&vreg_cam1_2p8>; + + port { + imx577_ep1: endpoint { + clock-lanes =3D <7>; + link-frequencies =3D /bits/ 64 <600000000>; + data-lanes =3D <0 1 2 3>; + remote-endpoint =3D <&csiphy1_ep>; + }; + }; + }; +}; + +&tlmm { + cam1_default: cam1-default-state { + mclk-pins { + pins =3D "gpio68"; + function =3D "cam_mclk"; + drive-strength =3D <2>; + bias-disable; + }; + + ldo-avdd-pins { + pins =3D "gpio74"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + }; +}; --=20 2.25.1