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charset="utf-8" From: Michael Trimarchi Replace 'SETING' with 'SETTING'. Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi Reviewed-by: Frank Li --- (no changes since v2) Changes in v2: - Add Reviewed-by tag of Frank Li. drivers/input/touchscreen/imx6ul_tsc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/input/touchscreen/imx6ul_tsc.c b/drivers/input/touchsc= reen/imx6ul_tsc.c index 6ac8fa84ed9f..c2c6e50efc54 100644 --- a/drivers/input/touchscreen/imx6ul_tsc.c +++ b/drivers/input/touchscreen/imx6ul_tsc.c @@ -55,7 +55,7 @@ #define ADC_TIMEOUT msecs_to_jiffies(100) =20 /* TSC registers */ -#define REG_TSC_BASIC_SETING 0x00 +#define REG_TSC_BASIC_SETTING 0x00 #define REG_TSC_PRE_CHARGE_TIME 0x10 #define REG_TSC_FLOW_CONTROL 0x20 #define REG_TSC_MEASURE_VALUE 0x30 @@ -192,7 +192,7 @@ static void imx6ul_tsc_set(struct imx6ul_tsc *tsc) =20 basic_setting |=3D tsc->measure_delay_time << 8; basic_setting |=3D DETECT_4_WIRE_MODE | AUTO_MEASURE; - writel(basic_setting, tsc->tsc_regs + REG_TSC_BASIC_SETING); + writel(basic_setting, tsc->tsc_regs + REG_TSC_BASIC_SETTING); =20 writel(DE_GLITCH_2, tsc->tsc_regs + REG_TSC_DEBUG_MODE2); =20 --=20 2.43.0 From nobody Thu Oct 2 11:51:11 2025 Received: from mail-ed1-f46.google.com (mail-ed1-f46.google.com [209.85.208.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 462A4306B21 for ; Wed, 17 Sep 2025 08:05:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758096344; cv=none; b=mqHLSvq98Onku0eMVSxnGNTqqTwyi/n1/x1ttJgU9fZxaFUIn9wfSvmU5qyCnqKdClu9G5UCZVhLh3dZEjgVZyuUc5wpHjUiOPdC8dd63gV9sC3e9hE4VvibrjDwZPYjdxopFZGAsCdkAfJzA2xqWT6NiBB7627IDkSh0ncpuT0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758096344; c=relaxed/simple; bh=SWFqSXFx87fpKeGP6WN4l1K7YHQdzfNtqBr/fu+vOFA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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Wed, 17 Sep 2025 01:05:40 -0700 (PDT) Received: from localhost.localdomain ([2001:b07:6474:ebbf:1215:4a13:8ee5:da2a]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b07e1aed5ffsm924936766b.81.2025.09.17.01.05.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Sep 2025 01:05:40 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Frank Li , Dario Binacchi , Dmitry Torokhov , Fabio Estevam , Michael Trimarchi , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org Subject: [PATCH v4 2/6] Input: imx6ul_tsc - use BIT, FIELD_{GET,PREP} and GENMASK macros Date: Wed, 17 Sep 2025 10:05:07 +0200 Message-ID: <20250917080534.1772202-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250917080534.1772202-1-dario.binacchi@amarulasolutions.com> References: <20250917080534.1772202-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace opencoded masking and shifting, with BIT(), GENMASK(), FIELD_GET() and FIELD_PREP() macros. Signed-off-by: Dario Binacchi Reviewed-by: Frank Li --- (no changes since v2) Changes in v2: - Add Reviewed-by tag of Frank Li. - Move the patch right after the one fixing the typo according to Frank Li's suggestions. drivers/input/touchscreen/imx6ul_tsc.c | 96 +++++++++++++++----------- 1 file changed, 54 insertions(+), 42 deletions(-) diff --git a/drivers/input/touchscreen/imx6ul_tsc.c b/drivers/input/touchsc= reen/imx6ul_tsc.c index c2c6e50efc54..e2c59cc7c82c 100644 --- a/drivers/input/touchscreen/imx6ul_tsc.c +++ b/drivers/input/touchscreen/imx6ul_tsc.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -20,25 +21,23 @@ #include =20 /* ADC configuration registers field define */ -#define ADC_AIEN (0x1 << 7) +#define ADC_AIEN BIT(7) +#define ADC_ADCH_MASK GENMASK(4, 0) #define ADC_CONV_DISABLE 0x1F -#define ADC_AVGE (0x1 << 5) -#define ADC_CAL (0x1 << 7) -#define ADC_CALF 0x2 -#define ADC_12BIT_MODE (0x2 << 2) -#define ADC_CONV_MODE_MASK (0x3 << 2) +#define ADC_AVGE BIT(5) +#define ADC_CAL BIT(7) +#define ADC_CALF BIT(1) +#define ADC_CONV_MODE_MASK GENMASK(3, 2) +#define ADC_12BIT_MODE 0x2 #define ADC_IPG_CLK 0x00 -#define ADC_INPUT_CLK_MASK 0x3 -#define ADC_CLK_DIV_8 (0x03 << 5) -#define ADC_CLK_DIV_MASK (0x3 << 5) -#define ADC_SHORT_SAMPLE_MODE (0x0 << 4) -#define ADC_SAMPLE_MODE_MASK (0x1 << 4) -#define ADC_HARDWARE_TRIGGER (0x1 << 13) -#define ADC_AVGS_SHIFT 14 -#define ADC_AVGS_MASK (0x3 << 14) +#define ADC_INPUT_CLK_MASK GENMASK(1, 0) +#define ADC_CLK_DIV_8 0x03 +#define ADC_CLK_DIV_MASK GENMASK(6, 5) +#define ADC_SAMPLE_MODE BIT(4) +#define ADC_HARDWARE_TRIGGER BIT(13) +#define ADC_AVGS_MASK GENMASK(15, 14) #define SELECT_CHANNEL_4 0x04 #define SELECT_CHANNEL_1 0x01 -#define DISABLE_CONVERSION_INT (0x0 << 7) =20 /* ADC registers */ #define REG_ADC_HC0 0x00 @@ -65,19 +64,26 @@ #define REG_TSC_DEBUG_MODE 0x70 #define REG_TSC_DEBUG_MODE2 0x80 =20 +/* TSC_MEASURE_VALUE register field define */ +#define X_VALUE_MASK GENMASK(27, 16) +#define Y_VALUE_MASK GENMASK(11, 0) + /* TSC configuration registers field define */ -#define DETECT_4_WIRE_MODE (0x0 << 4) -#define AUTO_MEASURE 0x1 -#define MEASURE_SIGNAL 0x1 -#define DETECT_SIGNAL (0x1 << 4) -#define VALID_SIGNAL (0x1 << 8) -#define MEASURE_INT_EN 0x1 -#define MEASURE_SIG_EN 0x1 -#define VALID_SIG_EN (0x1 << 8) -#define DE_GLITCH_2 (0x2 << 29) -#define START_SENSE (0x1 << 12) -#define TSC_DISABLE (0x1 << 16) +#define MEASURE_DELAY_TIME_MASK GENMASK(31, 8) +#define DETECT_5_WIRE_MODE BIT(4) +#define AUTO_MEASURE BIT(0) +#define MEASURE_SIGNAL BIT(0) +#define DETECT_SIGNAL BIT(4) +#define VALID_SIGNAL BIT(8) +#define MEASURE_INT_EN BIT(0) +#define MEASURE_SIG_EN BIT(0) +#define VALID_SIG_EN BIT(8) +#define DE_GLITCH_MASK GENMASK(30, 29) +#define DE_GLITCH_2 0x02 +#define START_SENSE BIT(12) +#define TSC_DISABLE BIT(16) #define DETECT_MODE 0x2 +#define STATE_MACHINE_MASK GENMASK(22, 20) =20 struct imx6ul_tsc { struct device *dev; @@ -112,19 +118,20 @@ static int imx6ul_adc_init(struct imx6ul_tsc *tsc) =20 adc_cfg =3D readl(tsc->adc_regs + REG_ADC_CFG); adc_cfg &=3D ~(ADC_CONV_MODE_MASK | ADC_INPUT_CLK_MASK); - adc_cfg |=3D ADC_12BIT_MODE | ADC_IPG_CLK; - adc_cfg &=3D ~(ADC_CLK_DIV_MASK | ADC_SAMPLE_MODE_MASK); - adc_cfg |=3D ADC_CLK_DIV_8 | ADC_SHORT_SAMPLE_MODE; + adc_cfg |=3D FIELD_PREP(ADC_CONV_MODE_MASK, ADC_12BIT_MODE) | + FIELD_PREP(ADC_INPUT_CLK_MASK, ADC_IPG_CLK); + adc_cfg &=3D ~(ADC_CLK_DIV_MASK | ADC_SAMPLE_MODE); + adc_cfg |=3D FIELD_PREP(ADC_CLK_DIV_MASK, ADC_CLK_DIV_8); if (tsc->average_enable) { adc_cfg &=3D ~ADC_AVGS_MASK; - adc_cfg |=3D (tsc->average_select) << ADC_AVGS_SHIFT; + adc_cfg |=3D FIELD_PREP(ADC_AVGS_MASK, tsc->average_select); } adc_cfg &=3D ~ADC_HARDWARE_TRIGGER; writel(adc_cfg, tsc->adc_regs + REG_ADC_CFG); =20 /* enable calibration interrupt */ adc_hc |=3D ADC_AIEN; - adc_hc |=3D ADC_CONV_DISABLE; + adc_hc |=3D FIELD_PREP(ADC_ADCH_MASK, ADC_CONV_DISABLE); writel(adc_hc, tsc->adc_regs + REG_ADC_HC0); =20 /* start ADC calibration */ @@ -164,19 +171,21 @@ static void imx6ul_tsc_channel_config(struct imx6ul_t= sc *tsc) { u32 adc_hc0, adc_hc1, adc_hc2, adc_hc3, adc_hc4; =20 - adc_hc0 =3D DISABLE_CONVERSION_INT; + adc_hc0 =3D FIELD_PREP(ADC_AIEN, 0); writel(adc_hc0, tsc->adc_regs + REG_ADC_HC0); =20 - adc_hc1 =3D DISABLE_CONVERSION_INT | SELECT_CHANNEL_4; + adc_hc1 =3D FIELD_PREP(ADC_AIEN, 0) | + FIELD_PREP(ADC_ADCH_MASK, SELECT_CHANNEL_4); writel(adc_hc1, tsc->adc_regs + REG_ADC_HC1); =20 - adc_hc2 =3D DISABLE_CONVERSION_INT; + adc_hc2 =3D FIELD_PREP(ADC_AIEN, 0); writel(adc_hc2, tsc->adc_regs + REG_ADC_HC2); =20 - adc_hc3 =3D DISABLE_CONVERSION_INT | SELECT_CHANNEL_1; + adc_hc3 =3D FIELD_PREP(ADC_AIEN, 0) | + FIELD_PREP(ADC_ADCH_MASK, SELECT_CHANNEL_1); writel(adc_hc3, tsc->adc_regs + REG_ADC_HC3); =20 - adc_hc4 =3D DISABLE_CONVERSION_INT; + adc_hc4 =3D FIELD_PREP(ADC_AIEN, 0); writel(adc_hc4, tsc->adc_regs + REG_ADC_HC4); } =20 @@ -188,13 +197,16 @@ static void imx6ul_tsc_channel_config(struct imx6ul_t= sc *tsc) static void imx6ul_tsc_set(struct imx6ul_tsc *tsc) { u32 basic_setting =3D 0; + u32 debug_mode2; u32 start; =20 - basic_setting |=3D tsc->measure_delay_time << 8; - basic_setting |=3D DETECT_4_WIRE_MODE | AUTO_MEASURE; + basic_setting |=3D FIELD_PREP(MEASURE_DELAY_TIME_MASK, + tsc->measure_delay_time); + basic_setting |=3D AUTO_MEASURE; writel(basic_setting, tsc->tsc_regs + REG_TSC_BASIC_SETTING); =20 - writel(DE_GLITCH_2, tsc->tsc_regs + REG_TSC_DEBUG_MODE2); + debug_mode2 =3D FIELD_PREP(DE_GLITCH_MASK, DE_GLITCH_2); + writel(debug_mode2, tsc->tsc_regs + REG_TSC_DEBUG_MODE2); =20 writel(tsc->pre_charge_time, tsc->tsc_regs + REG_TSC_PRE_CHARGE_TIME); writel(MEASURE_INT_EN, tsc->tsc_regs + REG_TSC_INT_EN); @@ -250,7 +262,7 @@ static bool tsc_wait_detect_mode(struct imx6ul_tsc *tsc) =20 usleep_range(200, 400); debug_mode2 =3D readl(tsc->tsc_regs + REG_TSC_DEBUG_MODE2); - state_machine =3D (debug_mode2 >> 20) & 0x7; + state_machine =3D FIELD_GET(STATE_MACHINE_MASK, debug_mode2); } while (state_machine !=3D DETECT_MODE); =20 usleep_range(200, 400); @@ -278,8 +290,8 @@ static irqreturn_t tsc_irq_fn(int irq, void *dev_id) =20 if (status & MEASURE_SIGNAL) { value =3D readl(tsc->tsc_regs + REG_TSC_MEASURE_VALUE); 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charset="utf-8" Add support for glitch threshold configuration. A detected signal is valid only if it lasts longer than the set threshold; otherwise, it is regarded as a glitch. Signed-off-by: Dario Binacchi Acked-by: Conor Dooley --- (no changes since v2) Changes in v2: - Added in v2. .../devicetree/bindings/input/touchscreen/touchscreen.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/input/touchscreen/touchscree= n.yaml b/Documentation/devicetree/bindings/input/touchscreen/touchscreen.ya= ml index 3e3572aa483a..a60b4d08620d 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/touchscreen.yaml +++ b/Documentation/devicetree/bindings/input/touchscreen/touchscreen.yaml @@ -206,6 +206,10 @@ properties: =20 unevaluatedProperties: false =20 + touchscreen-glitch-threshold-ns: + description: Minimum duration in nanoseconds a signal must remain stab= le + to be considered valid. + dependencies: touchscreen-size-x: [ touchscreen-size-y ] touchscreen-size-y: [ touchscreen-size-x ] --=20 2.43.0 From nobody Thu Oct 2 11:51:11 2025 Received: from mail-ed1-f49.google.com (mail-ed1-f49.google.com [209.85.208.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80992308F25 for ; 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Wed, 17 Sep 2025 01:05:43 -0700 (PDT) Received: from localhost.localdomain ([2001:b07:6474:ebbf:1215:4a13:8ee5:da2a]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b07e1aed5ffsm924936766b.81.2025.09.17.01.05.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Sep 2025 01:05:43 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Frank Li , Dario Binacchi , Conor Dooley , Dmitry Torokhov , Fabio Estevam , Haibo Chen , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org Subject: [PATCH v4 4/6] dt-bindings: touchscreen: fsl,imx6ul-tsc: support glitch thresold Date: Wed, 17 Sep 2025 10:05:09 +0200 Message-ID: <20250917080534.1772202-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250917080534.1772202-1-dario.binacchi@amarulasolutions.com> References: <20250917080534.1772202-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support the touchscreen-glitch-threshold-ns property. Drivers must convert this value to IPG clock cycles and map it to one of the four discrete thresholds exposed by the TSC_DEBUG_MODE2 register: 0: 8191 IPG cycles 1: 4095 IPG cycles 2: 2047 IPG cycles 3: 1023 IPG cycles Signed-off-by: Dario Binacchi Reviewed-by: Conor Dooley --- Changes in v4: - Adjust property description following the suggestions of Conor Dooley and Frank Li. - Update the commit description. Changes in v3: - Remove the final part of the description that refers to implementation details. .../bindings/input/touchscreen/fsl,imx6ul-tsc.yaml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/input/touchscreen/fsl,imx6ul= -tsc.yaml b/Documentation/devicetree/bindings/input/touchscreen/fsl,imx6ul-= tsc.yaml index 678756ad0f92..1975f741cf3d 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/fsl,imx6ul-tsc.ya= ml +++ b/Documentation/devicetree/bindings/input/touchscreen/fsl,imx6ul-tsc.ya= ml @@ -62,6 +62,20 @@ properties: description: Number of data samples which are averaged for each read. enum: [ 1, 4, 8, 16, 32 ] =20 + touchscreen-glitch-threshold-ns: + description: | + Minimum duration in nanoseconds a signal must remain stable + to be considered valid. + + Drivers must convert this value to IPG clock cycles and map + it to one of the four discrete thresholds exposed by the + TSC_DEBUG_MODE2 register: + + 0: 8191 IPG cycles + 1: 4095 IPG cycles + 2: 2047 IPG cycles + 3: 1023 IPG cycles + required: - compatible - reg --=20 2.43.0 From nobody Thu Oct 2 11:51:11 2025 Received: from mail-ed1-f52.google.com (mail-ed1-f52.google.com [209.85.208.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC2593090EC for ; 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Wed, 17 Sep 2025 01:05:44 -0700 (PDT) Received: from localhost.localdomain ([2001:b07:6474:ebbf:1215:4a13:8ee5:da2a]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b07e1aed5ffsm924936766b.81.2025.09.17.01.05.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Sep 2025 01:05:44 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Frank Li , Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 5/6] ARM: dts: imx6ull-engicam-microgea-bmm: set touchscreen glitch threshold Date: Wed, 17 Sep 2025 10:05:10 +0200 Message-ID: <20250917080534.1772202-6-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250917080534.1772202-1-dario.binacchi@amarulasolutions.com> References: <20250917080534.1772202-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable This way the detected signal is valid only if it lasts longer than 62 =C2=B5s, otherwise it is not sampled. Signed-off-by: Dario Binacchi Reviewed-by: Frank Li --- (no changes since v1) arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dts b/a= rch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dts index 279d46c22cd7..f12084d8f2a0 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dts @@ -154,6 +154,7 @@ &tsc { pinctrl-0 =3D <&pinctrl_tsc>; measure-delay-time =3D <0x9ffff>; pre-charge-time =3D <0xfff>; + touchscreen-glitch-threshold-ns =3D <62000>; xnur-gpios =3D <&gpio1 3 GPIO_ACTIVE_LOW>; status =3D "okay"; }; --=20 2.43.0 From nobody Thu Oct 2 11:51:11 2025 Received: from mail-ej1-f45.google.com (mail-ej1-f45.google.com [209.85.218.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7111C309DA8 for ; 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Wed, 17 Sep 2025 01:05:46 -0700 (PDT) Received: from localhost.localdomain ([2001:b07:6474:ebbf:1215:4a13:8ee5:da2a]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b07e1aed5ffsm924936766b.81.2025.09.17.01.05.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Sep 2025 01:05:46 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, Frank Li , Dario Binacchi , Dmitry Torokhov , Fabio Estevam , Michael Trimarchi , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org Subject: [PATCH v4 6/6] Input: imx6ul_tsc - set glitch threshold by DTS property Date: Wed, 17 Sep 2025 10:05:11 +0200 Message-ID: <20250917080534.1772202-7-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250917080534.1772202-1-dario.binacchi@amarulasolutions.com> References: <20250917080534.1772202-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Set the glitch threshold previously hardcoded in the driver. The change is backward compatible. Signed-off-by: Dario Binacchi Reviewed-by: Frank Li --- Changes in v4: - Adjust property description fsl,imx6ul-tsc.yaml following the suggestions of Conor Dooley and Frank Li. Changes in v3: - Remove the final part of the description that refers to implementation details in fsl,imx6ul-tsc.yaml. Changes in v2: - Replace patch ("dt-bindings: input: touchscreen: fsl,imx6ul-tsc: add fsl,glitch-threshold") with ("dt-bindings: touchscreen: add touchscreen-glitch-threshold-ns property"), making the previous property general by moving it to touchscreen.yaml. - Rework "Input: imx6ul_tsc - set glitch threshold by DTS property" patch to match changes made to the DTS property. - Move "Input: imx6ul_tsc - use BIT, FIELD_{GET,PREP} and GENMASK macros" patch right after the patch fixing the typo. - Rework to match changes made to the DTS property. drivers/input/touchscreen/imx6ul_tsc.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/input/touchscreen/imx6ul_tsc.c b/drivers/input/touchsc= reen/imx6ul_tsc.c index e2c59cc7c82c..0d753aa05fbf 100644 --- a/drivers/input/touchscreen/imx6ul_tsc.c +++ b/drivers/input/touchscreen/imx6ul_tsc.c @@ -79,7 +79,7 @@ #define MEASURE_SIG_EN BIT(0) #define VALID_SIG_EN BIT(8) #define DE_GLITCH_MASK GENMASK(30, 29) -#define DE_GLITCH_2 0x02 +#define DE_GLITCH_DEF 0x02 #define START_SENSE BIT(12) #define TSC_DISABLE BIT(16) #define DETECT_MODE 0x2 @@ -98,6 +98,7 @@ struct imx6ul_tsc { u32 pre_charge_time; bool average_enable; u32 average_select; + u32 de_glitch; =20 struct completion completion; }; @@ -205,7 +206,7 @@ static void imx6ul_tsc_set(struct imx6ul_tsc *tsc) basic_setting |=3D AUTO_MEASURE; writel(basic_setting, tsc->tsc_regs + REG_TSC_BASIC_SETTING); =20 - debug_mode2 =3D FIELD_PREP(DE_GLITCH_MASK, DE_GLITCH_2); + debug_mode2 =3D FIELD_PREP(DE_GLITCH_MASK, tsc->de_glitch); writel(debug_mode2, tsc->tsc_regs + REG_TSC_DEBUG_MODE2); =20 writel(tsc->pre_charge_time, tsc->tsc_regs + REG_TSC_PRE_CHARGE_TIME); @@ -391,6 +392,7 @@ static int imx6ul_tsc_probe(struct platform_device *pde= v) int tsc_irq; int adc_irq; u32 average_samples; + u32 de_glitch; =20 tsc =3D devm_kzalloc(&pdev->dev, sizeof(*tsc), GFP_KERNEL); if (!tsc) @@ -513,6 +515,26 @@ static int imx6ul_tsc_probe(struct platform_device *pd= ev) return -EINVAL; } =20 + err =3D of_property_read_u32(np, "touchscreen-glitch-threshold-ns", + &de_glitch); + if (err) { + tsc->de_glitch =3D DE_GLITCH_DEF; + } else { + u64 cycles; + unsigned long rate =3D clk_get_rate(tsc->tsc_clk); + + cycles =3D DIV64_U64_ROUND_UP((u64)de_glitch * rate, NSEC_PER_SEC); + + if (cycles <=3D 0x3ff) + tsc->de_glitch =3D 3; + else if (cycles <=3D 0x7ff) + tsc->de_glitch =3D 2; + else if (cycles <=3D 0xfff) + tsc->de_glitch =3D 1; + else + tsc->de_glitch =3D 0; + } + err =3D input_register_device(tsc->input); if (err) { dev_err(&pdev->dev, --=20 2.43.0