From nobody Thu Oct 2 13:03:51 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75187283FF0; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054325; cv=none; b=I5mVz83LsIqYuWNJZHWBqTTV7pteTDtApgMYOf37GBFv8dTIDtNJH5OdK4RdkNbhHYgyfX4agoTLbmgthRim85er4J+VIlk3va+9+AkndDu3RdBxybrUlRLz+xeJeVPqj98B14ayCnEpxu5yHR81aY4eAczsFKWbuLqgrUZwXG4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054325; c=relaxed/simple; bh=g8WKS6OWWxn2i9b93Vms3rDWq8kUvZxINbkSWPCdUAg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rIjRHlE0r6PYByjv7vg94R82zc93fxi5GwVFzlNh50qTzxqpiwMnVbjtC8aDNPwAVSdAmgBd6PooYVxsPzrUGuwF7epjh5MzdtXryxw+/9Qo4iicgt+QKIhamIDyN4XN7Y6qtB8it/ZP+wP/pj++1Pkxyp/3RpUyVQknK7uKyjI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ngdC1s+8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ngdC1s+8" Received: by smtp.kernel.org (Postfix) with ESMTPS id 00F17C4CEF9; Tue, 16 Sep 2025 20:25:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758054325; bh=g8WKS6OWWxn2i9b93Vms3rDWq8kUvZxINbkSWPCdUAg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ngdC1s+8aKoELBX4ttC402zvWkjkBhpUXSFAfc8yZIPOIJQESQSAmr92qwfyf4ISL aV71PAQWX5zh/MDkk89hEAG6X1g5iO1KTkUznbCOZOFoQxfLcfOKLVFR93qLPdZoGU TfF+S8w5u/Ru+Hf758byUnWrjqdV1Gpk3rMef10MINTa/RUFAPPu4YFuBLM7wHjCN9 4WSRAOnBUBR06RovRp6a8scMic+jYtIVJ0vTRod+T3bx9Aj/8iAsISJa8sdMSZtrGb BsFvzyES5fd9H8Wv8hmQ31rxJSFA+Em+eeGxOhJzdEYDzVY5D8/Oljd2fOxCXO/06R gITtXiOdLeB9w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7723CAC59B; Tue, 16 Sep 2025 20:25:24 +0000 (UTC) From: Dang Huynh via B4 Relay Date: Wed, 17 Sep 2025 03:24:58 +0700 Subject: [PATCH 01/25] ARM: dts: unisoc: rda8810pl: Add label to GPIO nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-rda8810pl-drivers-v1-1-9ca9184ca977@mainlining.org> References: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> In-Reply-To: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> To: Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Alexandre Belloni , Michael Turquette , Stephen Boyd , Philipp Zabel , Sebastian Reichel , Vinod Koul , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, dmaengine@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mmc@vger.kernel.org, Dang Huynh X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758054322; l=1425; i=dang.huynh@mainlining.org; s=20250917; h=from:subject:message-id; bh=gehgcAARQ8SuL4G+2lQ4aVqQ18cLEbIKhDsg1ccbtlY=; b=vkVKhU4yFFQMGNx4j1vlk9SkqiDmkH60RhCQ7wo0S9uGQumeaKqLqNlS0OScNrteBhazOecZ8 T9KNvTq6xRZAUqrRvG/mu3SAX3P636QQs8gFg7biuveiCHR5chOs6NK X-Developer-Key: i=dang.huynh@mainlining.org; a=ed25519; pk=RyzH4CL4YU/ItXYUurA51EVBidfx4lIy8/E4EKRJCUk= X-Endpoint-Received: by B4 Relay for dang.huynh@mainlining.org/20250917 with auth_id=526 X-Original-From: Dang Huynh Reply-To: dang.huynh@mainlining.org From: Dang Huynh So we can add devices to these GPIO nodes for each board. Signed-off-by: Dang Huynh --- arch/arm/boot/dts/unisoc/rda8810pl.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/unisoc/rda8810pl.dtsi b/arch/arm/boot/dts/un= isoc/rda8810pl.dtsi index f30d6ece49fb33d9c5c3ad9522c83bb8e4f8b488..6553fc102c6751696e75e4de614= fc3428d182061 100644 --- a/arch/arm/boot/dts/unisoc/rda8810pl.dtsi +++ b/arch/arm/boot/dts/unisoc/rda8810pl.dtsi @@ -39,7 +39,7 @@ modem@10000000 { #size-cells =3D <1>; ranges =3D <0x0 0x10000000 0xfffffff>; =20 - gpioc@1a08000 { + gpioc: gpioc@1a08000 { compatible =3D "rda,8810pl-gpio"; reg =3D <0x1a08000 0x1000>; gpio-controller; @@ -76,7 +76,7 @@ timer@10000 { interrupt-names =3D "hwtimer", "ostimer"; }; =20 - gpioa@30000 { + gpioa: gpioa@30000 { compatible =3D "rda,8810pl-gpio"; reg =3D <0x30000 0x1000>; gpio-controller; @@ -87,7 +87,7 @@ gpioa@30000 { interrupts =3D <12 IRQ_TYPE_LEVEL_HIGH>; }; =20 - gpiob@31000 { + gpiob: gpiob@31000 { compatible =3D "rda,8810pl-gpio"; reg =3D <0x31000 0x1000>; gpio-controller; @@ -98,7 +98,7 @@ gpiob@31000 { interrupts =3D <13 IRQ_TYPE_LEVEL_HIGH>; }; =20 - gpiod@32000 { + gpiod: gpiod@32000 { compatible =3D "rda,8810pl-gpio"; reg =3D <0x32000 0x1000>; gpio-controller; --=20 2.51.0 From nobody Thu Oct 2 13:03:51 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B40B2E0927; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054325; cv=none; b=bHKc77ZXcM5daU90cE2kowdHCOk7xNHSpgmOJL9L1X82TnwIlJbe9Quk5a0WCK0bhIipiGI8j3Ib3dzvzu0LQukPGGqJrGtzGs/n8du4v94S38rG5pi2pGqCj7vcDDloWt4qN4FP83jyvZbgWdw+zu6x0n5aBQ46/PlXBRaJ9yw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054325; c=relaxed/simple; bh=X893mXdG5jDAoakU25w6AZ+PiFmR96PaE7s6Wnh4JEE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=elPDETkKqyHLOJX343IQkt2ZX/hEpCTDI8ol+IjV3ExbRqrKlaQMlAA5FpqBPY9+1hnilRrOrIqHQVCRlnFGJxua1Q0kaMgyx5KdkvEeD3kavaip0b0+7sd4G6MeH2w2WpNxQ6eKXsw2N3WN5+OPPeDZo7tq2ury/Q2c7h+Z2xk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XlVltMwP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XlVltMwP" Received: by smtp.kernel.org (Postfix) with ESMTPS id 125A4C4CEF0; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758054325; bh=X893mXdG5jDAoakU25w6AZ+PiFmR96PaE7s6Wnh4JEE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=XlVltMwPC7nNczwGoEIxDvOnbVd/T0P9HRB68TaGLfkQvRojcP444NbvGrx+Mmvc6 nut9J3OGDCfFVNbyFfSsZ5nbOlpjbdU8QlP4Tr1Uvljn6ija86f6oWLHr1lEGY9NJS 3gdGtPcKjCipIcxglJPeaLYXA36bDP8ICq1GQWxioMhUypE4ubq6DnlSzgSm5RpyJ7 YvbQkhArhH2IGsJ+jCGM4Bm34kk9lFkDWd+biHQQ8a9QeMp03jyGZn5WW+jg6ph2eM oO+WD4aev9S2dRQxXSWq95nkmkeoyeGlNtuwjRm3ztPBEKWRL/7cmlDvWBLM1QBLkl /FHvZPlMbaysQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 017D1CAC59D; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) From: Dang Huynh via B4 Relay Date: Wed, 17 Sep 2025 03:24:59 +0700 Subject: [PATCH 02/25] drivers: gpio: rda: Make IRQ optional Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-rda8810pl-drivers-v1-2-9ca9184ca977@mainlining.org> References: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> In-Reply-To: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> To: Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Alexandre Belloni , Michael Turquette , Stephen Boyd , Philipp Zabel , Sebastian Reichel , Vinod Koul , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, dmaengine@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mmc@vger.kernel.org, Dang Huynh X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758054322; l=961; i=dang.huynh@mainlining.org; s=20250917; h=from:subject:message-id; bh=Fax4H41w25n5u6GELyum7Uq2SVrab6rxKUOtQRQV09k=; b=8NPdXoYR6QMjpq7tWNquTNmGzt1Zr4mpACDx1zfor3wYw4pn/Zqu2jUfRZ99rq5r4TeUYxPub D4syMEvbMWWAYGlhGdETHjrWpszpet/JuedVRzqk5g7xv9O7nsvn0Hz X-Developer-Key: i=dang.huynh@mainlining.org; a=ed25519; pk=RyzH4CL4YU/ItXYUurA51EVBidfx4lIy8/E4EKRJCUk= X-Endpoint-Received: by B4 Relay for dang.huynh@mainlining.org/20250917 with auth_id=526 X-Original-From: Dang Huynh Reply-To: dang.huynh@mainlining.org From: Dang Huynh Not all GPIO have IRQ. When we use this driver with GPIOC (handled by modem) we get: rda-gpio 11a08000.gpioc: error -ENXIO: IRQ index 0 not found Let's mark IRQ as optional so this error doesn't show up. Signed-off-by: Dang Huynh --- drivers/gpio/gpio-rda.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-rda.c b/drivers/gpio/gpio-rda.c index bcd85a2237a532b875df9470d972ac88b95a91cc..b4db8553a2371ae407fdb7e681d= 0f82c4d9f74b7 100644 --- a/drivers/gpio/gpio-rda.c +++ b/drivers/gpio/gpio-rda.c @@ -229,7 +229,7 @@ static int rda_gpio_probe(struct platform_device *pdev) * RDA8810PL, GPIOC doesn't support interrupt. So we must handle * those also. */ - rda_gpio->irq =3D platform_get_irq(pdev, 0); + rda_gpio->irq =3D platform_get_irq_optional(pdev, 0); =20 rda_gpio->base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(rda_gpio->base)) --=20 2.51.0 From nobody Thu Oct 2 13:03:51 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B20052F2609; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054325; cv=none; b=ZuJVVdA02XnSRs/XcSxid9YyohkzIEPddS6P5lmflk/s82xEUGwdwF9SWiXvvsckD3WnbJVjbJWuzWXbbxCdMeF8Sa708HBo4pEKhnhVCSorLmN5f7Qv2zA9qjb+ya8rqB4/kk9Y9Q0tWGANoCFV0AmNNcG80Jxpy9xTHGDkASs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054325; c=relaxed/simple; bh=xub1/tI9O5DTgQhmhRBbs4Xjsw6qwKviTq2SxNAQ5VM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NsL0MCf22rMVTiPGo4ko8QBuAhKaUu+ZX8i1vtvfbe3Jy5rBp7rzs23aphXPYVL/ewmAgvohYcXlDdDpURGyHZ8ceLtI+EN6bpQvlhYtUby2J5a0Vk2ZP7/JTVQ+TxGId2WOJ//KbhLzT8nS4HoLi3fEs56EEWQNeM0iaKvBanU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=fcl4xDz1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fcl4xDz1" Received: by smtp.kernel.org (Postfix) with ESMTPS id 25CB5C4CEFF; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758054325; bh=xub1/tI9O5DTgQhmhRBbs4Xjsw6qwKviTq2SxNAQ5VM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=fcl4xDz1ZHp5+J8K8HjCWy3jmZaXLcIIwdfJFBIleSSBefPR3RHy+ZQxUO0sRA6fe fF4AW4NFW0VxJy6l1lYy0EM7Z/t5WqXyDlchlqYcVavBi0dvxncUhgtGTeMdFRVUyp KdUcPPHpjmmMz8UksyEbyFWty4ehkw05D1s22im+BUA191x0KwOXkd+S66zF5qPd27 eQVEw1E0m7NY2hU8517TDEpLUUWKLyJv7NivdyTFGD5gJ+kSXgdNEeaM/p/fSdQsKi RMrReUg5FWlBW/WdHLdXLoRPYWLogCrGj8QDpo0ohoa0OVFRyT28akLURoTMJJMdUk x0EZCWfQ0uLFg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10F37CAC592; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) From: Dang Huynh via B4 Relay Date: Wed, 17 Sep 2025 03:25:00 +0700 Subject: [PATCH 03/25] dt-bindings: gpio: rda: Make interrupts optional Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-rda8810pl-drivers-v1-3-9ca9184ca977@mainlining.org> References: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> In-Reply-To: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> To: Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Alexandre Belloni , Michael Turquette , Stephen Boyd , Philipp Zabel , Sebastian Reichel , Vinod Koul , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, dmaengine@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mmc@vger.kernel.org, Dang Huynh X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758054322; l=767; i=dang.huynh@mainlining.org; s=20250917; h=from:subject:message-id; bh=Ifgj24X3WuB4jA0+A119cFjcjAjN444atKSTzNtV5QI=; b=w5Dv0+XyivOW8fKisHFtboYipMhkeJG5JlSdgVYg9JCFW0dK+AUye0klaEHuhYZkbKF8yFV3d bbnf7sXd5NlDsF+1JmkU6i+0CfwfvX/taK6GSxR2IwyVaLwjD6ceHsT X-Developer-Key: i=dang.huynh@mainlining.org; a=ed25519; pk=RyzH4CL4YU/ItXYUurA51EVBidfx4lIy8/E4EKRJCUk= X-Endpoint-Received: by B4 Relay for dang.huynh@mainlining.org/20250917 with auth_id=526 X-Original-From: Dang Huynh Reply-To: dang.huynh@mainlining.org From: Dang Huynh The GPIO controller from the modem does not have an interrupt. Signed-off-by: Dang Huynh --- Documentation/devicetree/bindings/gpio/gpio-rda.yaml | 3 --- 1 file changed, 3 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/gpio-rda.yaml b/Documen= tation/devicetree/bindings/gpio/gpio-rda.yaml index 6ece555f074f84b396537917d7149d4061724dcc..dbb73b4d33ed39aa65024376b1a= f0c4e2fb896db 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-rda.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-rda.yaml @@ -41,9 +41,6 @@ required: - gpio-controller - "#gpio-cells" - ngpios - - interrupt-controller - - "#interrupt-cells" - - interrupts =20 additionalProperties: false =20 --=20 2.51.0 From nobody Thu Oct 2 13:03:51 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEF41305E26; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054325; cv=none; b=kTG14+IviuuETdivTQSatk5tJyQjA42zJACgZSPr8qxnbniWSPY8deta9OFtchjIEvOHIEQd1M3RTUWcvTg+4B/Wfl64SWkBkfGa4vg7XmupYNLTRpkpYIJ3mzX7ahuPjP4deLx5YV5xKKw7mzYDPc2nCed8aL8RMYqTCuL67Rw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054325; c=relaxed/simple; bh=PGC9RLyvUYb11AvcYKFthsR2RXxFjvbJW7ULzcMM1n4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pxxy1qXt3BWtQ/Xx6KR8hZo1En4AQoyoRA1aox8HrEusnN/f91f1XpSU07o7fM0yXtX49379XsZDaN9SO887JUC6ofqKf63mRtU5/uGrriHegwdgR7HQU8/40PpUbTPggkyR2nfCeCI9YAH4gIXjt4vDYwtjhvFOekhbEHNqibc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WF/U+ils; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WF/U+ils" Received: by smtp.kernel.org (Postfix) with ESMTPS id 31796C19422; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758054325; bh=PGC9RLyvUYb11AvcYKFthsR2RXxFjvbJW7ULzcMM1n4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=WF/U+ilsuMpWThSrx1H0QFkgdZaMVWBGJlBSSTATkfxZT6q0ZKb4HEFTUEJ8bf3nk /k4vNhDzDpvL5piUH2exVhGXwpg+s+v9RNTKpicxPJd0y9eU3E78Bg3z2zRLns9qc+ 9WSeaaXRF3arHwwhkyaEtB+r9wVDxgtL/iQYNJtCx2Ryhcy4NG3OKtbaFjbA/qW56I so2OsPiqAPCn8xTAVqSBmuYU8dBFkHegK9FLvgeyX3VFjxSB78VL4MI7oZHBpfiyKR 3kuLWgcwvQJyZbL0BTXDZSjIghucFTYPeSVBE+dIsOVQriJdJ7oqnKUmV9S4bY87Jf xREiIfqhBD1fQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 216E8CAC5A0; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) From: Dang Huynh via B4 Relay Date: Wed, 17 Sep 2025 03:25:01 +0700 Subject: [PATCH 04/25] rtc: Add timestamp for the end of 2127 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-rda8810pl-drivers-v1-4-9ca9184ca977@mainlining.org> References: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> In-Reply-To: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> To: Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Alexandre Belloni , Michael Turquette , Stephen Boyd , Philipp Zabel , Sebastian Reichel , Vinod Koul , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, dmaengine@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mmc@vger.kernel.org, Dang Huynh X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758054322; l=913; i=dang.huynh@mainlining.org; s=20250917; h=from:subject:message-id; bh=DzZHdJKZCRZsyIe84ay5pJ/2Z/eJ/DpBDRNQR5GG0kc=; b=TXUPCWPqfcmGpwTVgoZ/csRKglLlNBEzrYFxRh7ZQ//BPu6xMzaihEwxcAVhhtA00DbneF6R7 Kv5Wv87ejuhBJCzOJ67wnp3h9v8C3HAnCIfUnZpMcrApewJyPWho9WA X-Developer-Key: i=dang.huynh@mainlining.org; a=ed25519; pk=RyzH4CL4YU/ItXYUurA51EVBidfx4lIy8/E4EKRJCUk= X-Endpoint-Received: by B4 Relay for dang.huynh@mainlining.org/20250917 with auth_id=526 X-Original-From: Dang Huynh Reply-To: dang.huynh@mainlining.org From: Dang Huynh Some RTC (like MT2712 and RDA Micro) can handle until the end of the year 2127. Signed-off-by: Dang Huynh --- include/linux/rtc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/rtc.h b/include/linux/rtc.h index 95da051fb155dab4c8ec72ccae7b8e12a117a7f1..ec5828ccc7449388da2ab8bc757= 030e6795ace30 100644 --- a/include/linux/rtc.h +++ b/include/linux/rtc.h @@ -175,6 +175,7 @@ struct rtc_device { #define RTC_TIMESTAMP_END_2063 2966371199LL /* 2063-12-31 23:59:59 */ #define RTC_TIMESTAMP_END_2079 3471292799LL /* 2079-12-31 23:59:59 */ #define RTC_TIMESTAMP_END_2099 4102444799LL /* 2099-12-31 23:59:59 */ +#define RTC_TIMESTAMP_END_2127 4985971199LL /* 2127-12-31 23:59:59 */ #define RTC_TIMESTAMP_END_2199 7258118399LL /* 2199-12-31 23:59:59 */ #define RTC_TIMESTAMP_END_9999 253402300799LL /* 9999-12-31 23:59:59 */ =20 --=20 2.51.0 From nobody Thu Oct 2 13:03:51 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB683304BD0; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054325; cv=none; b=lhSHZdf9j4BhR5arTuYBKpIFnGVpeIvCuPKGKOnH1VXzyceFpEynB/iZ6EtA5JD3QZEiqj0bS5b0R/dwsLULNzWFCs1euWWge5+c+4V2Fo5a48seyxbcpB56+zPoBh1uc3C9VTkiWGQOQQ/z33N8cYczbZOpEifVLDri38lll+M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054325; c=relaxed/simple; bh=p/pUs0MZFo/+qdpENMcLyBKM/numNqXrgeAhrFls3Eo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BxQITD8cIPZAR11hGkfJRekGjJPtVknKw4ubexL2BMQNIzh4QTKcVk3kv1PTGVzYKICP4H13RKgPq9VE43kIp+lKCwgQiBRljgztiaihj51XvnZkQsIj7WlyYCbCYJvsADOyImhtaDOXJKyNtsVFdNPnyNulaJTUj6nP/Lj7/04= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=X40rBasv; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="X40rBasv" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3B570C2BC9E; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758054325; bh=p/pUs0MZFo/+qdpENMcLyBKM/numNqXrgeAhrFls3Eo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=X40rBasvR7PF9fN2qZQCQCcMCvK+/79psNEO7of+ZdYpkF69MAr0mnbIigzoHre2b jx9HjMjRyRSaCrimkK/eqqMxWdoW8v3CHPEww8hrQLkp3csUFfFeLLyCdqCcSvu6zI HWOA3QD+Ku2kR8Dj7zScHUzKEsTBPK+YbDobYP8GQmOebRUlZlvYmXKEXp/q0TX3Tl /QvOaZLAcZoPr92AEA3siTedj5AV3iHptxfTowEYaB1heIfj7/B49bp/Nkns7ifsEF x8qKh8xWD46Mbc8VfSb1g+8SGej7y5tanDSXVqUIxhCpLNSAFSz34bFs1DQJYUV3a/ qEDMtb68I2Azw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30ECFCAC598; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) From: Dang Huynh via B4 Relay Date: Wed, 17 Sep 2025 03:25:02 +0700 Subject: [PATCH 05/25] dt-bindings: rtc: Add RDA Micro RDA8810PL RTC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-rda8810pl-drivers-v1-5-9ca9184ca977@mainlining.org> References: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> In-Reply-To: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> To: Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Alexandre Belloni , Michael Turquette , Stephen Boyd , Philipp Zabel , Sebastian Reichel , Vinod Koul , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, dmaengine@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mmc@vger.kernel.org, Dang Huynh X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758054322; l=1198; i=dang.huynh@mainlining.org; s=20250917; h=from:subject:message-id; bh=WXHBrmFovBDD+aODYzMgHF0ddvJv66eaBAA1wb46O10=; b=1AWpjOVHeC7A/fG05V5076Du73/ixlPO3tOlVdOzwByzDZgvNmGQVQIvJBjfRQdO6qHjcr8dk nUyBOunSsouDcKxdzeqOCwhm+B7f/3Zy6jwd0Awas0NtAUvq1ASF3OD X-Developer-Key: i=dang.huynh@mainlining.org; a=ed25519; pk=RyzH4CL4YU/ItXYUurA51EVBidfx4lIy8/E4EKRJCUk= X-Endpoint-Received: by B4 Relay for dang.huynh@mainlining.org/20250917 with auth_id=526 X-Original-From: Dang Huynh Reply-To: dang.huynh@mainlining.org From: Dang Huynh Add documentation describing the RTC found in RDA8810PL SoC. Signed-off-by: Dang Huynh --- .../devicetree/bindings/rtc/rda,8810pl-rtc.yaml | 30 ++++++++++++++++++= ++++ 1 file changed, 30 insertions(+) diff --git a/Documentation/devicetree/bindings/rtc/rda,8810pl-rtc.yaml b/Do= cumentation/devicetree/bindings/rtc/rda,8810pl-rtc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..3ceae294921cc3211cd775d9b38= 90393196faf82 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/rda,8810pl-rtc.yaml @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/rda,8810pl-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RDA Micro RDA8810PL Real Time Clock + +maintainers: + - Dang Huynh + +properties: + compatible: + const: rda,8810pl-rtc + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + rtc@1a06000 { + compatible =3D "rda,8810pl-rtc"; + reg =3D <0x1a06000 0x1000>; + }; --=20 2.51.0 From nobody Thu Oct 2 13:03:51 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E0C3B313D7A; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054326; cv=none; b=RXvA6vqsDUfFjswO5bjHKgKXOWpVSzN6tBX6qgQJRTfo/d8XOz6nUm/gU3M+YvtpSGKVEn1G/39zjamrLAh/AeVHAGe03Tet5XgebtZDyHYZ8lwegFROJczSs9eZbazdDirkbN12zkiU6EBHsBYzU9SrKJhbOALd4ujDQ9s9MnA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054326; c=relaxed/simple; bh=6a7uRpDFFwmJD90P9fw5aBw9D1Bqy2wqv4v3bXssn10=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kX8gxeEH/T/Y8rqkq4/qCuC+VKE9hJdxGzGaeAT5CSnSVPtEaYZLy9+MmYwTc2BzD8bGqonrBlG32FZX2wiNZOSp3XBi6nMdL+FdNftZExcwO9BZdHKrXPxioP5C78oA1Yyqb4eDEjGMrH4SdNUoxXm4AJeXjMLpxzWec6Oj4Bg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nbqz4/4M; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nbqz4/4M" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4CB05C116B1; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758054325; bh=6a7uRpDFFwmJD90P9fw5aBw9D1Bqy2wqv4v3bXssn10=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=nbqz4/4Ms1V2NDIjE037IPoihF7TCtIfauQ00yIKCPcNACiZj1p6MjSeyTuT7et+C HSpG9aPw2oPL5OlRPiQPdxlCrelFCwZ8U5lfiLf8evTMNqe6oaFl9bJD3+/ZJ3rSi0 MriJ2iJqJBZHmS+UFuME7QhY6k0Y9l3d4S0kDey0yhdJLxmnItCz2suMhmTYoXphLj 1FPLlTURZ9QVfMpAWxlboym9P9yKkxc6xyODFY8HSC9AhWrbHUnyeWvoAlZ6STnwjM vsQvTh4PX2qIqsf0fOGDazevcjcYeimA74M2fYaSGbFTwWE4G8oBjBgGI9DqjQD/Ai QnXzBuQt/MWPw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41236CAC59F; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) From: Dang Huynh via B4 Relay Date: Wed, 17 Sep 2025 03:25:03 +0700 Subject: [PATCH 06/25] rtc: Add driver for RDA Micro SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-rda8810pl-drivers-v1-6-9ca9184ca977@mainlining.org> References: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> In-Reply-To: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> To: Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Alexandre Belloni , Michael Turquette , Stephen Boyd , Philipp Zabel , Sebastian Reichel , Vinod Koul , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, dmaengine@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mmc@vger.kernel.org, Dang Huynh X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758054322; l=12867; i=dang.huynh@mainlining.org; s=20250917; h=from:subject:message-id; bh=cSJlbB/SvEEJA+EINZDwWhdF79lGvQa4JzoffiXw/8A=; b=Kerwaw//6fBvHo9376TQSXrx+rBI8DCHbXxwdiEX7xIvpmGu5dhndFwWTM6Vg5geOi9Y7Neu5 CSES8aJIaDmCPO9wetq+ZJzdPpI13ZweHRK6Z2NhRw7BxkASASNYofo X-Developer-Key: i=dang.huynh@mainlining.org; a=ed25519; pk=RyzH4CL4YU/ItXYUurA51EVBidfx4lIy8/E4EKRJCUk= X-Endpoint-Received: by B4 Relay for dang.huynh@mainlining.org/20250917 with auth_id=526 X-Original-From: Dang Huynh Reply-To: dang.huynh@mainlining.org From: Dang Huynh The RDA Micro SoC has built-in RTC, it supports read/write date as well as alarm. Signed-off-by: Dang Huynh --- MAINTAINERS | 6 + drivers/rtc/Kconfig | 11 ++ drivers/rtc/Makefile | 1 + drivers/rtc/rtc-rda.c | 356 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 374 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index fa7f80bd7b2f8bd2099acb9f38070498e7b1cc7e..0549b1d0657f2caaf86a723db13= 9cf9d84d59c4a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21393,6 +21393,12 @@ S: Supported T: git git://git.kernel.org/pub/scm/linux/kernel/git/rcu/linux.git rcu/dev F: tools/testing/selftests/rcutorture =20 +RDA MICRO REAL TIME CLOCK DRIVER +M: Dang Huynh +S: Maintained +F: Documentation/devicetree/bindings/rtc/rda,8810pl-rtc.yaml +F: drivers/rtc/rtc-rda.c + RDACM20 Camera Sensor M: Jacopo Mondi M: Kieran Bingham diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 64f6e9756aff4a1f6f6c50f9b4fc2140f66a8578..287fc3bbd474ab78a9bd3b8813e= 8b9d475c07198 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -1471,6 +1471,17 @@ config RTC_DRV_OMAP This driver can also be built as a module, if so, module will be called rtc-omap. =20 +config RTC_DRV_RDA + tristate "RDA Micro RTC" + depends on ARCH_RDA || COMPILE_TEST + select REGMAP_MMIO + help + If you say yes here you get support for the built-in RTC on + RDA Micro SoC. + + This driver can also be built as a module, if so, the module + will be called rtc-rda. + config RTC_DRV_S3C tristate "Samsung S3C series SoC RTC" depends on ARCH_EXYNOS || ARCH_S3C64XX || ARCH_S5PV210 || \ diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 789bddfea99d8fcd024566891c37ee73e527cf93..02f73062bb158fe4738a3043c58= ee40f8a58b3c6 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -141,6 +141,7 @@ obj-$(CONFIG_RTC_DRV_PS3) +=3D rtc-ps3.o obj-$(CONFIG_RTC_DRV_PXA) +=3D rtc-pxa.o obj-$(CONFIG_RTC_DRV_R7301) +=3D rtc-r7301.o obj-$(CONFIG_RTC_DRV_R9701) +=3D rtc-r9701.o +obj-$(CONFIG_RTC_DRV_RDA) +=3D rtc-rda.o obj-$(CONFIG_RTC_DRV_RC5T583) +=3D rtc-rc5t583.o obj-$(CONFIG_RTC_DRV_RC5T619) +=3D rtc-rc5t619.o obj-$(CONFIG_RTC_DRV_RK808) +=3D rtc-rk808.o diff --git a/drivers/rtc/rtc-rda.c b/drivers/rtc/rtc-rda.c new file mode 100644 index 0000000000000000000000000000000000000000..bb5aa25fb7d0ad538a0f7f67a80= d08fe67af1c5d --- /dev/null +++ b/drivers/rtc/rtc-rda.c @@ -0,0 +1,356 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * RTC driver for RDA Micro + * + * Copyright (C) 2013-2014 RDA Microelectronics Inc. + * Copyright (C) 2024 Dang Huynh + */ + +#include +#include +#include +#include +#include +#include + +struct rda_rtc { + struct rtc_device *rtc_dev; + struct regmap *regmap; +}; + +/* RTC Registers */ +#define RDA_RTC_CTRL_REG 0x0 +#define RDA_RTC_CMD_REG 0x4 +#define RDA_RTC_STA_REG 0x8 +#define RDA_RTC_CAL_LOAD_LOW_REG 0xC +#define RDA_RTC_CAL_LOAD_HIGH_REG 0x10 +#define RDA_RTC_CUR_LOAD_LOW_REG 0x14 +#define RDA_RTC_CUR_LOAD_HIGH_REG 0x18 +#define RDA_RTC_ALARM_LOW_REG 0x1C +#define RDA_RTC_ALARM_HIGH_REG 0x20 + +/* RTC Bits */ +#define RDA_RTC_CMD_CAL_LOAD BIT(0) +#define RDA_RTC_CMD_ALARM_LOAD BIT(4) +#define RDA_RTC_CMD_ALARM_ENABLE BIT(5) +#define RDA_RTC_CMD_ALARM_DISABLE BIT(6) +#define RDA_RTC_CMD_INVALID BIT(31) +#define RDA_RTC_STA_ALARM_ENABLE BIT(20) +#define RDA_RTC_STA_NOT_PROG BIT(31) + +/* RTC Masks */ +#define RDA_SEC_MASK GENMASK(7, 0) +#define RDA_MIN_MASK GENMASK(15, 8) +#define RDA_HRS_MASK GENMASK(23, 16) + +#define RDA_MDAY_MASK GENMASK(7, 0) +#define RDA_MON_MASK GENMASK(11, 8) +#define RDA_YEAR_MASK GENMASK(22, 16) +#define RDA_WDAY_MASK GENMASK(26, 24) + +static int rda_rtc_settime(struct device *dev, struct rtc_time *tm) +{ + struct rda_rtc *rtc =3D dev_get_drvdata(dev); + u32 high, low; + int ret; + + ret =3D rtc_valid_tm(tm); + if (ret < 0) + return ret; + + /* + * The number of years since 1900 in kernel, + * but it is defined since 2000 by HW. + * The number of mons' range is from 0 to 11 in kernel, + * but it is defined from 1 to 12 by HW. + */ + low =3D FIELD_PREP(RDA_SEC_MASK, tm->tm_sec) | + FIELD_PREP(RDA_MIN_MASK, tm->tm_min) | + FIELD_PREP(RDA_HRS_MASK, tm->tm_hour); + + high =3D FIELD_PREP(RDA_MDAY_MASK, tm->tm_mday) | + FIELD_PREP(RDA_MON_MASK, tm->tm_mon + 1) | + FIELD_PREP(RDA_YEAR_MASK, tm->tm_year - 100) | + FIELD_PREP(RDA_WDAY_MASK, tm->tm_wday); + + ret =3D regmap_write(rtc->regmap, RDA_RTC_CAL_LOAD_LOW_REG, low); + if (ret < 0) { + dev_err(dev, "Failed to update RTC low register: %d\n", ret); + return ret; + } + + ret =3D regmap_write(rtc->regmap, RDA_RTC_CAL_LOAD_HIGH_REG, high); + if (ret < 0) { + dev_err(dev, "Failed to update RTC low register: %d\n", ret); + return ret; + } + + ret =3D regmap_update_bits(rtc->regmap, RDA_RTC_CMD_REG, RDA_RTC_CMD_CAL_= LOAD, 1); + if (ret < 0) { + dev_err(dev, "Failed to update RTC cal load register: %d\n", ret); + return ret; + } + + return 0; +} + +static int rda_rtc_readtime(struct device *dev, struct rtc_time *tm) +{ + struct rda_rtc *rtc =3D dev_get_drvdata(dev); + unsigned int high, low; + int ret; + + /* + * Check if RTC data is valid. + * + * When this bit is set, it means the data in the RTC is invalid + * or not configured. + */ + ret =3D regmap_test_bits(rtc->regmap, RDA_RTC_STA_REG, RDA_RTC_STA_NOT_PR= OG); + if (ret < 0) { + dev_err(dev, "Failed to read RTC status: %d\n", ret); + return ret; + } else if (ret > 0) + return -EINVAL; + + ret =3D regmap_read(rtc->regmap, RDA_RTC_CUR_LOAD_HIGH_REG, &high); + if (ret) { + dev_err(dev, "Failed to read RTC high reg: %d\n", ret); + return ret; + } + + ret =3D regmap_read(rtc->regmap, RDA_RTC_CUR_LOAD_LOW_REG, &low); + if (ret) { + dev_err(dev, "Failed to read RTC low reg: %d\n", ret); + return ret; + } + + tm->tm_sec =3D FIELD_GET(RDA_SEC_MASK, low); + tm->tm_min =3D FIELD_GET(RDA_MIN_MASK, low); + tm->tm_hour =3D FIELD_GET(RDA_HRS_MASK, low); + tm->tm_mday =3D FIELD_GET(RDA_MDAY_MASK, high); + tm->tm_mon =3D FIELD_GET(RDA_MON_MASK, high); + tm->tm_year =3D FIELD_GET(RDA_YEAR_MASK, high); + tm->tm_wday =3D FIELD_GET(RDA_WDAY_MASK, high); + + /* + * The number of years since 1900 in kernel, + * but it is defined since 2000 by HW. + */ + tm->tm_year +=3D 100; + /* + * The number of mons' range is from 0 to 11 in kernel, + * but it is defined from 1 to 12 by HW. + */ + tm->tm_mon -=3D 1; + + return 0; +} + +static int rda_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct rda_rtc *rtc =3D dev_get_drvdata(dev); + struct rtc_time *tm =3D &alrm->time; + unsigned int high, low; + int ret; + + ret =3D regmap_read(rtc->regmap, RDA_RTC_ALARM_HIGH_REG, &high); + if (ret) { + dev_err(dev, "Failed to read alarm low reg: %d\n", ret); + return ret; + } + + ret =3D regmap_read(rtc->regmap, RDA_RTC_ALARM_LOW_REG, &low); + if (ret) { + dev_err(dev, "Failed to read alarm low reg: %d\n", ret); + return ret; + } + + tm->tm_sec =3D FIELD_GET(RDA_SEC_MASK, low); + tm->tm_min =3D FIELD_GET(RDA_MIN_MASK, low); + tm->tm_hour =3D FIELD_GET(RDA_HRS_MASK, low); + tm->tm_mday =3D FIELD_GET(RDA_MDAY_MASK, high); + tm->tm_mon =3D FIELD_GET(RDA_MON_MASK, high); + tm->tm_year =3D FIELD_GET(RDA_YEAR_MASK, high); + tm->tm_wday =3D FIELD_GET(RDA_WDAY_MASK, high); + + /* + * The number of years since 1900 in kernel, + * but it is defined since 2000 by HW. + */ + tm->tm_year +=3D 100; + /* + * The number of mons' range is from 0 to 11 in kernel, + * but it is defined from 1 to 12 by HW. + */ + tm->tm_mon -=3D 1; + + return 0; +} + +static int rda_rtc_alarm_irq_enable(struct device *dev, unsigned int enabl= ed) +{ + struct rda_rtc *rtc =3D dev_get_drvdata(dev); + + if (enabled) + return regmap_update_bits(rtc->regmap, RDA_RTC_CMD_REG, + RDA_RTC_CMD_ALARM_ENABLE, 1); + + return regmap_update_bits(rtc->regmap, RDA_RTC_CMD_REG, + RDA_RTC_CMD_ALARM_DISABLE, 1); +} + +static int rda_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct rda_rtc *rtc =3D dev_get_drvdata(dev); + struct rtc_time *tm =3D &alrm->time; + u32 high, low; + int ret; + + ret =3D rtc_valid_tm(tm); + if (ret < 0) + return ret; + + /* TODO: Check if it's necessary to disable IRQ first */ + rda_rtc_alarm_irq_enable(dev, 0); + + /* + * The number of years since 1900 in kernel, + * but it is defined since 2000 by HW. + * The number of mons' range is from 0 to 11 in kernel, + * but it is defined from 1 to 12 by HW. + */ + low =3D FIELD_PREP(RDA_SEC_MASK, tm->tm_sec) | + FIELD_PREP(RDA_MIN_MASK, tm->tm_min) | + FIELD_PREP(RDA_HRS_MASK, tm->tm_hour); + + high =3D FIELD_PREP(RDA_MDAY_MASK, tm->tm_mday) | + FIELD_PREP(RDA_MON_MASK, tm->tm_mon + 1) | + FIELD_PREP(RDA_YEAR_MASK, tm->tm_year - 100) | + FIELD_PREP(RDA_WDAY_MASK, tm->tm_wday); + + + ret =3D regmap_write(rtc->regmap, RDA_RTC_ALARM_LOW_REG, low); + if (ret < 0) { + dev_err(dev, "Failed to set low alarm register: %d\n", ret); + return ret; + } + + ret =3D regmap_write(rtc->regmap, RDA_RTC_ALARM_HIGH_REG, high); + if (ret < 0) { + dev_err(dev, "Failed to set low alarm register: %d\n", ret); + return ret; + } + + ret =3D regmap_update_bits(rtc->regmap, RDA_RTC_CMD_REG, RDA_RTC_CMD_ALAR= M_LOAD, 1); + if (ret < 0) { + dev_err(dev, "Failed to set alarm register: %d\n", ret); + return ret; + } + + dev_dbg(dev, "Alarm set: %4d-%02d-%02d %02d:%02d:%02d\n", + 2000 + (tm->tm_year - 100), tm->tm_mon + 1, tm->tm_mday, + tm->tm_hour, tm->tm_min, tm->tm_sec); + + return 0; +} + +static int rda_rtc_proc(struct device *dev, struct seq_file *seq) +{ + struct rda_rtc *rtc =3D dev_get_drvdata(dev); + int ret; + + ret =3D regmap_test_bits(rtc->regmap, RDA_RTC_STA_REG, RDA_RTC_STA_ALARM_= ENABLE); + if (ret < 0) { + dev_err(dev, "Failed to read alarm status: %d\n", ret); + return ret; + } + + seq_printf(seq, "alarm enable\t: %s\n", (ret > 0) ? "yes" : "no"); + + return 0; +} + +static const struct rtc_class_ops rda_rtc_ops =3D { + .read_time =3D rda_rtc_readtime, + .set_time =3D rda_rtc_settime, + .read_alarm =3D rda_rtc_readalarm, + .set_alarm =3D rda_rtc_setalarm, + .proc =3D rda_rtc_proc, + .alarm_irq_enable =3D rda_rtc_alarm_irq_enable, +}; + +#ifdef CONFIG_PM_SLEEP +static int rda_rtc_suspend(struct platform_device *pdev, pm_message_t stat= e) +{ + /* TODO: Check if it's okay to turn on alarm IRQ when it's not set */ + return rda_rtc_alarm_irq_enable(&pdev->dev, 1); +} + +static int rda_rtc_resume(struct platform_device *pdev) +{ + /* If alarms were left, we turn them off. */ + return rda_rtc_alarm_irq_enable(&pdev->dev, 0); +} +#endif + +static SIMPLE_DEV_PM_OPS(rda_rtc_pm_ops, rda_rtc_suspend, rda_rtc_resume); + +static const struct regmap_config regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, +}; + +static int rda_rtc_probe(struct platform_device *pdev) +{ + struct rda_rtc *rda_rtc; + void __iomem *base; + + rda_rtc =3D devm_kzalloc(&pdev->dev, sizeof(*rda_rtc), GFP_KERNEL); + if (!rda_rtc) + return -ENOMEM; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return dev_err_probe(&pdev->dev, PTR_ERR(base), + "failed to remap resource\n"); + + rda_rtc->regmap =3D devm_regmap_init_mmio(&pdev->dev, base, ®map_confi= g); + if (!rda_rtc->regmap) + return dev_err_probe(&pdev->dev, PTR_ERR(rda_rtc->regmap), + "can't find regmap\n"); + + rda_rtc->rtc_dev =3D devm_rtc_allocate_device(&pdev->dev); + if (IS_ERR(rda_rtc->rtc_dev)) + return dev_err_probe(&pdev->dev, PTR_ERR(rda_rtc->rtc_dev), + "failed to allocate rtc device\n"); + + rda_rtc->rtc_dev->ops =3D &rda_rtc_ops; + rda_rtc->rtc_dev->range_min =3D RTC_TIMESTAMP_BEGIN_2000; + rda_rtc->rtc_dev->range_max =3D RTC_TIMESTAMP_END_2127; + + platform_set_drvdata(pdev, rda_rtc); + + return devm_rtc_register_device(rda_rtc->rtc_dev); +} + +static const struct of_device_id rda_rtc_id_table[] =3D { + { .compatible =3D "rda,8810pl-rtc", }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, rda_rtc_id_table); + +static struct platform_driver rda_rtc_driver =3D { + .probe =3D rda_rtc_probe, + .driver =3D { + .name =3D "rtc-rda", + .pm =3D &rda_rtc_pm_ops, + .of_match_table =3D rda_rtc_id_table, + }, +}; +module_platform_driver(rda_rtc_driver); + +MODULE_AUTHOR("Dang Huynh "); +MODULE_DESCRIPTION("RDA Micro RTC driver"); +MODULE_LICENSE("GPL"); --=20 2.51.0 From nobody Thu Oct 2 13:03:51 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF128313D79; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054326; cv=none; b=ojkd/hBMrha9MTPh/kPTdfc47VbM3/nVyg3Ed5XhyQZzPbcAL7U0k9W66C62KsKVh3gi3iIYFhFkJeBaCkY3BF3QlfDv58kTrdK84WvtojlFW/qYzszZkDZkUgEXahe/ezXIvbpJB8zXVUUvEqhsBw/lY4B6aJOzjOYyWxzykK8= ARC-Message-Signature: i=1; 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b=scV+PQn964rxS3ZPctvG+R7FhPeCSWfGf9komgdbw6iiuybNidlGvoDSt/xlkW0oc 4035P0m2F65qcztXQziIXfYUzzeAMXmfe0IKlGgpFzisjSvzHB0O5Pu0EvxA5gYG5Q ycgEz0pF8VrUUAk/RSq6cpMrhuIyNGdfbQfwA2m60j6uvYCEYR7XKD8M0RQPLkar4y ELufdydE/YKRaPQA78fbloBw9QejQGg5PQswdCf7rq7ahsdQVF02gE+j6wZ3VXfcGp U9uWeolxbW+kUf/0aHZ3ZY2TSKtcWCBElAhxP3BSDy2dA/A+5gRkVTAsOr5Qy+0Aps ieXYUVKmmH+MA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50625CAC59D; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) From: Dang Huynh via B4 Relay Date: Wed, 17 Sep 2025 03:25:04 +0700 Subject: [PATCH 07/25] ARM: dts: unisoc: rda8810pl: Enable Real-Time Clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-rda8810pl-drivers-v1-7-9ca9184ca977@mainlining.org> References: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> In-Reply-To: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> To: Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Alexandre Belloni , Michael Turquette , Stephen Boyd , Philipp Zabel , Sebastian Reichel , Vinod Koul , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, dmaengine@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mmc@vger.kernel.org, Dang Huynh X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758054322; l=779; i=dang.huynh@mainlining.org; s=20250917; h=from:subject:message-id; bh=CMytnUCPsfWK+Zir9iDw5CkhUnTaS4MnLkyTK6BwbAk=; b=8EhQxw0LLMM2LDVQTNZ8vl25jTC3/GCxaDYQ7uSwHCHHdz62F1wVQJjmy1WNmtyxi2SS9g+G1 ldz7HeyKeUcBO6vdkIEyJR4XdsV1mIPJnTtzHx2ZgUV1OLieWUsiZ6x X-Developer-Key: i=dang.huynh@mainlining.org; a=ed25519; pk=RyzH4CL4YU/ItXYUurA51EVBidfx4lIy8/E4EKRJCUk= X-Endpoint-Received: by B4 Relay for dang.huynh@mainlining.org/20250917 with auth_id=526 X-Original-From: Dang Huynh Reply-To: dang.huynh@mainlining.org From: Dang Huynh The RDA8810PL has built-in RTC. Signed-off-by: Dang Huynh --- arch/arm/boot/dts/unisoc/rda8810pl.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/unisoc/rda8810pl.dtsi b/arch/arm/boot/dts/un= isoc/rda8810pl.dtsi index 6553fc102c6751696e75e4de614fc3428d182061..609359aa91537168435934077e7= 36b216adf50f4 100644 --- a/arch/arm/boot/dts/unisoc/rda8810pl.dtsi +++ b/arch/arm/boot/dts/unisoc/rda8810pl.dtsi @@ -39,6 +39,11 @@ modem@10000000 { #size-cells =3D <1>; ranges =3D <0x0 0x10000000 0xfffffff>; =20 + rtc@1a06000 { + compatible =3D "rda,8810pl-rtc"; + reg =3D <0x1a06000 0x1000>; + }; + gpioc: gpioc@1a08000 { compatible =3D "rda,8810pl-gpio"; reg =3D <0x1a08000 0x1000>; --=20 2.51.0 From nobody Thu Oct 2 13:03:51 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEA58313D52; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054326; cv=none; b=oJmIriuYk/MXi9u+JNUPXybntboZKPaCe2WLEnGlC2OmZrdLu8zrSUYYxpHslT+iuF+kpyo6CaCof93thjT42yL0lLpPeT/sJMG8FXMX4aNRWsx0bJnm7Oo+kUkjdts7i+00m/Ih99/jpoRaJ/dDwUzhaHzhQtrbBNcuNfVieNw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054326; c=relaxed/simple; bh=e/qC+sVxQ9TrDHhG0wtazM84HxOMKYeszZU0EuODGJs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HJ2wBpUBrX+60J3INKJoeoLGWpmHyfu5YrTYu9G8HPsryBk+nDEELopTBJiCdJe/BlEiGE/Nhj+vMDsb8wBiSBuo7GKqlQDLA8btWaA73UqaBvMgZJ0aGykr0eq+YeGpoTE81n8uwJLZb7A+Vo1p2kzbRlhPVbzJhCL0nqx6KwE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JQK0nw9S; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JQK0nw9S" Received: by smtp.kernel.org (Postfix) with ESMTPS id 67AB2C116C6; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758054325; bh=e/qC+sVxQ9TrDHhG0wtazM84HxOMKYeszZU0EuODGJs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=JQK0nw9SBa2eVYYGvCy8nmx53sGgdLx/FyORN5DzspfPQt24tLYQaFsC0MlDud1S2 gIqO9nWVRE7MYLVeiI6LJTf5FbkB0ApYljJ1zvIGfwRTLJPEaxiPzTgsEHcEA5+i5C hOnnQENAY9wP8qMtTl9iyauSoX280tEPoDukO3TsmW+mw58CCW5/2kHl+QZ47IPoFf 18lavy+cYon26CUGzTIpIOuny0U7Q9DCsvLl9N2C8Q5vTLX2Tpkdw2BdV7R7ugEyjC OPScv0AHz21XahXWoff39Uiin5vexBF9oDsNfFcuf7h8e5nCrLxpkS/oQd3oUqmh4A Wz1x4ynN10zRw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F238CAC592; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) From: Dang Huynh via B4 Relay Date: Wed, 17 Sep 2025 03:25:05 +0700 Subject: [PATCH 08/25] ARM: dts: unisoc: rda8810pl: Enable ARM PMU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-rda8810pl-drivers-v1-8-9ca9184ca977@mainlining.org> References: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> In-Reply-To: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> To: Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Alexandre Belloni , Michael Turquette , Stephen Boyd , Philipp Zabel , Sebastian Reichel , Vinod Koul , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, dmaengine@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mmc@vger.kernel.org, Dang Huynh X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758054322; l=907; i=dang.huynh@mainlining.org; s=20250917; h=from:subject:message-id; bh=YAW/bGAZr0vX0B6I3xTMN5lJP76jY17Qpzu5kruaYow=; b=Xx4eEf+AW3RfI/PbEY5JiaKmRAPppuTYEIz3HyHrxewzcQWqWGWhkO1ddTilsHUwqfkZstlrk 2wL45PEan/qADgsP0ddnn6WAkTtuRkV+QW9c5fDgsFPwxfxBZIgttWj X-Developer-Key: i=dang.huynh@mainlining.org; a=ed25519; pk=RyzH4CL4YU/ItXYUurA51EVBidfx4lIy8/E4EKRJCUk= X-Endpoint-Received: by B4 Relay for dang.huynh@mainlining.org/20250917 with auth_id=526 X-Original-From: Dang Huynh Reply-To: dang.huynh@mainlining.org From: Dang Huynh The SoC uses a standard ARM PMU, enable it. Signed-off-by: Dang Huynh --- arch/arm/boot/dts/unisoc/rda8810pl.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/unisoc/rda8810pl.dtsi b/arch/arm/boot/dts/un= isoc/rda8810pl.dtsi index 609359aa91537168435934077e736b216adf50f4..45a2fd3e04cea5aac4fb6b40a6b= 332ce3eee4f2c 100644 --- a/arch/arm/boot/dts/unisoc/rda8810pl.dtsi +++ b/arch/arm/boot/dts/unisoc/rda8810pl.dtsi @@ -6,6 +6,7 @@ * Copyright (c) 2018 Manivannan Sadhasivam */ =20 +#include #include =20 / { @@ -25,6 +26,11 @@ cpu@0 { }; }; =20 + pmu { + compatible =3D "arm,cortex-a5-pmu"; + interrupts =3D <21 IRQ_TYPE_LEVEL_HIGH>; + }; + sram@100000 { compatible =3D "mmio-sram"; reg =3D <0x100000 0x10000>; --=20 2.51.0 From nobody Thu Oct 2 13:03:51 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E19E731B820; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054326; cv=none; b=bAFzep2i4tX+7kUTakDwKQh7blccoqZ6ETIjWxXfzySyG/8IQH6EcWwN2fUwkIY8Gsa0O38AR54PY/C+svKslrH5xhKH2FbkRNuLfZEwgx2SItqdlubogOL5houV+9aO4TGej/LIAvSWwrb/1/5sBx18fBQPMy3wiAxhVMuy3SU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054326; c=relaxed/simple; bh=s5jfml22S4HZXK96jIcDhIwNffw2qcJ0QY0RssdtAYg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PoM3RIMhF5Ex/WwsL8HFUqt1KdtXn4M6pSnmI2b8zPenYo5bZImfnKwlUDsbyUqf6So4tH03DYptE1BYTggKfQ0pb5Hg6hIKq+CM0ob4bCq3nucXoiCM3PVMNOqZgwkU017fbJAfGdFt1xMolLDWl6wttFs+kbBPQAVkuiLGplg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Birj6Lfi; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Birj6Lfi" Received: by smtp.kernel.org (Postfix) with ESMTPS id 78A3DC2BCC4; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758054325; bh=s5jfml22S4HZXK96jIcDhIwNffw2qcJ0QY0RssdtAYg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Birj6LfivaNjxqb8uCvp/d+CR1xUfaMr/nE+QUIambTVTGHnn8cCDzqmT4pGj1Pfu WKL6K68MdfVk1K/Wma+iBl8XbHykjT4D6/Rotfj0uLFRn2yLMFYaXlRzHA123sYELY vpOMj6KWEEedSp3OSnrm2/zhHGscp2bEI84xoV4NykeqhcWb8l8OcI7UF8P7Ub60DQ 2PoZ9BLaxo9GDQ9B3WLuUPieOFYlYoyw2d7OIIb9KW269AEHOXKwlj+FLUYt6lWRGI io6TfrMkaogxPet+GDXEyVlsqojpzOufXEWzMtJpQNuh6yYF8Rwj6dMoTTN8KYvBpx gnfQNM9yHCtYw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E18FCAC5A0; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) From: Dang Huynh via B4 Relay Date: Wed, 17 Sep 2025 03:25:06 +0700 Subject: [PATCH 09/25] dt-bindings: clock: Add RDA Micro RDA8810PL clock/reset controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-rda8810pl-drivers-v1-9-9ca9184ca977@mainlining.org> References: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> In-Reply-To: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> To: Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Alexandre Belloni , Michael Turquette , Stephen Boyd , Philipp Zabel , Sebastian Reichel , Vinod Koul , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, dmaengine@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mmc@vger.kernel.org, Dang Huynh X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758054322; l=3631; i=dang.huynh@mainlining.org; s=20250917; h=from:subject:message-id; bh=F0hJeg4vF8n1IM7OJY4KSBkC9cZRnfQ7Ctr7Iv83zwo=; b=W5aQqbp5wDQi2g8XC9wV9RV6i8ghSROwrftQm0G26e3EgJ7UwRgy8QFcZDW/kC8joRM4uC3Vz OnZu0YIn94TBd4gvxz2dnv/wUco20c3tMi/KuPVnqJ9wsl7lNQZzVrw X-Developer-Key: i=dang.huynh@mainlining.org; a=ed25519; pk=RyzH4CL4YU/ItXYUurA51EVBidfx4lIy8/E4EKRJCUk= X-Endpoint-Received: by B4 Relay for dang.huynh@mainlining.org/20250917 with auth_id=526 X-Original-From: Dang Huynh Reply-To: dang.huynh@mainlining.org From: Dang Huynh Add documentation describing the RDA8810PL Clock and Reset controller. Signed-off-by: Dang Huynh --- .../bindings/clock/rda,8810pl-apsyscon.yaml | 44 ++++++++++++ include/dt-bindings/clock/rda,8810pl-apclk.h | 79 ++++++++++++++++++= ++++ 2 files changed, 123 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/rda,8810pl-apsyscon.ya= ml b/Documentation/devicetree/bindings/clock/rda,8810pl-apsyscon.yaml new file mode 100644 index 0000000000000000000000000000000000000000..988b609403a96abc4964ab366da= a6fec0514595c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rda,8810pl-apsyscon.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rda,8810pl-apsyscon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RDA Micro RDA8810PL AP Clock Controller + +maintainers: + - Dang Huynh + +properties: + compatible: + items: + - const: rda,8810pl-apsyscon + - const: syscon + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + #include + + ap_syscon: syscon@0 { + compatible =3D "rda,8810pl-apsyscon", "syscon"; + reg =3D <0x0 0x1000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; diff --git a/include/dt-bindings/clock/rda,8810pl-apclk.h b/include/dt-bind= ings/clock/rda,8810pl-apclk.h new file mode 100644 index 0000000000000000000000000000000000000000..372358e72436a28c0775519f496= 26c9c5f4c6046 --- /dev/null +++ b/include/dt-bindings/clock/rda,8810pl-apclk.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ + +#ifndef _DT_BINDINGS_CLK_RDA8810_H_ +#define _DT_BINDINGS_CLK_RDA8810_H_ + +/* soc clocks */ +#define CLK_CPU 0 +#define CLK_BUS 1 +#define CLK_MEM 2 + +#define CLK_USB 3 +#define CLK_AXI 4 +#define CLK_GCG 5 +#define CLK_AHB1 6 +#define CLK_APB1 7 +#define CLK_APB2 8 + +#define CLK_GPU 9 +#define CLK_VPU 10 +#define CLK_VOC 11 +#define CLK_SFLSH 12 + +#define CLK_UART1 13 +#define CLK_UART2 14 +#define CLK_UART3 15 + +#define CLK_VOC2 16 +#define CLK_EMMC 17 + +#define CLK_COUNT (CLK_EMMC + 1) + +/* resets */ +#define RST_CPU 0 + +#define RST_AXI_VOC 1 +#define RST_AXI_DMA 2 +#define RST_AXI_CONNECT 3 +#define RST_AXI_VPU 4 + +#define RST_GCG_GOUDA 5 +#define RST_GCG_CAMERA 6 +#define RST_GCG_LCDC 7 + +#define RST_AHB1_USBC 8 +#define RST_AHB1_SPIFLASH 9 + +#define RST_APB1_TIMER 10 +#define RST_APB1_KEYPAD 11 +#define RST_APB1_GPIO 12 +#define RST_APB1_PWM 13 +#define RST_APB1_AIF 14 +#define RST_APB1_AUIFC 15 +#define RST_APB1_I2C1 16 +#define RST_APB1_I2C2 17 +#define RST_APB1_I2C3 18 +#define RST_APB1_COMREGS 19 +#define RST_APB1_DMC 20 +#define RST_APB1_DDRPHY_P 21 + +#define RST_APB2_IFC 22 +#define RST_APB2_UART1 23 +#define RST_APB2_UART2 24 +#define RST_APB2_UART3 25 +#define RST_APB2_SPI1 26 +#define RST_APB2_SPI2 27 +#define RST_APB2_SPI3 28 +#define RST_APB2_SDMMC1 29 +#define RST_APB2_SDMMC2 30 +#define RST_APB2_SDMMC3 31 +#define RST_APB2_NAND 32 + +#define RST_MEM_GPU 33 +#define RST_MEM_VPU 34 +#define RST_MEM_DMC 35 +#define RST_MEM_DDRPHY_P 36 + +#define RST_COUNT (RST_MEM_DDRPHY_P + 1) + +#endif /* _DT_BINDINGS_CLK_RDA8810_H_ */ --=20 2.51.0 From nobody Thu Oct 2 13:03:51 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0EBE5323F51; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-rda8810pl-drivers-v1-10-9ca9184ca977@mainlining.org> References: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> In-Reply-To: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> To: Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Alexandre Belloni , Michael Turquette , Stephen Boyd , Philipp Zabel , Sebastian Reichel , Vinod Koul , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, dmaengine@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mmc@vger.kernel.org, Dang Huynh X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758054322; l=26571; i=dang.huynh@mainlining.org; s=20250917; h=from:subject:message-id; bh=viiqgCEDzz7zJ0J1XOj3LXd3b+khlbXGBeY3H7SkBMc=; b=s1kimWXztfMI3RjptT8l1WdNs/VmkG8cjP/SoOZzfKLfnmFMoWDN72VKorAFCOiOLacyXmvxy 60R7+ZO04QQAKfPtM+hf7SQWHhApvL3WzsDPUf2LhSkl/QH0VYalBHv X-Developer-Key: i=dang.huynh@mainlining.org; a=ed25519; pk=RyzH4CL4YU/ItXYUurA51EVBidfx4lIy8/E4EKRJCUk= X-Endpoint-Received: by B4 Relay for dang.huynh@mainlining.org/20250917 with auth_id=526 X-Original-From: Dang Huynh Reply-To: dang.huynh@mainlining.org From: Dang Huynh Add a clock/reset driver for RDA8810PL SoC, which provides clocks for various subsystems. Signed-off-by: Dang Huynh --- MAINTAINERS | 6 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/rda/Kconfig | 14 + drivers/clk/rda/Makefile | 2 + drivers/clk/rda/clk-rda8810.c | 770 ++++++++++++++++++++++++++++++++++++++= ++++ 6 files changed, 794 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0549b1d0657f2caaf86a723db139cf9d84d59c4a..cbe2ab8af6dcd40dd1456d9df55= 673dace3c87b2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21393,6 +21393,12 @@ S: Supported T: git git://git.kernel.org/pub/scm/linux/kernel/git/rcu/linux.git rcu/dev F: tools/testing/selftests/rcutorture =20 +RDA MICRO CLOCK AND RESET DRIVER +M: Dang Huynh +S: Maintained +F: Documentation/devicetree/bindings/clock/rda,8810pl-apsyscon.yaml +F: drivers/clk/rda/clk-rda8810.c + RDA MICRO REAL TIME CLOCK DRIVER M: Dang Huynh S: Maintained diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index b1425aed659387a676bd933fe50ac4894c7156fe..15f5bc9108b565acb1c3c6e978a= d0e5a71f5550d 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -520,6 +520,7 @@ source "drivers/clk/nuvoton/Kconfig" source "drivers/clk/pistachio/Kconfig" source "drivers/clk/qcom/Kconfig" source "drivers/clk/ralink/Kconfig" +source "drivers/clk/rda/Kconfig" source "drivers/clk/renesas/Kconfig" source "drivers/clk/rockchip/Kconfig" source "drivers/clk/samsung/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 18ed29cfdc1133b6c254190c6092eb263366d5ac..8241bb7f88daaebde766ba92d71= 8b2ca710d6b5f 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -141,6 +141,7 @@ obj-$(CONFIG_COMMON_CLK_PISTACHIO) +=3D pistachio/ obj-$(CONFIG_COMMON_CLK_PXA) +=3D pxa/ obj-$(CONFIG_COMMON_CLK_QCOM) +=3D qcom/ obj-y +=3D ralink/ +obj-y +=3D rda/ obj-y +=3D renesas/ obj-$(CONFIG_ARCH_ROCKCHIP) +=3D rockchip/ obj-$(CONFIG_COMMON_CLK_SAMSUNG) +=3D samsung/ diff --git a/drivers/clk/rda/Kconfig b/drivers/clk/rda/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..b505e3e552cef1e7ea3da4aa46d= 61d0d0a3d5db0 --- /dev/null +++ b/drivers/clk/rda/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only +config CLK_RDA8810 + bool "RDA Micro RDA8810PL Clock and Reset Controller" + depends on ARCH_RDA || COMPILE_TEST + select MFD_SYSCON + select REGMAP_MMIO + select RESET_CONTROLLER + help + This driver supports clock and reset for RDA Micro RDA8810 platform. + If you have a board with the RDA8810PL SoC, say Y to use most of the + board peripherals. + + If unsure, say N. + diff --git a/drivers/clk/rda/Makefile b/drivers/clk/rda/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..98848dccabe5d2199d5e9469d6b= de154b2b3d86a --- /dev/null +++ b/drivers/clk/rda/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_CLK_RDA8810) +=3D clk-rda8810.o diff --git a/drivers/clk/rda/clk-rda8810.c b/drivers/clk/rda/clk-rda8810.c new file mode 100644 index 0000000000000000000000000000000000000000..8bea60d5376aeb4c67cd15bc1a6= 4dbcf7a0a1f7c --- /dev/null +++ b/drivers/clk/rda/clk-rda8810.c @@ -0,0 +1,770 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * RDA8810PL Clock and Reset driver + * + * Copyright (C) 2013 RDA Microelectronics Inc. + * Copyright (c) 2025 Dang Huynh + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MHZ 1000000U + +/* + * Some registers are protected, we need to write AP_CTRL_PROTECT_UNLOCK to + * AP_REG_DBG then we can make changes to them. + */ +#define AP_CTRL_PROTECT_LOCK 0xA50000 +#define AP_CTRL_PROTECT_UNLOCK 0xA50001 + +/* Register Base */ +#define AP_REG_DBG 0x0 +#define AP_REG_CPU_ENABLE 0x60 +#define AP_REG_AXI_ENABLE 0x6C +#define AP_REG_AXIDIV2_ENABLE 0x78 +#define AP_REG_GCG_ENABLE 0x84 +#define AP_REG_AHB1_ENABLE 0x90 +#define AP_REG_APB1_ENABLE 0x9C +#define AP_REG_APB2_ENABLE 0xA8 +#define AP_REG_MEM_ENABLE 0xB4 +#define AP_REG_APO_ENABLE 0xC0 + +/* AP Clk Config Bits */ +#define AP_PERI_SRC_DIV BIT(12) + +/* UART Clock Bits */ +#define AP_UART_DIVIDER GENMASK(9, 0) +#define AP_UART_SET_PLL BIT(12) + +/* AP Clk Enable */ +#define AP_ENABLE_CPU_CORE BIT(0) +#define AP_ENABLE_CPU_DUMMY BIT(1) +#define AP_ENABLE_AHB0_CONF BIT(0) +#define AP_ENABLE_APB0_CONF BIT(1) +#define AP_ENABLE_AXI_VOC BIT(2) +#define AP_ENABLE_AXI_DMA BIT(3) +#define AP_ENABLE_AXI_ALWAYS BIT(4) +#define AP_ENABLE_AXI_CONNECT BIT(5) +#define AP_ENABLE_APB0_IRQ BIT(6) +#define AP_ENABLE_AXIDIV2_IMEM BIT(0) +#define AP_ENABLE_AXIDIV2_ALWAYS BIT(1) +#define AP_ENABLE_AXIDIV2_CONNECT BIT(2) +#define AP_ENABLE_AXIDIV2_VPU BIT(3) +#define AP_ENABLE_GCG_APB_CONF BIT(0) +#define AP_ENABLE_GCG_GOUDA BIT(1) +#define AP_ENABLE_GCG_CAMERA BIT(2) +#define AP_ENABLE_GCG_ALWAYS BIT(3) +#define AP_ENABLE_GCG_CONNECT BIT(4) +#define AP_ENABLE_GCG_DPI BIT(7) +#define AP_ENABLE_AHB1_USBC BIT(0) +#define AP_ENABLE_AHB1_ALWAYS BIT(1) +#define AP_ENABLE_AHB1_SPIFLASH BIT(2) +#define AP_ENABLE_APB1_CONF BIT(0) +#define AP_ENABLE_APB1_AIF BIT(1) +#define AP_ENABLE_APB1_AUIFC BIT(2) +#define AP_ENABLE_APB1_AUIFC_CH0 BIT(3) +#define AP_ENABLE_APB1_AUIFC_CH1 BIT(4) +#define AP_ENABLE_APB1_I2C1 BIT(5) +#define AP_ENABLE_APB1_I2C2 BIT(6) +#define AP_ENABLE_APB1_I2C3 BIT(7) +#define AP_ENABLE_APB1D_OSC BIT(8) +#define AP_ENABLE_APB1D_PWM BIT(9) +#define AP_ENABLE_APB1_ALWAYS BIT(10) +#define AP_ENABLE_APB1_DAPLITE BIT(11) +#define AP_ENABLE_APB1_TIMER BIT(12) +#define AP_ENABLE_APB1_GPIO BIT(13) +#define AP_ENABLE_APB2_CONF BIT(0) +#define AP_ENABLE_APB2_IFC BIT(1) +#define AP_ENABLE_APB2_IFC_CH0 BIT(2) +#define AP_ENABLE_APB2_IFC_CH1 BIT(3) +#define AP_ENABLE_APB2_IFC_CH2 BIT(4) +#define AP_ENABLE_APB2_IFC_CH3 BIT(5) +#define AP_ENABLE_APB2_IFC_CH4 BIT(6) +#define AP_ENABLE_APB2_IFC_CH5 BIT(7) +#define AP_ENABLE_APB2_IFC_CH6 BIT(8) +#define AP_ENABLE_APB2_IFC_CH7 BIT(9) +#define AP_ENABLE_APB2_UART1 BIT(10) +#define AP_ENABLE_APB2_UART2 BIT(11) +#define AP_ENABLE_APB2_UART3 BIT(12) +#define AP_ENABLE_APB2_SPI1 BIT(13) +#define AP_ENABLE_APB2_SPI2 BIT(14) +#define AP_ENABLE_APB2_SPI3 BIT(15) +#define AP_ENABLE_APB2_SDMMC1 BIT(16) +#define AP_ENABLE_APB2_SDMMC2 BIT(17) +#define AP_ENABLE_APB2_SDMMC3 BIT(18) +#define AP_ENABLE_APB2_ALWAYS BIT(19) +#define AP_ENABLE_APB2_NANDFLASH BIT(20) +#define AP_ENABLE_MEM_CONF BIT(0) +#define AP_ENABLE_MEM_DMC BIT(1) +#define AP_ENABLE_MEM_GPU BIT(2) +#define AP_ENABLE_MEM_VPU BIT(3) +#define AP_ENABLE_MEM_DDRPHY_P BIT(4) +#define AP_ENABLE_MEM_CONNECT BIT(5) +#define AP_ENABLE_APOC_VPU BIT(0) +#define AP_ENABLE_APOC_BCK BIT(1) +#define AP_ENABLE_APOC_UART1 BIT(2) +#define AP_ENABLE_APOC_UART2 BIT(3) +#define AP_ENABLE_APOC_UART3 BIT(4) +#define AP_ENABLE_APOC_VOC_CORE BIT(5) +#define AP_ENABLE_APOC_VOC BIT(6) +#define AP_ENABLE_APOC_VOC_ALWAYS BIT(7) +#define AP_ENABLE_APOC_DDRPHY_N BIT(8) +#define AP_ENABLE_APOC_DDRPHY2XP BIT(9) +#define AP_ENABLE_APOC_DDRPHY2XN BIT(10) +#define AP_ENABLE_APOC_GPU BIT(11) +#define AP_ENABLE_APOC_USBPHY BIT(12) +#define AP_ENABLE_APOC_CSI BIT(13) +#define AP_ENABLE_APOC_DSI BIT(14) +#define AP_ENABLE_APOC_GPIO BIT(15) +#define AP_ENABLE_APOC_SPIFLASH BIT(16) +#define AP_ENABLE_APOC_PIX BIT(17) +#define AP_ENABLE_APOC_PDGB BIT(18) + +/* AP Reset */ +#define AP_RST_CPU_REG 0x1C +#define AP_RST_AXI_REG 0x24 +#define AP_RST_AXIDIV2_REG 0x2C +#define AP_RST_GCG_REG 0x34 +#define AP_RST_AHB1_REG 0x3C +#define AP_RST_APB1_REG 0x44 +#define AP_RST_APB2_REG 0x4C +#define AP_RST_MEM_REG 0x54 + +/* Bits */ +#define AP_RST_CPU_CORE BIT(0) +#define AP_RST_CPU_SYS BIT(1) +#define AP_RST_AXI_VOC BIT(0) +#define AP_RST_AXI_DMA BIT(1) +#define AP_RST_AXI_SYS BIT(2) +#define AP_RST_AXI_CONNECT BIT(3) +#define AP_RST_AXI_VPU BIT(5) +#define AP_RST_AXIDIV2_IMEM BIT(0) +#define AP_RST_AXIDIV2_SYS BIT(1) +#define AP_RST_AXIDIV2_VPU BIT(2) +#define AP_RST_GCG_SYS BIT(0) +#define AP_RST_GCG_GOUDA BIT(1) +#define AP_RST_GCG_CAMERA BIT(2) +#define AP_RST_GCG_LCDC BIT(4) +#define AP_RST_AHB1_SYS BIT(0) +#define AP_RST_AHB1_USBC BIT(1) +#define AP_RST_AHB1_SPIFLASH BIT(2) +#define AP_RST_APB1_SYS BIT(0) +#define AP_RST_APB1_TIMER BIT(1) +#define AP_RST_APB1_KEYPAD BIT(2) +#define AP_RST_APB1_GPIO BIT(3) +#define AP_RST_APB1_PWM BIT(4) +#define AP_RST_APB1_AIF BIT(5) +#define AP_RST_APB1_AUIFC BIT(6) +#define AP_RST_APB1_I2C1 BIT(7) +#define AP_RST_APB1_I2C2 BIT(8) +#define AP_RST_APB1_I2C3 BIT(9) +#define AP_RST_APB1_COMREGS BIT(10) +#define AP_RST_APB1_DMC BIT(11) +#define AP_RST_APB1_DDRPHY_P BIT(12) +#define AP_RST_APB2_SYS BIT(0) +#define AP_RST_APB2_IFC BIT(1) +#define AP_RST_APB2_UART1 BIT(2) +#define AP_RST_APB2_UART2 BIT(3) +#define AP_RST_APB2_UART3 BIT(4) +#define AP_RST_APB2_SPI1 BIT(5) +#define AP_RST_APB2_SPI2 BIT(6) +#define AP_RST_APB2_SPI3 BIT(7) +#define AP_RST_APB2_SDMMC1 BIT(8) +#define AP_RST_APB2_SDMMC2 BIT(9) +#define AP_RST_APB2_SDMMC3 BIT(10) +#define AP_RST_APB2_NANDFLASH BIT(11) +#define AP_RST_MEM_SYS BIT(0) +#define AP_RST_MEM_GPU BIT(1) +#define AP_RST_MEM_VPU BIT(2) +#define AP_RST_MEM_DMC BIT(3) +#define AP_RST_MEM_DDRPHY_P BIT(4) + +/* Default PLL frequency */ +#define AP_PLL_CPU_FREQ (988 * MHZ) +#define AP_PLL_BUS_FREQ (800 * MHZ) +#define AP_PLL_MEM_FREQ (260 * MHZ) +#define AP_PLL_USB_FREQ (480 * MHZ) + +struct rda8810_reset_list { + int reg; + int bit; +}; + +struct rda_clk_priv { + struct device *dev; + struct regmap *regmap; + struct clk_hw_onecell_data *onecell; + struct reset_controller_dev rstctl; + const struct rda8810_reset_list *rstlist; +}; + +struct rda_clk_hw { + int id; + int reg; + struct clk_hw hw; + + int ena_reg; + int ena_bit; + + struct rda_clk_priv *priv; +}; + +struct rda_clk_matchdata { + const struct rda_clk_hw *clk_list; + int max_clocks; +}; + +static const struct clk_ops rda8810_clk_ops; + +#define RDA_CLK_INIT(_id, _name, _parent, _flags, _reg, _ena_reg, _ena_bit= ) { \ + .id =3D _id, \ + .reg =3D _reg, \ + .ena_reg =3D _ena_reg, \ + .ena_bit =3D _ena_bit, \ + .hw.init =3D CLK_HW_INIT_PARENTS_DATA(_name, \ + _parent, \ + &rda8810_clk_ops, \ + _flags) \ +} + +#define RDA_CLK_INIT_NO_PARENT(_id, _name, _flags, _reg, _ena_reg, _ena_bi= t) { \ + .id =3D _id, \ + .reg =3D _reg, \ + .ena_reg =3D _ena_reg, \ + .ena_bit =3D _ena_bit, \ + .hw.init =3D CLK_HW_INIT_NO_PARENT(_name, &rda8810_clk_ops, _flags) \ +} + +#define to_rda_rst(p) container_of(p, struct rda_clk_priv, rstctl) + +static inline struct rda_clk_hw *to_rda_hw(struct clk_hw *hw) +{ + return container_of(hw, struct rda_clk_hw, hw); +} + +/* clock division value map */ +static const u8 clk_div_map[] =3D { + 4*60, /* 0 */ + 4*60, /* 1 */ + 4*60, /* 2 */ + 4*60, /* 3 */ + 4*60, /* 4 */ + 4*60, /* 5 */ + 4*60, /* 6 */ + 4*60, /* 7 */ + 4*40, /* 8 */ + 4*30, /* 9 */ + 4*24, /* 10 */ + 4*20, /* 11 */ + 4*17, /* 12 */ + 4*15, /* 13 */ + 4*13, /* 14 */ + 4*12, /* 15 */ + 4*11, /* 16 */ + 4*10, /* 17 */ + 4*9, /* 18 */ + 4*8, /* 19 */ + 4*7, /* 20 */ + 4*13/2, /* 21 */ + 4*6, /* 22 */ + 4*11/2, /* 23 */ + 4*5, /* 24 */ + 4*9/2, /* 25 */ + 4*4, /* 26 */ + 4*7/2, /* 27 */ + 4*3, /* 28 */ + 4*5/2, /* 29 */ + 4*2, /* 30 */ + 4*1, /* 31 */ +}; + +static u32 apsys_get_divreg(u32 basefreq, u32 reqfreq, u32 *pdiv2) +{ + int i; + int index; + u32 adiv; + u32 ndiv; + + adiv =3D basefreq / (reqfreq >> 2); + if (pdiv2) { + /* try div2 mode first */ + ndiv =3D adiv >> 1; + } else { + ndiv =3D adiv; + } + + for (i =3D ARRAY_SIZE(clk_div_map) - 1; i >=3D 1; i--) + if (ndiv < ((clk_div_map[i] + clk_div_map[i-1]) >> 1)) + break; + index =3D i; + + if (pdiv2) { + if (adiv =3D=3D (clk_div_map[index] << 1)) { + /* div2 mode is OK */ + *pdiv2 =3D 1; + } else { + /* try div1 mode */ + for (i =3D ARRAY_SIZE(clk_div_map) - 1; i >=3D 1; i--) + if (adiv < ((clk_div_map[i] + clk_div_map[i-1]) >> 1)) + break; + /* compare the results between div1 and div2 */ + if (abs(adiv - (clk_div_map[index] << 1)) <=3D + abs(adiv - clk_div_map[i])) { + *pdiv2 =3D 1; + } else { + *pdiv2 =3D 0; + index =3D i; + } + } + } + + return index; +} + +static u32 apsys_cal_freq_by_divreg(u32 basefreq, u32 reg, u32 div2) +{ + u32 newfreq; + + if (reg >=3D ARRAY_SIZE(clk_div_map)) + reg =3D ARRAY_SIZE(clk_div_map) - 1; + + /* Assuming basefreq is smaller than 2^31 (2.147G Hz) */ + newfreq =3D (basefreq << (div2 ? 0 : 1)) / (clk_div_map[reg] >> 1); + return newfreq; +} + +static void apsys_get_reg_div(struct rda_clk_hw *rda_hw, u32 *reg, u32 *di= v2) +{ + struct rda_clk_priv *priv =3D rda_hw->priv; + int tmp_reg, tmp_div2; + int ret; + + ret =3D regmap_read(priv->regmap, rda_hw->reg, &tmp_reg); + if (ret) + return; + + tmp_div2 =3D tmp_reg & AP_PERI_SRC_DIV; + + *reg =3D tmp_reg; + *div2 =3D tmp_div2; +} + +static int apsys_get_uart_clock(unsigned long parent_rate, u32 *reg) +{ + int clksrc =3D 26000000; + u32 div; + int rate =3D 0; + + if (*reg & AP_UART_SET_PLL) + clksrc =3D parent_rate / 8; + + div =3D FIELD_GET(AP_UART_DIVIDER, *reg); + + /* rate =3D clksrc / divmode / (div+2) */ + rate =3D clksrc / 4 / (div + 2); + + return rate; +} + +static int apsys_cal_uart_clock(int freq) +{ + int new_freq =3D freq; + + /* + * To calculate maximum clock: + * freq =3D 26 MHz / div / (0 + 2) + * + * For lowest clock: + * freq =3D 26 MHz / div / (0x3FF + 2) + */ + if (freq > 3250000) + new_freq =3D 3250000; + else if (freq < 6342) + new_freq =3D 6342; + + new_freq =3D (26000000 + 4 / 2 * new_freq) / (4 * new_freq) - 2; + + return new_freq; +} + +static int rda8810_clk_set_rate(struct clk_hw *clk, unsigned long rate, + unsigned long parent_rate) +{ + struct rda_clk_hw *rda_hw =3D to_rda_hw(clk); + struct rda_clk_priv *priv =3D rda_hw->priv; + struct device *dev =3D priv->dev; + int val, div2 =3D 0; + int ret; + + switch (rda_hw->id) { + case CLK_CPU: + val =3D apsys_get_divreg(AP_PLL_CPU_FREQ, rate, NULL); + break; + case CLK_AXI: + case CLK_AHB1: + case CLK_APB1: + case CLK_APB2: + case CLK_GCG: + case CLK_GPU: + case CLK_SFLSH: + case CLK_VOC: + case CLK_VPU: + val =3D apsys_get_divreg(parent_rate, rate, &div2); + break; + case CLK_UART1: + case CLK_UART2: + case CLK_UART3: + val =3D apsys_cal_uart_clock(rate); + if (val =3D=3D 0) + return -EINVAL; + break; + default: + return -EINVAL; + } + + if (div2) + val |=3D AP_PERI_SRC_DIV; + + dev_dbg(dev, "clk_id: %d - rate: %ld - parent rate: %ld - val: %d - div: = %d\n", + rda_hw->id, rate, parent_rate, val, div2); + + ret =3D regmap_write(priv->regmap, rda_hw->reg, val); + if (ret < 0) + return ret; + + return rate; +} + +static unsigned long rda8810_clk_recalc_rate(struct clk_hw *clk, + unsigned long parent_rate) +{ + struct rda_clk_hw *rda_hw =3D to_rda_hw(clk); + u32 reg, div2; + + apsys_get_reg_div(rda_hw, ®, &div2); + + switch (rda_hw->id) { + case CLK_CPU: + return apsys_cal_freq_by_divreg(AP_PLL_CPU_FREQ, reg, 0); + case CLK_BUS: + return AP_PLL_BUS_FREQ; + case CLK_MEM: + return AP_PLL_MEM_FREQ >> (2 + div2); + /* Bus peripherals */ + case CLK_USB: + return AP_PLL_USB_FREQ; + case CLK_AXI: + case CLK_AHB1: + case CLK_APB1: + case CLK_APB2: + case CLK_GCG: + case CLK_GPU: + case CLK_SFLSH: + case CLK_VOC: + case CLK_VPU: + return apsys_cal_freq_by_divreg(parent_rate, reg, div2); + /* For UART clocks, we'll have to do more calculation */ + case CLK_UART1: + case CLK_UART2: + case CLK_UART3: + return apsys_get_uart_clock(parent_rate, ®); + default: + return 0; + } +} + +static long rda8810_clk_round_rate(struct clk_hw *clk, unsigned long rate, + unsigned long *parent_rate) +{ + return rate; +} + +static int rda8810_clk_enable(struct clk_hw *clk) +{ + struct rda_clk_hw *rda_hw =3D to_rda_hw(clk); + struct rda_clk_priv *priv =3D rda_hw->priv; + + if (rda_hw->ena_reg < 0 || rda_hw->ena_bit < 0) + return 0; + + return regmap_write(priv->regmap, rda_hw->ena_reg, rda_hw->ena_bit); +} + +static void rda8810_clk_disable(struct clk_hw *clk) +{ + struct rda_clk_hw *rda_hw =3D to_rda_hw(clk); + struct rda_clk_priv *priv =3D rda_hw->priv; + + if (rda_hw->ena_reg < 0 || rda_hw->ena_bit < 0) + return; + + regmap_write(priv->regmap, rda_hw->ena_reg + 4, rda_hw->ena_bit); +} + +static const struct clk_ops rda8810_clk_ops =3D { + .enable =3D rda8810_clk_enable, + .disable =3D rda8810_clk_disable, + + .recalc_rate =3D rda8810_clk_recalc_rate, + .round_rate =3D rda8810_clk_round_rate, + .set_rate =3D rda8810_clk_set_rate, +}; + +/* Root clocks */ +static struct rda_clk_hw rda8810_clk_cpu_desc =3D +RDA_CLK_INIT_NO_PARENT(CLK_CPU, "cpu", CLK_IS_CRITICAL, 0xC8, + AP_REG_CPU_ENABLE, AP_ENABLE_CPU_CORE); +static struct rda_clk_hw rda8810_clk_mem_desc =3D +RDA_CLK_INIT_NO_PARENT(CLK_MEM, "mem", CLK_IS_CRITICAL, 0xE0, -1, -1); + +static struct rda_clk_hw rda8810_clk_bus_desc =3D +RDA_CLK_INIT_NO_PARENT(CLK_BUS, "bus", CLK_IS_CRITICAL, -1, -1, -1); + +/* Bus clocks */ +static struct rda_clk_hw rda8810_clk_usb_desc =3D RDA_CLK_INIT(CLK_USB, "u= sb", + (const struct clk_parent_data[]) { { .hw =3D &rda8810_clk_bus_desc.hw } = }, + 0, -1, -1, -1); +static struct rda_clk_hw rda8810_clk_axi_desc =3D RDA_CLK_INIT(CLK_AXI, "a= xi", + (const struct clk_parent_data[]) { { .hw =3D &rda8810_clk_bus_desc.hw } = }, + 0, 0xCC, -1, -1); +static struct rda_clk_hw rda8810_clk_gcg_desc =3D RDA_CLK_INIT(CLK_GCG, "g= cg", + (const struct clk_parent_data[]) { { .hw =3D &rda8810_clk_bus_desc.hw } = }, + 0, 0xD0, -1, -1); +static struct rda_clk_hw rda8810_clk_ahb1_desc =3D RDA_CLK_INIT(CLK_AHB1, = "ahb1", + (const struct clk_parent_data[]) { { .hw =3D &rda8810_clk_bus_desc.hw } = }, + 0, 0xD4, -1, -1); +static struct rda_clk_hw rda8810_clk_apb1_desc =3D RDA_CLK_INIT(CLK_APB1, = "apb1", + (const struct clk_parent_data[]) { { .hw =3D &rda8810_clk_bus_desc.hw } = }, + 0, 0xD8, -1, -1); +static struct rda_clk_hw rda8810_clk_apb2_desc =3D RDA_CLK_INIT(CLK_APB2, = "apb2", + (const struct clk_parent_data[]) { { .hw =3D &rda8810_clk_bus_desc.hw } = }, + 0, 0xDC, -1, -1); +static struct rda_clk_hw rda8810_clk_gpu_desc =3D RDA_CLK_INIT(CLK_GPU, "g= pu", + (const struct clk_parent_data[]) { { .hw =3D &rda8810_clk_bus_desc.hw } = }, + 0, 0xE4, AP_REG_APO_ENABLE, AP_ENABLE_APOC_GPU); +static struct rda_clk_hw rda8810_clk_vpu_desc =3D RDA_CLK_INIT(CLK_VPU, "v= pu", + (const struct clk_parent_data[]) { { .hw =3D &rda8810_clk_bus_desc.hw } = }, + 0, 0xE8, AP_REG_APO_ENABLE, AP_ENABLE_APOC_VPU); +static struct rda_clk_hw rda8810_clk_voc_desc =3D RDA_CLK_INIT(CLK_VOC, "v= oc", + (const struct clk_parent_data[]) { { .hw =3D &rda8810_clk_bus_desc.hw } = }, + 0, 0xEC, AP_REG_APO_ENABLE, + AP_ENABLE_APOC_VOC | AP_ENABLE_APOC_VOC_CORE | AP_ENABLE_APOC_VOC_ALWAYS= ); + +/* APB1 peripherals */ +static struct rda_clk_hw rda8810_clk_spiflash_desc =3D RDA_CLK_INIT(CLK_SF= LSH, "spiflash", + (const struct clk_parent_data[]) { { .hw =3D &rda8810_clk_apb1_desc.hw }= }, + 0, 0xF0, AP_REG_APO_ENABLE, AP_ENABLE_APOC_SPIFLASH); + +/* APB2 peripherals */ +static struct rda_clk_hw rda8810_clk_uart_desc[] =3D { + RDA_CLK_INIT(CLK_UART1, "uart1", + (const struct clk_parent_data[]) { { .hw =3D &rda8810_clk_apb2_desc.hw = } }, + 0, 0xF4, + AP_REG_APO_ENABLE, AP_ENABLE_APOC_UART1), + RDA_CLK_INIT(CLK_UART2, "uart2", + (const struct clk_parent_data[]) { { .hw =3D &rda8810_clk_apb2_desc.hw = } }, + 0, 0xF8, + AP_REG_APO_ENABLE, AP_ENABLE_APOC_UART2), + RDA_CLK_INIT(CLK_UART3, "uart3", + (const struct clk_parent_data[]) { { .hw =3D &rda8810_clk_apb2_desc.hw = } }, + 0, 0xFC, + AP_REG_APO_ENABLE, AP_ENABLE_APOC_UART3), +}; + +static struct rda_clk_hw *const rda8810_clk_list[] =3D { + &rda8810_clk_cpu_desc, + &rda8810_clk_bus_desc, + &rda8810_clk_mem_desc, + + &rda8810_clk_usb_desc, + &rda8810_clk_axi_desc, + &rda8810_clk_gcg_desc, + &rda8810_clk_ahb1_desc, + &rda8810_clk_apb1_desc, + &rda8810_clk_apb2_desc, + + &rda8810_clk_gpu_desc, + &rda8810_clk_vpu_desc, + &rda8810_clk_voc_desc, + + &rda8810_clk_spiflash_desc, + + &rda8810_clk_uart_desc[0], + &rda8810_clk_uart_desc[1], + &rda8810_clk_uart_desc[2], +}; + +static const struct rda8810_reset_list rda8810_rst_data[] =3D { + /* ID, REG */ + + /* CPU */ + [RST_CPU] =3D { AP_RST_CPU_REG, AP_RST_CPU_CORE }, + + /* AXI */ + [RST_AXI_VOC] =3D { AP_RST_AXI_REG, AP_RST_AXI_VOC }, + [RST_AXI_DMA] =3D { AP_RST_AXI_REG, AP_RST_AXI_DMA }, + [RST_AXI_CONNECT] =3D { AP_RST_AXI_REG, AP_RST_AXI_CONNECT }, + [RST_AXI_VPU] =3D { AP_RST_AXI_REG, AP_RST_AXI_VPU }, + + /* GCG */ + [RST_GCG_GOUDA] =3D { AP_RST_GCG_REG, AP_RST_GCG_GOUDA }, + [RST_GCG_CAMERA] =3D { AP_RST_GCG_REG, AP_RST_GCG_CAMERA }, + [RST_GCG_LCDC] =3D { AP_RST_GCG_REG, AP_RST_GCG_LCDC }, + + /* AHB1 */ + [RST_AHB1_USBC] =3D { AP_RST_AHB1_REG, AP_RST_AHB1_USBC }, + [RST_AHB1_SPIFLASH] =3D { AP_RST_AHB1_REG, AP_RST_AHB1_SPIFLASH }, + + /* APB1 */ + [RST_APB1_TIMER] =3D { AP_RST_APB1_REG, AP_RST_APB1_TIMER }, + [RST_APB1_KEYPAD] =3D { AP_RST_APB1_REG, AP_RST_APB1_KEYPAD }, + [RST_APB1_GPIO] =3D { AP_RST_APB1_REG, AP_RST_APB1_GPIO }, + [RST_APB1_PWM] =3D { AP_RST_APB1_REG, AP_RST_APB1_PWM }, + [RST_APB1_AIF] =3D { AP_RST_APB1_REG, AP_RST_APB1_AIF }, + [RST_APB1_AUIFC] =3D { AP_RST_APB1_REG, AP_RST_APB1_AUIFC }, + [RST_APB1_I2C1] =3D { AP_RST_APB1_REG, AP_RST_APB1_I2C1 }, + [RST_APB1_I2C2] =3D { AP_RST_APB1_REG, AP_RST_APB1_I2C2 }, + [RST_APB1_I2C3] =3D { AP_RST_APB1_REG, AP_RST_APB1_I2C3 }, + [RST_APB1_COMREGS] =3D { AP_RST_APB1_REG, AP_RST_APB1_COMREGS }, + [RST_APB1_DMC] =3D { AP_RST_APB1_REG, AP_RST_APB1_DMC }, + [RST_APB1_DDRPHY_P] =3D { AP_RST_APB1_REG, AP_RST_APB1_DDRPHY_P }, + + /* APB2 */ + [RST_APB2_IFC] =3D { AP_RST_APB2_REG, AP_RST_APB2_IFC }, + [RST_APB2_UART1] =3D { AP_RST_APB2_REG, AP_RST_APB2_UART1 }, + [RST_APB2_UART2] =3D { AP_RST_APB2_REG, AP_RST_APB2_UART2 }, + [RST_APB2_UART3] =3D { AP_RST_APB2_REG, AP_RST_APB2_UART3 }, + [RST_APB2_SPI1] =3D { AP_RST_APB2_REG, AP_RST_APB2_SPI1 }, + [RST_APB2_SPI2] =3D { AP_RST_APB2_REG, AP_RST_APB2_SPI2 }, + [RST_APB2_SPI3] =3D { AP_RST_APB2_REG, AP_RST_APB2_SPI3 }, + [RST_APB2_SDMMC1] =3D { AP_RST_APB2_REG, AP_RST_APB2_SDMMC1 }, + [RST_APB2_SDMMC2] =3D { AP_RST_APB2_REG, AP_RST_APB2_SDMMC2 }, + [RST_APB2_SDMMC3] =3D { AP_RST_APB2_REG, AP_RST_APB2_SDMMC3 }, + [RST_APB2_NAND] =3D { AP_RST_APB2_REG, AP_RST_APB2_NANDFLASH }, + + /* MEM */ + [RST_MEM_GPU] =3D { AP_RST_MEM_REG, AP_RST_MEM_GPU }, + [RST_MEM_VPU] =3D { AP_RST_MEM_REG, AP_RST_MEM_VPU }, + [RST_MEM_DMC] =3D { AP_RST_MEM_REG, AP_RST_MEM_DMC }, + [RST_MEM_DDRPHY_P] =3D { AP_RST_MEM_REG, AP_RST_MEM_DDRPHY_P }, +}; + +static int rda8810_reset_assert(struct reset_controller_dev *rstctl, unsig= ned long id) +{ + struct rda_clk_priv *priv =3D to_rda_rst(rstctl); + + return regmap_write(priv->regmap, rda8810_rst_data[id].reg, rda8810_rst_d= ata[id].bit); +} + +static int rda8810_reset_deassert(struct reset_controller_dev *rstctl, uns= igned long id) +{ + struct rda_clk_priv *priv =3D to_rda_rst(rstctl); + + return regmap_write(priv->regmap, rda8810_rst_data[id].reg + 4, rda8810_r= st_data[id].bit); +} + +static const struct reset_control_ops rda8810_rst_ops =3D { + .assert =3D &rda8810_reset_assert, + .deassert =3D &rda8810_reset_deassert, +}; + +static int rda8810_clk_register(struct rda_clk_priv *priv) +{ + struct device *dev =3D priv->dev; + struct clk_hw_onecell_data *onecell_data; + int ret; + int i; + + onecell_data =3D devm_kzalloc(dev, + struct_size(onecell_data, hws, ARRAY_SIZE(rda8810_clk_list)), + GFP_KERNEL); + if (!onecell_data) + return -ENOMEM; + + for (i =3D 0; i < ARRAY_SIZE(rda8810_clk_list); i++) { + rda8810_clk_list[i]->priv =3D priv; + + ret =3D devm_clk_hw_register(dev, &rda8810_clk_list[i]->hw); + if (ret) { + dev_err(dev, "Failed to register clock: %d\n", ret); + return ret; + } + onecell_data->hws[i] =3D &rda8810_clk_list[i]->hw; + } + onecell_data->num =3D i; + priv->onecell =3D onecell_data; + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, onecell_da= ta); +} + +static int rda8810_rst_register(struct rda_clk_priv *priv) +{ + struct device *dev =3D priv->dev; + + priv->rstctl.dev =3D priv->dev; + priv->rstctl.nr_resets =3D RST_COUNT; + priv->rstctl.of_node =3D priv->dev->of_node; + priv->rstctl.ops =3D &rda8810_rst_ops; + priv->rstctl.owner =3D THIS_MODULE; + + return devm_reset_controller_register(dev, &priv->rstctl); +} + +static int rda8810_clk_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct rda_clk_priv *priv; + int ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return dev_err_probe(dev, -ENOMEM, "Cannot allocate memory\n"); + + priv->dev =3D dev; + + priv->regmap =3D syscon_node_to_regmap(dev->of_node); + if (IS_ERR(priv->regmap)) + return dev_err_probe(dev, -ENOMEM, "Cannot initialize regmap\n"); + + ret =3D rda8810_clk_register(priv); + if (ret) + return dev_err_probe(dev, -EINVAL, "Failed to setup clock: %d\n", ret); + + ret =3D rda8810_rst_register(priv); + if (ret) + return dev_err_probe(dev, -EINVAL, "Failed to setup reset: %d\n", ret); + + platform_set_drvdata(pdev, priv); + + return 0; +} + +static const struct of_device_id rda8810_clk_of_match_table[] =3D { + { .compatible =3D "rda,8810pl-apsyscon", }, + { } +}; +MODULE_DEVICE_TABLE(of, rda8810_clk_of_match_table); + +static struct platform_driver rda8810_clk_driver =3D { + .probe =3D rda8810_clk_probe, + .driver =3D { + .name =3D "rda8810-clk", + .of_match_table =3D rda8810_clk_of_match_table, + }, +}; +module_platform_driver(rda8810_clk_driver); + +MODULE_AUTHOR("Dang Huynh "); +MODULE_DESCRIPTION("RDA8810PL clock and reset driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:rda8810-clk"); --=20 2.51.0 From nobody Thu Oct 2 13:03:51 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1AB3E323F62; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none 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unisoc: rda8810pl: Enable clock/reset driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-rda8810pl-drivers-v1-11-9ca9184ca977@mainlining.org> References: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> In-Reply-To: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> To: Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Alexandre Belloni , Michael Turquette , Stephen Boyd , Philipp Zabel , Sebastian Reichel , Vinod Koul , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, dmaengine@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mmc@vger.kernel.org, Dang Huynh X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758054322; l=1103; i=dang.huynh@mainlining.org; s=20250917; h=from:subject:message-id; bh=iisWV1yQIJV2H6A79OICiudNGMDM/d8wOSexhp4+9s4=; b=Uvbh1qdCuPgMg2Cya3wHJFP9B0zxFrsqfkRbRH3160/AsRSPEzMZMlwk9yvCgAuRqcoJQnphz LShcA3DOx1LBDlnxtXB3POz/cK5m8ZeoMMoHjCQKsqRFMuyqcxZ4qHk X-Developer-Key: i=dang.huynh@mainlining.org; a=ed25519; pk=RyzH4CL4YU/ItXYUurA51EVBidfx4lIy8/E4EKRJCUk= X-Endpoint-Received: by B4 Relay for dang.huynh@mainlining.org/20250917 with auth_id=526 X-Original-From: Dang Huynh Reply-To: dang.huynh@mainlining.org From: Dang Huynh Enable RDA8810PL Clock and Reset driver so we can use it for various subsystems. Signed-off-by: Dang Huynh --- arch/arm/boot/dts/unisoc/rda8810pl.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/unisoc/rda8810pl.dtsi b/arch/arm/boot/dts/un= isoc/rda8810pl.dtsi index 45a2fd3e04cea5aac4fb6b40a6b332ce3eee4f2c..1f7a6908d68367441e5dc865216= cc7a5c39feb35 100644 --- a/arch/arm/boot/dts/unisoc/rda8810pl.dtsi +++ b/arch/arm/boot/dts/unisoc/rda8810pl.dtsi @@ -8,6 +8,7 @@ =20 #include #include +#include =20 / { compatible =3D "rda,8810pl"; @@ -79,6 +80,13 @@ apb@20900000 { #size-cells =3D <1>; ranges =3D <0x0 0x20900000 0x100000>; =20 + ap_syscon: syscon@0 { + compatible =3D "rda,8810pl-apsyscon", "syscon"; + reg =3D <0x0 0x1000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + timer@10000 { compatible =3D "rda,8810pl-timer"; reg =3D <0x10000 0x1000>; --=20 2.51.0 From nobody Thu Oct 2 13:03:51 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0EB62323F50; Tue, 16 Sep 2025 20:25:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054326; cv=none; b=bhM5otBzaWRfYLUFTHFHVnXuvlrd3ys/DC92mQM2ghdo0et6HDrDHVsAx6ROul2djZAhinaXU+2fId8ioP4WMmaZdtA9P2M81B/gwIS0ruaN8YG84EPO0F7cgdU02NyOnlPF6VXd9z8Zi9xX94zvS1kr2OhJhLipjoJas+r+JZA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054326; c=relaxed/simple; bh=RDpCXuNwW3F3KJj6jQvBGASBrt12FmdgYBI4SvuFthg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FU8dUSPqMjOw9Z+yOYM+sFMjO6bfznfRgE16yTB5/5jCa6GOBBVxpqi/YpG1U6AzD9E9sicnWu7hptoXcHs8EC8STnsWfpInflWYV/y46yE6jFJs3M+ZRoYG6fmeN29lSOW/PNuTMd4GZPMFOuHTx9pVlatU6RMwfPsDlVlCt9Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=VxzdsYVH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VxzdsYVH" Received: by smtp.kernel.org (Postfix) with ESMTPS id A4A68C2BC86; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758054325; bh=RDpCXuNwW3F3KJj6jQvBGASBrt12FmdgYBI4SvuFthg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=VxzdsYVHyAvZMHPfARysp6GnpbZGKIKAOSLH+/pcWfrhLRvw8CZeX4KnHfb/K1tX9 LE82efrF2Fjxu3Fm/sD4iY5MI7Wqc7UEtrvz1mLbEtH/XNk6rIq7pFvjGXbqCjK//L nmMILf+OnZr6N/2F8f6DxmpoB68iWmkv2PZeNTuLKlyOA8JUcjAl4E2iaZzzzIqc7h l1GZGUn9BySXjQjcz92UWO1Eqp/7V4O1olgW1jJEdBu/c9dIAKtxd2gMrfmsuAqkjf L+kNV8bLWAu5gdX1uA3wymb1CkPqnBtu5MtUbnGeXEaJ5vRKoZEMk+wVUeCAVyqxsl t9yao+8SSno0w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9CE81CAC5A0; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) From: Dang Huynh via B4 Relay Date: Wed, 17 Sep 2025 03:25:09 +0700 Subject: [PATCH 12/25] dts: unisoc: rda8810pl: Add OPP for CPU and define L2 cache Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-rda8810pl-drivers-v1-12-9ca9184ca977@mainlining.org> References: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> In-Reply-To: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> To: Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Alexandre Belloni , Michael Turquette , Stephen Boyd , Philipp Zabel , Sebastian Reichel , Vinod Koul , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, dmaengine@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mmc@vger.kernel.org, Dang Huynh X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758054322; l=1899; i=dang.huynh@mainlining.org; s=20250917; h=from:subject:message-id; bh=GGuxO6sraElHWuAQ/FHMGYb5YyRNyQdi3IohZFnJO8o=; b=45yf1gKixsaK1bkMYGoKRUqzU4uJvxee7LDvXHPDAXh0W7cXAZpeAuF2mOgWJyZNK24hfZKsM GIqqJqEHIYuDn891fKiP8cE0LCeJJW/uSiFgTzEbed0Tkmppo8BGIdV X-Developer-Key: i=dang.huynh@mainlining.org; a=ed25519; pk=RyzH4CL4YU/ItXYUurA51EVBidfx4lIy8/E4EKRJCUk= X-Endpoint-Received: by B4 Relay for dang.huynh@mainlining.org/20250917 with auth_id=526 X-Original-From: Dang Huynh Reply-To: dang.huynh@mainlining.org From: Dang Huynh Add available frequency table came from downstream kernel, this ensures that the CPU clock can be dynamically tuned. Signed-off-by: Dang Huynh --- arch/arm/boot/dts/unisoc/rda8810pl.dtsi | 52 +++++++++++++++++++++++++++++= ++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm/boot/dts/unisoc/rda8810pl.dtsi b/arch/arm/boot/dts/un= isoc/rda8810pl.dtsi index 1f7a6908d68367441e5dc865216cc7a5c39feb35..299b29e4df6e0a04c5769a568eb= a73ed1684a9e5 100644 --- a/arch/arm/boot/dts/unisoc/rda8810pl.dtsi +++ b/arch/arm/boot/dts/unisoc/rda8810pl.dtsi @@ -16,6 +16,54 @@ / { #address-cells =3D <1>; #size-cells =3D <1>; =20 + /* + * There are two frequency table for CPU. + * + * "High" table is used when operating in normal mode + * "Low" table is used when operating in power saving mode + */ + cpu_high_opp_table: opp-table-0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-329333333 { + opp-hz =3D /bits/ 64 <329333333>; + }; + + opp-395200000 { + opp-hz =3D /bits/ 64 <395200000>; + }; + + opp-494000000 { + opp-hz =3D /bits/ 64 <494000000>; + }; + + opp-988000000 { + opp-hz =3D /bits/ 64 <988000000>; + }; + }; + + cpu_low_opp_table: opp-table-1 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-266666666 { + opp-hz =3D /bits/ 64 <266666666>; + }; + + opp-320000000 { + opp-hz =3D /bits/ 64 <320000000>; + }; + + opp-400000000 { + opp-hz =3D /bits/ 64 <400000000>; + }; + + opp-800000000 { + opp-hz =3D /bits/ 64 <800000000>; + }; + }; + cpus { #address-cells =3D <1>; #size-cells =3D <0>; @@ -24,6 +72,10 @@ cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a5"; reg =3D <0x0>; + next-level-cache =3D <&l2>; + + clocks =3D <&ap_syscon CLK_CPU>; + operating-points-v2 =3D <&cpu_high_opp_table>; }; }; =20 --=20 2.51.0 From nobody Thu Oct 2 13:03:51 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10D89323F55; Tue, 16 Sep 2025 20:25:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054326; cv=none; b=nYwxg36+U1SMLUIO3Mrof3SdC0Mzdx6ZbebavWr8NRKC+563u1TUeHFi3XioSDbyuYTUN+WbSkqzcgQB5Y59UALW68u3i5LJw8T+2TnsM+yFJaEyapIyd8SwJhIdZrcjoiT/vOw1TdEmlUxJrwn0ycR8e9tAYw61OkstslP4NAU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054326; c=relaxed/simple; bh=Czlyuawt5NCDFtRIIQsXB+M6g7mpoAg3GuJazRPrBeI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qSbqwDn4saIo0Cfi48RVcHJffkQNcYGlPwrj3sE4r8gclMzaMM96SSQmnPwbeFJZnhFhfDOluXYXTQ1GPOwMT489H69zJEyiYz/bSzv9XcuakcnROoUAyK9ecoD5Hq7EfPR8ZfOCOywy0thrI3Lr448HL8F/tQbDTxmGRG9X4CA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Hf7kCTiO; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Hf7kCTiO" Received: by smtp.kernel.org (Postfix) with ESMTPS id B5992C4CEF7; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758054325; bh=Czlyuawt5NCDFtRIIQsXB+M6g7mpoAg3GuJazRPrBeI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Hf7kCTiORGTrm++NtElPg+BLvT/tPCYisK3L/uNUGqwouBOJH5KqTtG77kVaKuPlv wZJ1tVfBM+oD739xcpDYDCm0BfU/eDAXJtAwN6cHwz9XToI3Pi4NvC01sA9V6vN6Sy Hjav5hHyCHxfiBa5chtv4H0ACWzUGO9z9TWLBzYUW2h35Oh+c+1csTW9nEDhF8LQ5K 6o8xc0/nkiRGA5ZEIldbknzWtd5+v/Kx7snPjIgIPGEp8KcQEJeHds/KUDKRF1xvRd UI8qqvf17+peTy8L8rjLkGAdBlmYwPHtCP01ycoS8dOCdVzmK/J4uB3WwIH8VY+3OL 3Byo5FzCSJn6Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA26DCAC592; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) From: Dang Huynh via B4 Relay Date: Wed, 17 Sep 2025 03:25:10 +0700 Subject: [PATCH 13/25] dts: unisoc: orangepi: Disable UART with no users Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-rda8810pl-drivers-v1-13-9ca9184ca977@mainlining.org> References: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> In-Reply-To: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> To: Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Alexandre Belloni , Michael Turquette , Stephen Boyd , Philipp Zabel , Sebastian Reichel , Vinod Koul , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, dmaengine@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mmc@vger.kernel.org, Dang Huynh X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758054322; l=1477; i=dang.huynh@mainlining.org; s=20250917; h=from:subject:message-id; bh=XPO5kEJS5ocnBL76vZ0w5j7Lye5wuRkS9bNnKxmO9oo=; b=2zBM9XKo6rOYbZUNQpD9eFH0E5hNGPLBqV3M7IJCdwPx3vmKRrOd+pPLTcttmUftfCu1MJTme +esbSs3Nw5mA0QSS7+wm41hH4xrahHriqA1Ce8uMeTupFJtX3yQzKCr X-Developer-Key: i=dang.huynh@mainlining.org; a=ed25519; pk=RyzH4CL4YU/ItXYUurA51EVBidfx4lIy8/E4EKRJCUk= X-Endpoint-Received: by B4 Relay for dang.huynh@mainlining.org/20250917 with auth_id=526 X-Original-From: Dang Huynh Reply-To: dang.huynh@mainlining.org From: Dang Huynh By default, we should keep unused peripherals disabled. Signed-off-by: Dang Huynh --- arch/arm/boot/dts/unisoc/rda8810pl-orangepi-2g-iot.dts | 10 ---------- arch/arm/boot/dts/unisoc/rda8810pl-orangepi-i96.dts | 10 ---------- 2 files changed, 20 deletions(-) diff --git a/arch/arm/boot/dts/unisoc/rda8810pl-orangepi-2g-iot.dts b/arch/= arm/boot/dts/unisoc/rda8810pl-orangepi-2g-iot.dts index 98e34248ae80b1fcd673ff01fe045db412d5bcc9..46ccb9ad510c0df142b845d6fc5= 633b69c2298dd 100644 --- a/arch/arm/boot/dts/unisoc/rda8810pl-orangepi-2g-iot.dts +++ b/arch/arm/boot/dts/unisoc/rda8810pl-orangepi-2g-iot.dts @@ -34,16 +34,6 @@ uart_clk: uart-clk { }; }; =20 -&uart1 { - status =3D "okay"; - clocks =3D <&uart_clk>; -}; - -&uart2 { - status =3D "okay"; - clocks =3D <&uart_clk>; -}; - &uart3 { status =3D "okay"; clocks =3D <&uart_clk>; diff --git a/arch/arm/boot/dts/unisoc/rda8810pl-orangepi-i96.dts b/arch/arm= /boot/dts/unisoc/rda8810pl-orangepi-i96.dts index 728f76931b995fdfc036b586f899b15a7f07528b..a1d61ef138d12bb3ecb4b24513c= c1a7dfbac3107 100644 --- a/arch/arm/boot/dts/unisoc/rda8810pl-orangepi-i96.dts +++ b/arch/arm/boot/dts/unisoc/rda8810pl-orangepi-i96.dts @@ -34,16 +34,6 @@ uart_clk: uart-clk { }; }; =20 -&uart1 { - status =3D "okay"; - clocks =3D <&uart_clk>; -}; - -&uart2 { - status =3D "okay"; - clocks =3D <&uart_clk>; -}; - &uart3 { status =3D "okay"; clocks =3D <&uart_clk>; --=20 2.51.0 From nobody Thu Oct 2 13:03:51 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 714F432B49D; Tue, 16 Sep 2025 20:25:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054326; cv=none; b=KhnFjeKDOZOl4W/Mm/VwolAXJvmdaO8ANVBK/cnj+i+ng3fhMCkEtKN9HWBtqiJjgMwOiuJMLHFSv7gzkxA9doaCg18uNciBlaZOuXTdYqG4+A3TaKKh1gWbsO//XQdqSM5LpyLO023dYb51zOmnISvCAUDAeu9LcQ/Y19QLy8Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054326; c=relaxed/simple; bh=EegadZyE2ka3lqNPNKWfrSgt+VjG3SDvPe99w5hVinc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hKOMUkGlmPXVfj9/+wJF06OdLomHvQwpltA/jwpuL86gzXAnFdRoz0+2b7cKk368oGJEFLfZ5QjeTjqE+/l6vC5O2r85DJ6OOj4zRiHkWHN2VvKPL8ivYeLPFXmhU62hR4BI3nACXYPoDftM74IbG4cfmnS9Nld0T/jmQpkLfvw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TqjJmG2A; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TqjJmG2A" Received: by smtp.kernel.org (Postfix) with ESMTPS id C537FC2BCC6; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758054325; bh=EegadZyE2ka3lqNPNKWfrSgt+VjG3SDvPe99w5hVinc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=TqjJmG2A2cB8ngo4ajZYfJfPMOULRsF5fOoBAUEkiwgNY4F+FZ8BLxj7ewB+GWcz0 nCkyo4BZtNjh80Z1IoBu2Y5ocJGUGVMU0DqkV0nMKQGm/rUmk0yVMrYCbpXue27U6Z oktZfW0Qg1zrv3ndCM3+dY+9U+RyBpYOGU1iRPem8jfqa7hCKxFVY54M9u7h6xheDX dlvUQBNj8nUtlBaTWbIdhOtUBnlxn75aAGQFpCJYHW1BnnxYVFJ++IBJfPRvxLvGs+ IfmyJ/v9X67Ke2B79rvjVMcyoDKN1kp8N61hTJOC+szpM94zN1FmGX11jZSi+GODFL xEU2XYSFcDWKg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B989BCAC59F; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) From: Dang Huynh via B4 Relay Date: Wed, 17 Sep 2025 03:25:11 +0700 Subject: [PATCH 14/25] dt-bindings: power: reset: Add RDA Micro Modem Reset Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-rda8810pl-drivers-v1-14-9ca9184ca977@mainlining.org> References: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> In-Reply-To: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> To: Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Alexandre Belloni , Michael Turquette , Stephen Boyd , Philipp Zabel , Sebastian Reichel , Vinod Koul , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, dmaengine@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mmc@vger.kernel.org, Dang Huynh X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758054322; l=1439; i=dang.huynh@mainlining.org; s=20250917; h=from:subject:message-id; bh=Qx3A0YEz2hiOBr1X7Hx7B2Yur/VncHTnIWLD5/fTYjI=; b=ZgRTCdZsa4zMPNeOMmGFLo6ICngX1GwmdnktW4A702PqmzxT6psP5W8kdNHEKlVW88+WFP8Gv ElMMuGq68W5A4Nx++rKEmZFCTm3eK1x3SrQ1TYSmUBZhC4BLDLaBhGC X-Developer-Key: i=dang.huynh@mainlining.org; a=ed25519; pk=RyzH4CL4YU/ItXYUurA51EVBidfx4lIy8/E4EKRJCUk= X-Endpoint-Received: by B4 Relay for dang.huynh@mainlining.org/20250917 with auth_id=526 X-Original-From: Dang Huynh Reply-To: dang.huynh@mainlining.org From: Dang Huynh Add documentation describing the RDA Micro modem reset controller Signed-off-by: Dang Huynh --- .../bindings/power/reset/rda,md-reset.yaml | 36 ++++++++++++++++++= ++++ 1 file changed, 36 insertions(+) diff --git a/Documentation/devicetree/bindings/power/reset/rda,md-reset.yam= l b/Documentation/devicetree/bindings/power/reset/rda,md-reset.yaml new file mode 100644 index 0000000000000000000000000000000000000000..6d09bc8ee6b257aec9d2c4738d2= 85490044003ea --- /dev/null +++ b/Documentation/devicetree/bindings/power/reset/rda,md-reset.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/reset/rda,md-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RDA Micro Modem Reset + +maintainers: + - Dang Huynh + +description: + The modem has a reset register that can be used to fully reset the board. + + To do that, a magic value needs to be written to unprotect the register, + then the soft reset register can be used. + +properties: + compatible: + const: rda,md-reset + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + reset-controller@1a00000 { + compatible =3D "rda,md-reset"; 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Tue, 16 Sep 2025 20:25:25 +0000 (UTC) From: Dang Huynh via B4 Relay Date: Wed, 17 Sep 2025 03:25:12 +0700 Subject: [PATCH 15/25] power: reset: Add basic power reset driver for RDA8810PL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-rda8810pl-drivers-v1-15-9ca9184ca977@mainlining.org> References: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> In-Reply-To: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> To: Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Alexandre Belloni , Michael Turquette , Stephen Boyd , Philipp Zabel , Sebastian Reichel , Vinod Koul , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, dmaengine@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mmc@vger.kernel.org, Dang Huynh X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758054322; l=4260; i=dang.huynh@mainlining.org; s=20250917; h=from:subject:message-id; bh=HFlkcuGoP8mh0AtLbkenNjV8o+UREGJUxRrmMlpYY+8=; b=tDnwi027u0ZztdCHk9SEr/lKN0wXoeRqVTLuHk786MC7CkCmAPImsXjgN/ULbHg//6qHti8x6 8cGQKoU4pBQCo0nPOwWFQeuoR0ZX1cppWJGWEFpFHKUyjOi/YBYx5Y2 X-Developer-Key: i=dang.huynh@mainlining.org; a=ed25519; pk=RyzH4CL4YU/ItXYUurA51EVBidfx4lIy8/E4EKRJCUk= X-Endpoint-Received: by B4 Relay for dang.huynh@mainlining.org/20250917 with auth_id=526 X-Original-From: Dang Huynh Reply-To: dang.huynh@mainlining.org From: Dang Huynh This basic driver can only reboot, powering off requires the modem firmware which we don't have yet. Signed-off-by: Dang Huynh --- MAINTAINERS | 6 +++++ drivers/power/reset/Kconfig | 9 +++++++ drivers/power/reset/Makefile | 1 + drivers/power/reset/rda-reboot.c | 58 ++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 74 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index cbe2ab8af6dcd40dd1456d9df55673dace3c87b2..5ec24d8657bffb55c160947a930= 980e428c6a6b7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21399,6 +21399,12 @@ S: Maintained F: Documentation/devicetree/bindings/clock/rda,8810pl-apsyscon.yaml F: drivers/clk/rda/clk-rda8810.c =20 +RDA MICRO MODEM RESET DRIVER +M: Dang Huynh +S: Maintained +F: Documentation/devicetree/bindings/power/reset/rda,md-reset.yaml +F: drivers/power/reset/rda-reboot.c + RDA MICRO REAL TIME CLOCK DRIVER M: Dang Huynh S: Maintained diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig index 77ea3129c70806929f3c248667db42f05f5f1d27..de9b1afb94d14a5d23286ddb302= af4107d649c12 100644 --- a/drivers/power/reset/Kconfig +++ b/drivers/power/reset/Kconfig @@ -205,6 +205,15 @@ config POWER_RESET_QNAP =20 Say Y if you have a QNAP NAS. =20 +config POWER_RESET_RDA + bool "RDA Micro Reset Driver" + depends on ARCH_RDA + help + This driver supports soft resetting RDA Micro boards by writing + magic values to the modem register. + + Say Y if you have a board with RDA Micro SoC. + config POWER_RESET_REGULATOR bool "Regulator subsystem power-off driver" depends on OF && REGULATOR diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile index b7c2b5940be9971548a5527384d1931abff11c4c..14371230410dad2852489160f4f= c23d8fd087d6e 100644 --- a/drivers/power/reset/Makefile +++ b/drivers/power/reset/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_POWER_RESET_ODROID_GO_ULTRA_POWEROFF) +=3D o= droid-go-ultra-poweroff.o obj-$(CONFIG_POWER_RESET_PIIX4_POWEROFF) +=3D piix4-poweroff.o obj-$(CONFIG_POWER_RESET_LTC2952) +=3D ltc2952-poweroff.o obj-$(CONFIG_POWER_RESET_QNAP) +=3D qnap-poweroff.o +obj-$(CONFIG_POWER_RESET_RDA) +=3D rda-reboot.o obj-$(CONFIG_POWER_RESET_REGULATOR) +=3D regulator-poweroff.o obj-$(CONFIG_POWER_RESET_RESTART) +=3D restart-poweroff.o obj-$(CONFIG_POWER_RESET_ST) +=3D st-poweroff.o diff --git a/drivers/power/reset/rda-reboot.c b/drivers/power/reset/rda-reb= oot.c new file mode 100644 index 0000000000000000000000000000000000000000..d87b063ba67d847f8e869e50a6c= 01427b2866889 --- /dev/null +++ b/drivers/power/reset/rda-reboot.c @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025, Dang Huynh + * + * Based on drivers/power/reset/msm-poweroff.c: + * Copyright (c) 2013, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void __iomem *rda_md_sysctrl; + +static int do_rda_reboot(struct sys_off_data *data) +{ + /* unprotect md registers */ + writel(0x00A50001, rda_md_sysctrl); + + /* reset all */ + writel(0x80000000, rda_md_sysctrl + 4); + + return NOTIFY_DONE; +} + +static int rda_reboot_probe(struct platform_device *pdev) +{ + rda_md_sysctrl =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(rda_md_sysctrl)) + return PTR_ERR(rda_md_sysctrl); + + devm_register_sys_off_handler(&pdev->dev, SYS_OFF_MODE_RESTART, + 128, do_rda_reboot, NULL); + + return 0; +} + +static const struct of_device_id of_rda_reboot_match[] =3D { + { .compatible =3D "rda,md-reset", }, + {}, +}; +MODULE_DEVICE_TABLE(of, of_rda_reboot_match); + +static struct platform_driver rda_reboot_driver =3D { + .probe =3D rda_reboot_probe, + .driver =3D { + .name =3D "rda-reboot", + .of_match_table =3D of_match_ptr(of_rda_reboot_match), + }, +}; +builtin_platform_driver(rda_reboot_driver); --=20 2.51.0 From nobody Thu Oct 2 13:03:51 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 30134323F7F; Tue, 16 Sep 2025 20:25:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054326; cv=none; b=IL5xNR+e4IE9hDsyag+W9OMsli5LZduqYJoj6QDL9I2dYct+c2lvwWLAJgGaHKEN/fFiMjNzuOZcqrCj9+/eT0atVDsTxl13Or9iMmvfb7i4flDUctWOwfVwN3SiBjvhDAlN7Zuie+uETA8MH31xTesvh0eTmu018aYA53Yf5T0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054326; c=relaxed/simple; bh=Pnv5+FFv2iFRwSYEkairmz1Zl0wNKr5bOgIcKGaNzuQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PROsETQdDEP/ZTBRtzgQxE8vKjoDrEwIYbwAbC/wsRhPanfs8t2fBDXCc7QTfxZwvuIdG9NoKFLTEsT6fSEJAhpZuULnt7yg9p8+SqR2sPpLfTAE2j2cwgvbVUdYCgrTzFy3zz6m7vrFcyxZpWoFPeUZ5gcijdDwpEbNgW9R2H0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=q/zXKcbU; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="q/zXKcbU" Received: by smtp.kernel.org (Postfix) with ESMTPS id E01F1C2BCAF; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758054326; bh=Pnv5+FFv2iFRwSYEkairmz1Zl0wNKr5bOgIcKGaNzuQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=q/zXKcbUevPgRlaTCib4V5P98tSX76eBivNWx8aALG6g89LwXwdkOWDEtegJwP8o5 tGfCaRb0U5ehZav9v3RBQ8a3F6v00Zil3B+e5QxFJvA8wxp+9zezYEkgBIZjHSFy// WxzBFP3wIRZUpqfzQKWHq+MlptIZIQ81WW5jbFBOVoSZjKEtC+FpicXBwVQxmgklOq r+7BVAXDyZa04CezBiVjDhAW0IVidoO2vqy+5dFINzxuez83g05w7TunPbBDZX8V5G r9Yfyj6s/+FbjdJgO011hEw30hU/ez+Uj//nbHpf6OAIgZsP8W12J3E5bp1cAKDK+f eGUK2k4pZiWYQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D625FCAC592; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) From: Dang Huynh via B4 Relay Date: Wed, 17 Sep 2025 03:25:13 +0700 Subject: [PATCH 16/25] dts: unisoc: rda8810pl: Enable modem reset Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-rda8810pl-drivers-v1-16-9ca9184ca977@mainlining.org> References: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> In-Reply-To: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> To: Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Alexandre Belloni , Michael Turquette , Stephen Boyd , Philipp Zabel , Sebastian Reichel , Vinod Koul , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, dmaengine@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mmc@vger.kernel.org, Dang Huynh X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758054322; l=793; i=dang.huynh@mainlining.org; s=20250917; h=from:subject:message-id; bh=u8ofUfZnyL6AGUSAsraDhXZ8KtNj+jiTPktMzMifzHg=; b=fWZT1Fx32Hx9ZahhNzlPhngPS7qH4nNWfABkCpfT5wJanor1eQSweXur3kGePA0KRJvMK5TAB H8UQagjuGEgAjgojs4svCTAlHhh0Ir2INO/LHEgYgExeaecrkrYKpEG X-Developer-Key: i=dang.huynh@mainlining.org; a=ed25519; pk=RyzH4CL4YU/ItXYUurA51EVBidfx4lIy8/E4EKRJCUk= X-Endpoint-Received: by B4 Relay for dang.huynh@mainlining.org/20250917 with auth_id=526 X-Original-From: Dang Huynh Reply-To: dang.huynh@mainlining.org From: Dang Huynh This allows us to reboot the board from the OS. Signed-off-by: Dang Huynh --- arch/arm/boot/dts/unisoc/rda8810pl.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/unisoc/rda8810pl.dtsi b/arch/arm/boot/dts/un= isoc/rda8810pl.dtsi index 299b29e4df6e0a04c5769a568eba73ed1684a9e5..e90ae7845de7b79e55e9cd339a8= 2313b423e0252 100644 --- a/arch/arm/boot/dts/unisoc/rda8810pl.dtsi +++ b/arch/arm/boot/dts/unisoc/rda8810pl.dtsi @@ -98,6 +98,11 @@ modem@10000000 { #size-cells =3D <1>; ranges =3D <0x0 0x10000000 0xfffffff>; =20 + reset-controller@1a00000 { + compatible =3D "rda,md-reset"; + reg =3D <0x1a00000 0x4>; + }; + rtc@1a06000 { compatible =3D "rda,8810pl-rtc"; reg =3D <0x1a06000 0x1000>; --=20 2.51.0 From nobody Thu Oct 2 13:03:51 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52FF5329517; Tue, 16 Sep 2025 20:25:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054326; cv=none; b=rT86lOI6LpYAFLunUy/1d1GKTcwGRfFa2GINpbyyt1w5H2fZCmW45ZQD8EDZ2O47jEyrpUUpONsJofax6P0rVA2tC9VNEa0odr2zxXaBr0PuYFSju1PZcaem8G+BY5NuNTchhxZV3S1o6Yaw3soFsyRXDkDAkPbs4nmIEyTL5EM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054326; c=relaxed/simple; bh=4w6w5DvzwFyRo2J5VW1szw6dNb6N2JHLDo922TOLKcY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=u1hwfgYEklAeFrJpd7p3n3LG0m006FMmPVOC9oz/lqqP2l6d6JGg1rs+DqQlKwOfiMwdJcXSWcZATwbWyKKjIx1w59PvREE/WcBbZFOcqKhKQd/SkSbxObSx66EVfInyVNhenJfKw8GoGE0WbqtIxpBvOhlYUEsBq+0lD2pCh6E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Ma/CpcuB; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Ma/CpcuB" Received: by smtp.kernel.org (Postfix) with ESMTPS id 06C12C4CEFF; Tue, 16 Sep 2025 20:25:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758054326; bh=4w6w5DvzwFyRo2J5VW1szw6dNb6N2JHLDo922TOLKcY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Ma/CpcuBYVrPPjn8B5wDIMdK5MXsxC8Lgs9ueMxl7S9NVceWGjbSNc7QoFAQv10rw ur8thkyVEuWGBCwwlKeyC5KZgjl9wxNhj3R6IwTEvmVNsQZyNMyoU8MQZmRpPCksfw u05SWxcjEx103cFljCepFq6Kvns6i73kSrEQ3jWll+9HbQOi99pXQOCatoK5wv1uI2 O9m/FAv5Fbzdw36thgv1deL2EunYU468a9Aoqyj3a+vDSTZOqGF7BayMtXkucCkP4o fKED/ROmSfgdNe/+KuXzbSxjjUCmBMUByFUbEtRoX8gYqQxoH06n2UWVySlp2i9PnT OvlQZq5LjZY2Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4FA4CAC5A0; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) From: Dang Huynh via B4 Relay Date: Wed, 17 Sep 2025 03:25:14 +0700 Subject: [PATCH 17/25] drivers: gpio: rda: Make direction register unreadable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-rda8810pl-drivers-v1-17-9ca9184ca977@mainlining.org> References: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> In-Reply-To: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> To: Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Alexandre Belloni , Michael Turquette , Stephen Boyd , Philipp Zabel , Sebastian Reichel , Vinod Koul , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, dmaengine@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mmc@vger.kernel.org, Dang Huynh X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758054322; l=890; i=dang.huynh@mainlining.org; s=20250917; h=from:subject:message-id; bh=Ej4sfxzJ/Gsg0f6d9t0Id5MGonhTVkngeFDG/IpOGqc=; b=7/dQ+zSEH7UofRPjo+bKlBs6ViTT+WuJvSx4Gecx+bo6BYwM3Re5lMQKArpXET7WxhoCPOvfe Rk52QJ6IW9cA55W805ijHTkhu0687ofj0g1SAA1xQxJl5AhXuzcWLTL X-Developer-Key: i=dang.huynh@mainlining.org; a=ed25519; pk=RyzH4CL4YU/ItXYUurA51EVBidfx4lIy8/E4EKRJCUk= X-Endpoint-Received: by B4 Relay for dang.huynh@mainlining.org/20250917 with auth_id=526 X-Original-From: Dang Huynh Reply-To: dang.huynh@mainlining.org From: Dang Huynh The register doesn't like to be read, this causes the SD Card Card Detect GPIO to misbehaves in the OS. Signed-off-by: Dang Huynh --- drivers/gpio/gpio-rda.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-rda.c b/drivers/gpio/gpio-rda.c index b4db8553a2371ae407fdb7e681d0f82c4d9f74b7..56aaa9f33d29469dfb1bf86ed7b= 63c54b413c89c 100644 --- a/drivers/gpio/gpio-rda.c +++ b/drivers/gpio/gpio-rda.c @@ -245,7 +245,7 @@ static int rda_gpio_probe(struct platform_device *pdev) .clr =3D rda_gpio->base + RDA_GPIO_CLR, .dirout =3D rda_gpio->base + RDA_GPIO_OEN_SET_OUT, .dirin =3D rda_gpio->base + RDA_GPIO_OEN_SET_IN, - .flags =3D BGPIOF_READ_OUTPUT_REG_SET, + .flags =3D BGPIOF_READ_OUTPUT_REG_SET | BGPIOF_UNREADABLE_REG_DIR, }; =20 ret =3D gpio_generic_chip_init(&rda_gpio->chip, &config); --=20 2.51.0 From nobody Thu Oct 2 13:03:51 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 466A93294F8; Tue, 16 Sep 2025 20:25:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054326; cv=none; b=WiXkg02pcQirYjETBI1ITRBYyQ3iEHDGHUurD65N++xxEEKYZH//M2/Hy/GpvHIiU7WlIb3acBqf7wIU5Vqv39IdOCw72jfbjAaW4KmnD/FFh7RZndh4UCLGTrNUXQCcBTNmGUwupq2i3QuEX1vAotLa3KntOKJ8kPcxVRRSVvU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054326; c=relaxed/simple; bh=B44iCTmbdkKyp2fHglpeuA0FgGRACa5ozdrUyEJewhg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XuEYNpXK7zK/j1FCtwSn5vFVQexyeaypmCZ8p1edvz4DYDUXLM1N6xqIUat/+6JFvO8L//HmMrPCwVhFnjh7SAqxgM0OiGS0GXSCAqo9eQD6v4nKAB9zjAbtbdP2ZqjdqBmIUTAZfEiF3ZTCBRoFDpXhhPR364dTx7/tQTkRynE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NAEBA1y1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NAEBA1y1" Received: by smtp.kernel.org (Postfix) with ESMTPS id 0A674C4AF09; Tue, 16 Sep 2025 20:25:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758054326; bh=B44iCTmbdkKyp2fHglpeuA0FgGRACa5ozdrUyEJewhg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=NAEBA1y1K4tD/khRpZK6HkipNJr1YfntYnA1W8a1MzEjPiEZDlIUbUrvu6Vu+pe0p dE4zzG04EM+hdn+JeTZRE7swY4dzT+d3zaZlfXt1w080wMyHCp0vmyNmcQfp1EpRk4 +M5cgboJT5xIC7A1o9d3niTws0pIR9ymJ32HRLpSvJHNUrZoq77nijq2oVbdqcCnFX 18h9UHBn499TLmGp8F2huiSkDw3kNFZHs2OGD4zQ9TR7ELKLZlLg2bYtnrgFtG4mkE PjuOKrBP49md3posUyZxios2JUQ0yCVcmx4UwALtpQvdrA7nF/kp1Haj/rVzLgd/N6 8HwSnuIEXZLzw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3DD7CAC59F; Tue, 16 Sep 2025 20:25:25 +0000 (UTC) From: Dang Huynh via B4 Relay Date: Wed, 17 Sep 2025 03:25:15 +0700 Subject: [PATCH 18/25] dt-bindings: dma: Add RDA IFC DMA Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-rda8810pl-drivers-v1-18-9ca9184ca977@mainlining.org> References: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> In-Reply-To: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> To: Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Alexandre Belloni , Michael Turquette , Stephen Boyd , Philipp Zabel , Sebastian Reichel , Vinod Koul , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, dmaengine@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mmc@vger.kernel.org, Dang Huynh X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758054322; l=2537; i=dang.huynh@mainlining.org; s=20250917; h=from:subject:message-id; bh=QY6MPTi+ZEpXp5sbdSrBjaqgS0Xhdu1ZPCH1WF+g14Y=; b=f+73zCYT5uq1k6ilgLXi33C+NRy7J+fTOa4N/swr6XCdLJaXbG/yOKqpUhJI3D/PqTqY8XU0k QkM4vE+PJ/5Cn0iUPmzJgeqVeko3jz25IKQyFfbLa/CoguJ6psdmMSc X-Developer-Key: i=dang.huynh@mainlining.org; a=ed25519; pk=RyzH4CL4YU/ItXYUurA51EVBidfx4lIy8/E4EKRJCUk= X-Endpoint-Received: by B4 Relay for dang.huynh@mainlining.org/20250917 with auth_id=526 X-Original-From: Dang Huynh Reply-To: dang.huynh@mainlining.org From: Dang Huynh The Intelligent Flow Controller (IFC) is a scatter/gather DMA controller. Signed-off-by: Dang Huynh --- Documentation/devicetree/bindings/dma/rda,ifc.yaml | 42 ++++++++++++++++++= ++++ include/dt-bindings/dma/rda-ifc.h | 28 +++++++++++++++ 2 files changed, 70 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/rda,ifc.yaml b/Documenta= tion/devicetree/bindings/dma/rda,ifc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..3bb5932e8ff9404e3980eaef607= efceb6d883bda --- /dev/null +++ b/Documentation/devicetree/bindings/dma/rda,ifc.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/rda,ifc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RDA Intelligent Flow Controller (IFC) + +maintainers: + - Dang Huynh + +description: | + RDA IFC is a DMA controller, it only supports scatter/gather lists. + +allOf: + - $ref: dma-controller.yaml# + +properties: + compatible: + const: rda,8810pl-ifc + + reg: + maxItems: 1 + + "#dma-cells": + const: 1 + description: + The cell corresponding to DMA request ID + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + ifc: dma-controller@f0000 { + compatible =3D "rda,8810pl-ifc"; + reg =3D <0xf0000 0x1000>; + #dma-cells =3D <1>; + }; diff --git a/include/dt-bindings/dma/rda-ifc.h b/include/dt-bindings/dma/rd= a-ifc.h new file mode 100644 index 0000000000000000000000000000000000000000..e075fe26158e834d1ae87b6dce6= 1e41fb931add3 --- /dev/null +++ b/include/dt-bindings/dma/rda-ifc.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ + +#ifndef __DT_BINDINGS_DMA_RDA_IFC_H__ +#define __DT_BINDINGS_DMA_RDA_IFC_H__ + +#define IFC_UART1_TX 0 +#define IFC_UART1_RX 1 +#define IFC_UART2_TX 2 +#define IFC_UART2_RX 3 +#define IFC_SPI1_TX 4 +#define IFC_SPI1_RX 5 +#define IFC_SPI2_TX 6 +#define IFC_SPI2_RX 7 +#define IFC_SPI3_TX 8 +#define IFC_SPI3_RX 9 +#define IFC_SDMMC1_TX 10 +#define IFC_SDMMC1_RX 11 +#define IFC_SDMMC2_TX 12 +#define IFC_SDMMC2_RX 13 +#define IFC_SDMMC3_TX 14 +#define IFC_SDMMC3_RX 15 +#define IFC_NFSC_TX 16 +#define IFC_NFSC_RX 17 +#define IFC_UART3_TX 18 +#define IFC_UART3_RX 19 +#define IFC_NO_REQUEST 20 + +#endif /* __DT_BINDINGS_DMA_RDA_IFC_H__ */ --=20 2.51.0 From nobody Thu Oct 2 13:03:51 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54E8332951C; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-rda8810pl-drivers-v1-19-9ca9184ca977@mainlining.org> References: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> In-Reply-To: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> To: Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Alexandre Belloni , Michael Turquette , Stephen Boyd , Philipp Zabel , Sebastian Reichel , Vinod Koul , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, dmaengine@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mmc@vger.kernel.org, Dang Huynh X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758054322; l=14863; i=dang.huynh@mainlining.org; s=20250917; h=from:subject:message-id; bh=ozDiuqCC+FJAxSbuYu88bdo8XSDeudauUyugWzgat2I=; b=CWCkQ8NlveC83jYD1hyWhB+RKZzQYLJ6E78Oh/1vhFi68wtAWQ48Ep9UN8sTTt3v/NEvdvBwQ bhk5+/YMDXxCMaknhlaccidiXXjJK5R/Yo5aGevpKN5jvLv15u3j1gj X-Developer-Key: i=dang.huynh@mainlining.org; a=ed25519; pk=RyzH4CL4YU/ItXYUurA51EVBidfx4lIy8/E4EKRJCUk= X-Endpoint-Received: by B4 Relay for dang.huynh@mainlining.org/20250917 with auth_id=526 X-Original-From: Dang Huynh Reply-To: dang.huynh@mainlining.org From: Dang Huynh IFC stands for Intelligent Flow Control, a scatter/gather DMA controller. Signed-off-by: Dang Huynh --- MAINTAINERS | 6 + drivers/dma/Kconfig | 10 ++ drivers/dma/Makefile | 1 + drivers/dma/rda-ifc.c | 450 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 467 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 5ec24d8657bffb55c160947a930980e428c6a6b7..91be43782f4ba8aacb629002d35= 7a66704f10b2b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21399,6 +21399,12 @@ S: Maintained F: Documentation/devicetree/bindings/clock/rda,8810pl-apsyscon.yaml F: drivers/clk/rda/clk-rda8810.c =20 +RDA MICRO INTELLIGENT FLOW CONTROLLER DRIVER +M: Dang Huynh +S: Maintained +F: Documentation/devicetree/bindings/dma/rda,ifc.yaml +F: drivers/dma/rda-ifc.c + RDA MICRO MODEM RESET DRIVER M: Dang Huynh S: Maintained diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index b8a74b1798ba1d44b26553990428c065de6fc535..4a032acba932b0e8cc17c8e0f15= b9ecafbab210b 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -571,6 +571,16 @@ config PLX_DMA These are exposed via extra functions on the switch's upstream port. Each function exposes one DMA channel. =20 +config RDA_IFC + bool "RDA IFC support" + depends on ARCH_RDA + select DMA_ENGINE + help + Support RDA Intelligent Flow Controller for RDA Micro SoC. + The Intelligent Flow Controller is a scatter/gather DMA controller. + + If unsure, say N. + config SOPHGO_CV1800B_DMAMUX tristate "Sophgo CV1800/SG2000 series SoC DMA multiplexer support" depends on MFD_SYSCON diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index a54d7688392b1a0e956fa5d23633507f52f017d9..40f6c61dcce739f3ffd064fbdc2= 3388cfca83184 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -69,6 +69,7 @@ obj-$(CONFIG_PL330_DMA) +=3D pl330.o obj-$(CONFIG_PLX_DMA) +=3D plx_dma.o obj-$(CONFIG_PPC_BESTCOMM) +=3D bestcomm/ obj-$(CONFIG_PXA_DMA) +=3D pxa_dma.o +obj-$(CONFIG_RDA_IFC) +=3D rda-ifc.o obj-$(CONFIG_RENESAS_DMA) +=3D sh/ obj-$(CONFIG_SF_PDMA) +=3D sf-pdma/ obj-$(CONFIG_SOPHGO_CV1800B_DMAMUX) +=3D cv1800b-dmamux.o diff --git a/drivers/dma/rda-ifc.c b/drivers/dma/rda-ifc.c new file mode 100644 index 0000000000000000000000000000000000000000..ff7f59876a5895fbdc1adf584e1= 1519bcfcfdb11 --- /dev/null +++ b/drivers/dma/rda-ifc.c @@ -0,0 +1,450 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * RDA Micro Intelligent Flow Controller + * + * Copyright (C) 2013 RDA Microelectronics Inc. + * Copyright (C) 2025 Dang Huynh + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "dmaengine.h" + +#include + +/* Registers */ +#define IFC_REG_GET_CH 0x0 +#define IFC_REG_DMA_STATUS 0x4 +#define IFC_REG_DEBUG_STATUS 0x8 + +/* Channel registers */ +#define IFC_REG_SG_CONTROL 0x0 +#define IFC_REG_SG_STATUS 0x4 +#define IFC_REG_SG_START_ADDR 0x8 +#define IFC_REG_SG_TC 0xC + +#define IFC_REG_CH_RFSPI_CONTROL 0x80 +#define IFC_REG_CH_RFSPI_STATUS 0x84 +#define IFC_REG_CH_RFSPI_START_ADDR 0x88 +#define IFC_REG_CH_RFSPI_END_ADDR 0x8C +#define IFC_REG_CH_RFSPI_TC 0x90 + +/* Bits */ +/* DMA_STATUS */ +#define IFC_DMA_CH_ENABLE GENMASK(8, 0) +#define IFC_DMA_CH_BUSY GENMASK(23, 16) +/* DEBUG_STATUS */ +#define IFC_DBG_STATUS BIT(0) +/* CONTROL */ +#define IFC_CTL_ENABLE BIT(0) +#define IFC_CTL_DISABLE BIT(1) +#define IFC_CTL_CH_RD_HW_EXCH BIT(2) +#define IFC_CTL_CH_WR_HW_EXCH BIT(3) +#define IFC_CTL_AUTODISABLE BIT(4) +#define IFC_CTL_SIZE GENMASK(7, 5) /* byte: 0 - halfword: 1 - word: 2 */ +#define IFC_CTL_REQ_SRC GENMASK(15, 8) +#define IFC_CTL_FLUSH BIT(16) +#define IFC_CTL_SG_NUM GENMASK(24, 17) +/* STATUS */ +#define IFC_STATUS_ENABLE BIT(0) +#define IFC_STATUS_FIFO_EMPTY BIT(4) + +/* + * An available IFC channel can be obtained by reading IFC_REG_GET_CH regi= ster, + * if no channel are available the register reads 0xF. + * + * Memory map for each channel (starts at 0x10): + * + * [IFC_REG_SG_CONTROL] + * [IFC_REG_SG_STATUS] + * [IFC_REG_SG_START_ADDR] (1st sg_table) + * [IFC_REG_SG_TC] + * ... + * + * Depends on the hardware, it might support more than one sg table. If it + * does, the next sg table is right next to previous table. + * + * The next channel is right after the memory map above. + * + * The DMA channel MUST be disabled after the transaction is done or some = IP + * might misbehaves. + */ + +struct rda_ifc_chan { + struct rda_ifc *rda_ifc; + void __iomem *chan_base; + spinlock_t lock; + + struct dma_chan chan; + unsigned int request_id; + + enum dma_transfer_direction direction; + struct dma_slave_config sconfig; + struct dma_async_tx_descriptor tx; +}; + +struct rda_ifc { + struct device *dev; + void __iomem *base; + + struct dma_device ddev; + + int sg_max; + int max_chan; + struct rda_ifc_chan channels[] __counted_by(max_chan); +}; + +struct rda_ifc_platinfo { + int sg_max; + int std_channb; +}; + +static struct rda_ifc_chan *to_ifc_chan(struct dma_chan *chan) +{ + return container_of(chan, struct rda_ifc_chan, chan); +} + +static int rda_ifc_device_config(struct dma_chan *chan, struct dma_slave_c= onfig *config) +{ + struct rda_ifc_chan *ifc_chan =3D to_ifc_chan(chan); + + ifc_chan->direction =3D (ifc_chan->request_id & 1) ? DMA_DEV_TO_MEM : DMA= _MEM_TO_DEV; + memcpy(&ifc_chan->sconfig, config, sizeof(*config)); + + return 0; +} + +static void rda_ifc_issue_pending(struct dma_chan *chan) +{ + struct rda_ifc_chan *ifc_chan =3D to_ifc_chan(chan); + unsigned long flags; + u32 control; + + spin_lock_irqsave(&ifc_chan->lock, flags); + + control =3D readl(ifc_chan->chan_base); + control |=3D IFC_CTL_ENABLE; + writel(control, ifc_chan->chan_base); + + spin_unlock_irqrestore(&ifc_chan->lock, flags); +} + +static dma_cookie_t rda_ifc_tx_submit(struct dma_async_tx_descriptor *tx) +{ + return dma_cookie_assign(tx); +} + +static struct dma_async_tx_descriptor *rda_ifc_prep_slave_sg(struct dma_ch= an *chan, + struct scatterlist *sgl, unsigned int sg_len, + enum dma_transfer_direction direction, unsigned long dma_flags, + void *context) +{ + struct rda_ifc_chan *ifc_chan =3D to_ifc_chan(chan); + struct rda_ifc *ifc =3D ifc_chan->rda_ifc; + struct device *dev =3D dmaengine_get_dma_device(chan); + struct scatterlist *sg; + unsigned long flags; + u32 control =3D 0; + int width; + int i; + + if (sg_len > ifc->sg_max) { + dev_err(dev, "sg_len %d overflowed (max sg %d)\n", + sg_len, ifc->sg_max); + return NULL; + } + + if (direction !=3D ifc_chan->direction) { + dev_err(dev, "Inconsistent transfer direction\n"); + return NULL; + } + + spin_lock_irqsave(&ifc_chan->lock, flags); + + if (ifc_chan->direction =3D=3D DMA_DEV_TO_MEM) + width =3D ifc_chan->sconfig.src_addr_width; + else + width =3D ifc_chan->sconfig.dst_addr_width; + + switch (width) { + case DMA_SLAVE_BUSWIDTH_1_BYTE: + control |=3D FIELD_PREP(IFC_CTL_SIZE, 0); + break; + case DMA_SLAVE_BUSWIDTH_2_BYTES: + control |=3D FIELD_PREP(IFC_CTL_SIZE, 1); + break; + case DMA_SLAVE_BUSWIDTH_4_BYTES: + control |=3D FIELD_PREP(IFC_CTL_SIZE, 2); + break; + default: + return NULL; + } + + for_each_sg(sgl, sg, sg_len, i) { + if (!IS_ALIGNED(sg_dma_address(sg), width)) { + dev_err(dev, "Unaligned DMA address\n"); + spin_unlock_irqrestore(&ifc_chan->lock, flags); + return NULL; + } + + writel(sg_dma_address(sg), ifc_chan->chan_base + IFC_REG_SG_START_ADDR += (8 * i)); + writel(sg_dma_len(sg), ifc_chan->chan_base + IFC_REG_SG_TC + (8 * i)); + } + + control |=3D FIELD_PREP(IFC_CTL_REQ_SRC, ifc_chan->request_id) | + IFC_CTL_CH_RD_HW_EXCH | + FIELD_PREP(IFC_CTL_SG_NUM, sg_len-1); + writel(control, ifc_chan->chan_base); + + spin_unlock_irqrestore(&ifc_chan->lock, flags); + + dma_async_tx_descriptor_init(&ifc_chan->tx, chan); + ifc_chan->tx.tx_submit =3D rda_ifc_tx_submit; + + return &ifc_chan->tx; +} + +static enum dma_status rda_ifc_tx_status(struct dma_chan *chan, dma_cookie= _t cookie, + struct dma_tx_state *tx_state) +{ + struct rda_ifc_chan *ifc_chan =3D to_ifc_chan(chan); + enum dma_status dmaret; + unsigned long flags; + u32 status; + int residue =3D 0; + int tmp_residue =3D 0; + int i; + + dmaret =3D dma_cookie_status(chan, cookie, tx_state); + if (!tx_state || (dmaret =3D=3D DMA_COMPLETE)) + return dmaret; + + spin_lock_irqsave(&ifc_chan->lock, flags); + + status =3D readl(ifc_chan->chan_base + 4); + + if (status & IFC_STATUS_FIFO_EMPTY) + dmaret =3D DMA_COMPLETE; + else + dmaret =3D DMA_IN_PROGRESS; + + if (dmaret =3D=3D DMA_IN_PROGRESS) { + /* gather residue from all sg */ + for (i =3D 0; i < ifc_chan->rda_ifc->sg_max; i++) { + tmp_residue =3D readl(ifc_chan->chan_base + 12 + (8 * i)); + residue +=3D tmp_residue; + } + + dma_set_residue(tx_state, residue); + } + + spin_unlock_irqrestore(&ifc_chan->lock, flags); + + return dmaret; +} + +static int rda_ifc_terminate_all(struct dma_chan *chan) +{ + struct rda_ifc_chan *ifc_chan =3D to_ifc_chan(chan); + struct device *dev =3D dmaengine_get_dma_device(chan); + unsigned long flags; + u32 status, control; + int ret; + int i; + + spin_lock_irqsave(&ifc_chan->lock, flags); + + status =3D readl(ifc_chan->chan_base + 4); + + /* Flush operation only supports read requests */ + if (ifc_chan->direction =3D=3D DMA_DEV_TO_MEM) { + if (status & IFC_STATUS_FIFO_EMPTY) + goto clear_chan; + + control =3D readl(ifc_chan->chan_base); + control |=3D IFC_CTL_FLUSH; + writel(control, ifc_chan->chan_base); + + ret =3D readl_poll_timeout(ifc_chan->chan_base + 4, status, + (status & IFC_STATUS_FIFO_EMPTY), 100, 1000*1000); + if (ret < 0) + dev_err(dev, "Timed out flushing FIFO\n"); + } + +clear_chan: + control =3D readl(ifc_chan->chan_base); + control |=3D IFC_CTL_DISABLE; + writel(control, ifc_chan->chan_base); + + for (i =3D 0; i < ifc_chan->rda_ifc->sg_max; i++) + writel(0, ifc_chan->chan_base + 12 + (8 * i)); + + spin_unlock_irqrestore(&ifc_chan->lock, flags); + return 0; +} + +static int rda_ifc_chan_init(struct rda_ifc *ifc, struct dma_device *ddev, + int id) +{ + struct rda_ifc_chan *chan =3D &ifc->channels[id]; + + spin_lock_init(&chan->lock); + chan->rda_ifc =3D ifc; + chan->chan.chan_id =3D id; + chan->chan.device =3D &ifc->ddev; + chan->chan_base =3D ifc->base + 0x10 + (id * (8 + (8 * ifc->sg_max))); + + list_add_tail(&chan->chan.device_node, &ddev->channels); + return 0; +} + +static int rda_ifc_ddev_init(struct rda_ifc *ifc, struct dma_device *ddev) +{ + int ret; + int i; + + dma_cap_zero(ddev->cap_mask); + dma_cap_set(DMA_SLAVE, ddev->cap_mask); + dma_cap_set(DMA_PRIVATE, ddev->cap_mask); + + /* IFC maximum segment size is 32 MB */ + dma_set_max_seg_size(ddev->dev, 0x1FFFFFF); + dma_set_mask_and_coherent(ddev->dev, DMA_BIT_MASK(32)); + + /* IFC supports 8-bit and 32-bit transfers */ + ddev->copy_align =3D DMAENGINE_ALIGN_4_BYTES; + ddev->src_addr_widths =3D BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); + ddev->dst_addr_widths =3D BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); + ddev->directions =3D BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM); + + ddev->device_config =3D rda_ifc_device_config; + ddev->device_issue_pending =3D rda_ifc_issue_pending; + ddev->device_prep_slave_sg =3D rda_ifc_prep_slave_sg; + ddev->device_terminate_all =3D rda_ifc_terminate_all; + ddev->device_tx_status =3D rda_ifc_tx_status; + ddev->residue_granularity =3D DMA_RESIDUE_GRANULARITY_BURST; + + INIT_LIST_HEAD(&ddev->channels); + for (i =3D 0; i < ifc->max_chan; i++) { + ret =3D rda_ifc_chan_init(ifc, ddev, i); + if (ret) + return ret; + } + ddev->chancnt =3D i; + + return 0; +} + +static struct dma_chan *rda_ifc_xlate(struct of_phandle_args *dma_spec, + struct of_dma *of_dma) +{ + struct rda_ifc *ifc =3D of_dma->of_dma_data; + struct rda_ifc_chan *ifc_chan; + struct dma_chan *chan; + unsigned int request; + + if (dma_spec->args_count !=3D 1) + return NULL; + + request =3D dma_spec->args[0]; + if (request >=3D IFC_NO_REQUEST) + return NULL; + + chan =3D dma_get_any_slave_channel(&ifc->ddev); + if (!chan) + return NULL; + + ifc_chan =3D to_ifc_chan(chan); + ifc_chan->request_id =3D request; + + return chan; +} + +static int rda_ifc_probe(struct platform_device *pdev) +{ + const struct rda_ifc_platinfo *platinfo; + struct rda_ifc *ifc; + struct dma_device *ddev; + int ret; + + platinfo =3D of_device_get_match_data(&pdev->dev); + if (!platinfo) + return -EINVAL; + + ifc =3D devm_kzalloc(&pdev->dev, + struct_size(ifc, channels, platinfo->std_channb), + GFP_KERNEL); + if (!ifc) + return dev_err_probe(&pdev->dev, -ENOMEM, "Failed to allocate memory\n"); + + ifc->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(ifc->base)) + return dev_err_probe(&pdev->dev, PTR_ERR(ifc->base), "Cannot get base ad= dress\n"); + + ifc->max_chan =3D platinfo->std_channb; + ifc->sg_max =3D platinfo->sg_max; + + ddev =3D &ifc->ddev; + ddev->dev =3D &pdev->dev; + ret =3D rda_ifc_ddev_init(ifc, ddev); + if (ret) + return ret; + + platform_set_drvdata(pdev, ifc); + + ret =3D dma_async_device_register(ddev); + if (ret) + return ret; + + ret =3D of_dma_controller_register(pdev->dev.of_node, rda_ifc_xlate, ifc); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "Cannot register DMA controller\n"= ); + + return 0; +} + +static void rda_ifc_remove(struct platform_device *pdev) +{ + struct rda_ifc *ifc =3D platform_get_drvdata(pdev); + + dma_async_device_unregister(&ifc->ddev); + of_dma_controller_free(pdev->dev.of_node); +} + +static const struct rda_ifc_platinfo rda8810pl_data =3D { + .sg_max =3D 1, + .std_channb =3D 7 +}; + +static const struct of_device_id rda_ifc_of_match[] =3D { + { .compatible =3D "rda,8810pl-ifc", .data =3D &rda8810pl_data }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rda_ifc_of_match); + +static struct platform_driver rda_ifc_driver =3D { + .probe =3D rda_ifc_probe, + .remove =3D rda_ifc_remove, + .driver =3D { + .name =3D "rda-ifc", + .of_match_table =3D rda_ifc_of_match, + }, +}; +module_platform_driver(rda_ifc_driver); + +MODULE_AUTHOR("Dang Huynh "); +MODULE_DESCRIPTION("RDA IFC driver"); +MODULE_LICENSE("GPL"); --=20 2.51.0 From nobody Thu Oct 2 13:03:51 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6225932B48A; Tue, 16 Sep 2025 20:25:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-rda8810pl-drivers-v1-20-9ca9184ca977@mainlining.org> References: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> In-Reply-To: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> To: Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Alexandre Belloni , Michael Turquette , Stephen Boyd , Philipp Zabel , Sebastian Reichel , Vinod Koul , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, dmaengine@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mmc@vger.kernel.org, Dang Huynh X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758054322; l=799; i=dang.huynh@mainlining.org; s=20250917; h=from:subject:message-id; bh=ESVrh/e66fpCx8hkda0seGPWiRBFpNz918jLvjzC/2M=; b=xjdSUQMpB1QsdnW8tgHCeT8pweYzkXjix4jRKL4LWTM9cauqSrIz8lT0CyfI+75tbl+ectZHh CfYuGRCaLUQBLS7JKFKy7prh17FG7FrBkJ57XLn48PXdB9/L1RvywvP X-Developer-Key: i=dang.huynh@mainlining.org; a=ed25519; pk=RyzH4CL4YU/ItXYUurA51EVBidfx4lIy8/E4EKRJCUk= X-Endpoint-Received: by B4 Relay for dang.huynh@mainlining.org/20250917 with auth_id=526 X-Original-From: Dang Huynh Reply-To: dang.huynh@mainlining.org From: Dang Huynh Enable IFC so we can use it with I2C, SPI, SDMMC. Signed-off-by: Dang Huynh --- arch/arm/boot/dts/unisoc/rda8810pl.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/unisoc/rda8810pl.dtsi b/arch/arm/boot/dts/un= isoc/rda8810pl.dtsi index e90ae7845de7b79e55e9cd339a82313b423e0252..4b3ae19e9da41ee9ffa76dd4fff= 01824c07ce045 100644 --- a/arch/arm/boot/dts/unisoc/rda8810pl.dtsi +++ b/arch/arm/boot/dts/unisoc/rda8810pl.dtsi @@ -212,6 +212,12 @@ uart3: serial@90000 { interrupts =3D <11 IRQ_TYPE_LEVEL_HIGH>; status =3D "disabled"; }; + + ifc: dma-controller@f0000 { + compatible =3D "rda,8810pl-ifc"; + reg =3D <0xf0000 0x1000>; + #dma-cells =3D <1>; + }; }; =20 l2: cache-controller@21100000 { --=20 2.51.0 From nobody Thu Oct 2 13:03:51 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 786B032B4A5; Tue, 16 Sep 2025 20:25:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054326; cv=none; b=U+o4v85//cvUXHrbztm0OxBG63znBjxeVQlLD/BJG0W7E1WBmKuqHwfGMzJRCJnulIk9dKj5w1Vgm7dFCL5wKql1iPU5ur/T3gj6s3km6xoaWMmxgRkW6j+0BXvQn5KS6rbXLeaToQk3PyjKW1avGlgS+0+vwDkU3UxnA+yMGtg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054326; c=relaxed/simple; bh=0qQ2udejKRpnAkPOswtIFiUwzLjnAo9WAbKFCWb8urc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nIdzDQzcbZbtowlAPRdS1vAzzsAQ8orPXM/nMvIFcqYNpVj3ZTwE8bpZsPfRLgY3RIsPTUkCuKdDPl4ofSdwVwKPDyt7WvgFxwP6kQZQVQwxv9hAhLSvyHY2LnRzSy2W2dSq48QB/zRjk5tXpRQUBZfInJZfkj/i1+5coeXN4aM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Nqg+epgs; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Nqg+epgs" Received: by smtp.kernel.org (Postfix) with ESMTPS id 46689C4AF16; Tue, 16 Sep 2025 20:25:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758054326; bh=0qQ2udejKRpnAkPOswtIFiUwzLjnAo9WAbKFCWb8urc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Nqg+epgsHlJCi+v9o8ZDI7/WOr2tRhadQ1OmeKJ+oOqpGrEIAzHHvj4abZaUsZKbA yZvrtnwcN73RtvXF+U8Cu/qiaytS0G9WytGPaEvGGL1Ued4PZPR/Pn+gFR/lRkLad/ Ea232PZn3+Az7M9qxo25p8q4nRhRDrnDosHb28e5B8PmTWQqN1sZ0JSKz1Gb+Svf1+ 6Hn5/n6WquGODZXGOQx3ae2G/doiiGBS1RC1XdrMDM6oNPHGl/W0QbKdRK02j6WtfL ddwDL2RAmIc10ywIeYSXEbgR+ARBHdKRF870hz9J1E7KNVSysJ1T3tq6m8AEBvbtOf wpTIUU+rp3vnw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 325ABCAC5A3; Tue, 16 Sep 2025 20:25:26 +0000 (UTC) From: Dang Huynh via B4 Relay Date: Wed, 17 Sep 2025 03:25:18 +0700 Subject: [PATCH 21/25] dt-bindings: mmc: Add RDA SDMMC controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-rda8810pl-drivers-v1-21-9ca9184ca977@mainlining.org> References: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> In-Reply-To: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> To: Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Alexandre Belloni , Michael Turquette , Stephen Boyd , Philipp Zabel , Sebastian Reichel , Vinod Koul , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, dmaengine@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mmc@vger.kernel.org, Dang Huynh X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758054322; l=2660; i=dang.huynh@mainlining.org; s=20250917; h=from:subject:message-id; bh=a7tWvRJrTe69IGooiZ71r/xi++8VSr6BRQfhXkmhSjs=; b=k9ixwP93FswHA/DrqLQ0P+MKSIOY+R6N2rR/lW85K10mMwhxbS5PTIcRSPQbX5tIUM/Jvx8fC bD1/vTTKisDBkP3s5XNIBTbp0zTXkiqVGSf6Gx20RppETLe39/re5tT X-Developer-Key: i=dang.huynh@mainlining.org; a=ed25519; pk=RyzH4CL4YU/ItXYUurA51EVBidfx4lIy8/E4EKRJCUk= X-Endpoint-Received: by B4 Relay for dang.huynh@mainlining.org/20250917 with auth_id=526 X-Original-From: Dang Huynh Reply-To: dang.huynh@mainlining.org From: Dang Huynh Add documentation describing the SD/MMC controller in RDA Micro RDA8810PL SoC. Signed-off-by: Dang Huynh --- Documentation/devicetree/bindings/mmc/rda,mmc.yaml | 91 ++++++++++++++++++= ++++ 1 file changed, 91 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/rda,mmc.yaml b/Documenta= tion/devicetree/bindings/mmc/rda,mmc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..dfdd9c6d3044061c342519e35e3= 9c7751874bb03 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/rda,mmc.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/rda,mmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RDA Micro SD/MMC Controller + +allOf: + - $ref: mmc-controller.yaml + +maintainers: + - Dang Huynh + +properties: + compatible: + const: rda,8810pl-mmc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: apb + + resets: + maxItems: 1 + + dmas: + minItems: 2 + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + + rda,mclk-adj: + $ref: /schemas/types.yaml#/definitions/uint8 + description: + Some board need MCLK to be adjusted for the card to work. + If not present, MCLK will be handled by an external PCLK. + minimum: 0 + maximum: 255 + + rda,mclk-inv: + $ref: /schemas/types.yaml#/definitions/flag + description: + Some board need MCLK to be inverted for the card to work. + If not present, MCLK is not inverted. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - dmas + - dma-names + - vmmc-supply + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + mmc1: mmc@20950000 { + compatible =3D "rda,8810pl-mmc"; + reg =3D <0x20950000 0x1000>; + interrupts =3D <3 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ap_syscon CLK_APB2>; + clock-names =3D "apb"; + resets =3D <&ap_syscon RST_APB2_SDMMC1>; + dmas =3D <&ifc IFC_SDMMC1_TX>, <&ifc IFC_SDMMC1_RX>; + dma-names =3D "tx", "rx"; + vmmc-supply =3D <&vdd_sdmmc>; + rda,mclk-adj =3D /bits/ 8 <1>; + rda,mclk-inv; + status =3D "disabled"; + }; + +... --=20 2.51.0 From nobody Thu Oct 2 13:03:51 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8032732B4B1; Tue, 16 Sep 2025 20:25:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054326; cv=none; b=AgXVj2YiLEa1naM7WbCltk8oLwb0ytt2PMiEehObSvb8EW4i9zxUiYpejA4+SbLsS2BICF5pBimQes0+wbE4/uLzZtT+08N8cdZ/5Dvwe+cYVjH8FsxMhgU+c9jnlGryK7Sv1viKPUGQpe3Hnl7cjATCiJtD87Z68x8rxS8NOLE= ARC-Message-Signature: i=1; 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b=YbmrirpMxYvcYNhzYCbNyvSrUr0P++UaaQINgoZfl5+RReJPFv/YIQN3qfL8ZoKTF IWbDl/5X0vbGDMY8kAMNMYrlHfN4SjcFdw40cGRvLZ20AFLLTMVFV41s2zkOYtXONy iFh4rx/12xFS/VLxOErWL/Gnw63NGlHQapLmVH0JX3ZRqYtXklSey59N1RGgfeUrvq nygw47mri9TfWHfPPDSkD5r7xfe+fKAHhAD+HeRdM3z8GoDd3CXfnHvdD14xVtnHSS NcdLhoh+eK0QNHs3fGMRSN+dX5bbvSKXstWWXyGzz3BsrTzN13mGSUuqz/csNyPWpf 221VpYqOwVPmw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44692CAC592; Tue, 16 Sep 2025 20:25:26 +0000 (UTC) From: Dang Huynh via B4 Relay Date: Wed, 17 Sep 2025 03:25:19 +0700 Subject: [PATCH 22/25] mmc: host: Add RDA Micro SD/MMC driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-rda8810pl-drivers-v1-22-9ca9184ca977@mainlining.org> References: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> In-Reply-To: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> To: Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Alexandre Belloni , Michael Turquette , Stephen Boyd , Philipp Zabel , Sebastian Reichel , Vinod Koul , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, dmaengine@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mmc@vger.kernel.org, Dang Huynh X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758054322; l=25605; i=dang.huynh@mainlining.org; s=20250917; h=from:subject:message-id; bh=kM52IsCiYRotM7GzUsUvED96oijVZ9O0VQ9eo3hPKnM=; b=rMz/A3RkPApebTjBcT5FekA3YZNK3M0XuzxfKpb02/jCjD21PtYt+jtAT3E8bTHXxDrJFaACa 2Oz3JRC5b1yCajLjs/9SsYDsjdy0F4ylGfxmkby/ZrP2cZWZveotwEW X-Developer-Key: i=dang.huynh@mainlining.org; a=ed25519; pk=RyzH4CL4YU/ItXYUurA51EVBidfx4lIy8/E4EKRJCUk= X-Endpoint-Received: by B4 Relay for dang.huynh@mainlining.org/20250917 with auth_id=526 X-Original-From: Dang Huynh Reply-To: dang.huynh@mainlining.org From: Dang Huynh RDA Micro RDA8810PL includes an SD/MMC controller. This controller supports SD/SDIO/MMC interface. Signed-off-by: Dang Huynh --- MAINTAINERS | 6 + drivers/mmc/host/Kconfig | 12 + drivers/mmc/host/Makefile | 1 + drivers/mmc/host/rda-mmc.c | 853 +++++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 872 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 91be43782f4ba8aacb629002d357a66704f10b2b..33e04ce35dcc4cbadd715ec9199= f2453237b8002 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21417,6 +21417,12 @@ S: Maintained F: Documentation/devicetree/bindings/rtc/rda,8810pl-rtc.yaml F: drivers/rtc/rtc-rda.c =20 +RDA MICRO SECURE DIGITAL AND MULTIMEDIA CARD DRIVER +M: Dang Huynh +S: Maintained +F: Documentation/devicetree/bindings/mmc/rda,mmc.yaml +F: drivers/mmc/host/rda-mmc.c + RDACM20 Camera Sensor M: Jacopo Mondi M: Kieran Bingham diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 4afa0130779d97ca9d1c0ed2102b0babdedcaeeb..352a6eb4e30793b7311c7877c23= 8a7fe31121123 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -1040,6 +1040,18 @@ config MMC_MTK This is needed if support for any SD/SDIO/MMC devices is required. If unsure, say N. =20 +config MMC_RDA + tristate "RDA Micro SD/MMC Card Interface support" + depends on ARCH_RDA + depends on COMMON_CLK + depends on HAS_DMA + help + This selects the RDA Micro Secure digital and Multimedia card interface= . The + controller supports SD/SDIO/MMC interface. + If you have a board with RDA SoC and it uses this interface, say Y or M= here. + + If unsure, say N. + config MMC_SDHCI_MICROCHIP_PIC32 tristate "Microchip PIC32MZDA SDHCI support" depends on MMC_SDHCI && PIC32MZDA && MMC_SDHCI_PLTFM diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 5057fea8afb696e210e465a6a2aafc68adad7854..d819e18a478e35cb7de6d67b1cf= 827e1b3d09815 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_MMC_ALCOR) +=3D alcor.o obj-$(CONFIG_MMC_MTK) +=3D mtk-sd.o obj-$(CONFIG_MMC_OMAP) +=3D omap.o obj-$(CONFIG_MMC_OMAP_HS) +=3D omap_hsmmc.o +obj-$(CONFIG_MMC_RDA) +=3D rda-mmc.o obj-$(CONFIG_MMC_ATMELMCI) +=3D atmel-mci.o obj-$(CONFIG_MMC_TIFM_SD) +=3D tifm_sd.o obj-$(CONFIG_MMC_MVSDIO) +=3D mvsdio.o diff --git a/drivers/mmc/host/rda-mmc.c b/drivers/mmc/host/rda-mmc.c new file mode 100644 index 0000000000000000000000000000000000000000..1767d387bc482694fa9935bc59c= eba7e2a8a7535 --- /dev/null +++ b/drivers/mmc/host/rda-mmc.c @@ -0,0 +1,853 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * SD/MMC driver for RDA Micro platform + * + * Copyright (C) 2013 RDA Microelectronics Inc. + * Copyright (c) 2025 Dang Huynh + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Registers Definitions */ +#define SDMMC_REG_CTRL 0x0 +#define SDMMC_REG_FIFO_TXRX 0x8 +#define SDMMC_REG_CONFIG 0x800 +#define SDMMC_REG_STATUS 0x804 +#define SDMMC_REG_CMD_INDEX 0x808 +#define SDMMC_REG_CMD_ARG 0x80C +#define SDMMC_REG_RESP_INDEX 0x810 +#define SDMMC_REG_RESP_ARG3 0x814 +#define SDMMC_REG_RESP_ARG2 0x818 +#define SDMMC_REG_RESP_ARG1 0x81C +#define SDMMC_REG_RESP_ARG0 0x820 +#define SDMMC_REG_DATA_WIDTH 0x824 +#define SDMMC_REG_BLOCK_SIZE 0x828 +#define SDMMC_REG_BLOCK_COUNT 0x82C +#define SDMMC_REG_INT_STATUS 0x830 +#define SDMMC_REG_INT_MASK 0x834 +#define SDMMC_REG_INT_CLEAR 0x838 +#define SDMMC_REG_TRANS_SPEED 0x83C +#define SDMMC_REG_MCLK_ADJUST 0x840 + +/* Bits def */ +/* CTRL */ +#define SDMMC_CTRL_ENDIAN GENMASK(2, 0) +#define SDMMC_CTRL_SOFTRST_L BIT(3) + +/* CONFIG */ +#define SDMMC_CFG_SENDCMD BIT(0) +#define SDMMC_CFG_SUSPEND BIT(1) +#define SDMMC_CFG_RSP_EN BIT(4) +#define SDMMC_CFG_RSP_SEL GENMASK(6, 5) +#define SDMMC_CFG_RD_WT_EN BIT(8) +#define SDMMC_CFG_RD_WT_SEL BIT(9) +#define SDMMC_CFG_S_M_SEL BIT(10) +#define SDMMC_CFG_AUTO_FLAG_EN BIT(16) +#define SDMMC_CFG_SAMPLE_EDGE_SEL_FALL_EN BIT(17) + +/* STATUS */ +#define SDMMC_STATUS_NOTOVER BIT(0) +#define SDMMC_STATUS_BUSY BIT(1) +#define SDMMC_STATUS_DLBUSY BIT(2) +#define SDMMC_STATUS_SUSPEND BIT(3) +#define SDMMC_STATUS_RSP_ERR BIT(8) +#define SDMMC_STATUS_NO_RSP_ERR BIT(9) +#define SDMMC_STATUS_CRC_STATUS GENMASK(14, 12) +#define SDMMC_STATUS_DATA_ERROR GENMASK(23, 16) +#define SDMMC_STATUS_DAT3_VAL BIT(24) + +/* INTERRUPTS */ +/* Mask and Clear */ +#define SDMMC_INT_NO_RSP BIT(0) +#define SDMMC_INT_RSP_ERR BIT(1) +#define SDMMC_INT_RD_ERR BIT(2) +#define SDMMC_INT_WR_ERR BIT(3) +#define SDMMC_INT_DAT_OVER BIT(4) +#define SDMMC_INT_TXDMA_DONE BIT(5) +#define SDMMC_INT_RXDMA_DONE BIT(6) +#define SDMMC_INT_SDIO BIT(7) + +#define SDMMC_MCLK_INVERT BIT(4) +#define SDMMC_MCLK_DISABLE BIT(5) + +struct rda_mmc_host { + struct device *dev; + + struct mmc_host *mmc; + struct mmc_request *mrq; + + unsigned int clock; + unsigned int bus_width; + unsigned int power_mode; + struct regulator *vmmc; + + void __iomem *base; + int irq; + + struct clk *clk; + struct reset_control *reset; + + dma_cookie_t dma_cookie; + struct dma_chan *dma_tx; + struct dma_chan *dma_rx; + + bool sdio_irq; + bool sdio_irq_trigger; + + spinlock_t lock; + struct completion c; + + /* device tree properties */ + bool mclk_inv; + u8 mclk_adj; +}; + +static int rda_mmc_hw_init(struct rda_mmc_host *priv) +{ + void __iomem *base =3D priv->base; + + disable_irq(priv->irq); + + writel(FIELD_PREP(SDMMC_CTRL_ENDIAN, 1) | SDMMC_CTRL_SOFTRST_L, + base + SDMMC_REG_CTRL); + writel(SDMMC_INT_RD_ERR | SDMMC_INT_WR_ERR | SDMMC_INT_DAT_OVER, + base + SDMMC_REG_INT_MASK); + writel(0xFFFFFFFF, base + SDMMC_REG_INT_CLEAR); + + enable_irq(priv->irq); + + return 0; +} + +static void rda_mmc_reset(struct rda_mmc_host *priv) +{ + reset_control_assert(priv->reset); + mdelay(1); + reset_control_deassert(priv->reset); + mdelay(1); +} + +static void rda_mmc_recv_resp(struct mmc_host *host, struct mmc_command *c= md) +{ + struct rda_mmc_host *priv =3D mmc_priv(host); + struct device *dev =3D mmc_dev(host); + void __iomem *base =3D priv->base; + u32 status; + int ret; + + /* If the controller is busy, wait until it finishes */ + ret =3D readl_poll_timeout(base + SDMMC_REG_STATUS, status, + !(status & SDMMC_STATUS_NOTOVER), 50, 1000 * 1000); + if (ret) { + dev_err(dev, "Timed out waiting for the controller\n"); + cmd->error =3D ret; + return; + } + + if (status & SDMMC_STATUS_NO_RSP_ERR) + return; + + if (status & SDMMC_STATUS_RSP_ERR) { + cmd->error =3D -EILSEQ; + return; + } + + if (mmc_resp_type(cmd) & MMC_RSP_R2) { + cmd->resp[0] =3D readl_relaxed(base + SDMMC_REG_RESP_ARG3); + cmd->resp[1] =3D readl_relaxed(base + SDMMC_REG_RESP_ARG2); + cmd->resp[2] =3D readl_relaxed(base + SDMMC_REG_RESP_ARG1); + cmd->resp[3] =3D readl_relaxed(base + SDMMC_REG_RESP_ARG0) << 1; + } else { + cmd->resp[0] =3D readl_relaxed(base + SDMMC_REG_RESP_ARG3); + } + + dev_dbg(dev, "response: resp[0] =3D 0x%x, resp[1] =3D 0x%x, resp[2] =3D 0= x%x, resp[3] =3D 0x%x\n", + cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); +} + +static inline struct dma_chan *rda_mmc_get_dma_chan(struct rda_mmc_host *p= riv, + struct mmc_data *data) +{ + if (data->flags & MMC_DATA_WRITE) + return priv->dma_tx; + else + return priv->dma_rx; +} + +static int rda_mmc_send_data(struct mmc_host *host, struct mmc_data *data) +{ + struct rda_mmc_host *priv =3D mmc_priv(host); + struct device *dev =3D mmc_dev(host); + struct dma_slave_config slave_config; + struct dma_async_tx_descriptor *desc; + struct dma_chan *chan; + int ret; + + if (!data) { + dev_err(dev, "No MMC request or data\n"); + goto fail; + } + + if (data->flags & MMC_DATA_WRITE) { + slave_config.dst_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; + slave_config.direction =3D DMA_MEM_TO_DEV; + } else { + slave_config.src_addr_width =3D DMA_SLAVE_BUSWIDTH_4_BYTES; + slave_config.direction =3D DMA_DEV_TO_MEM; + } + + data->sg_count =3D dma_map_sg(dev, data->sg, data->sg_len, mmc_get_dma_di= r(data)); + if (data->sg_count =3D=3D 0) { + ret =3D -ENOMEM; + goto fail; + } + + chan =3D rda_mmc_get_dma_chan(priv, data); + + ret =3D dmaengine_slave_config(chan, &slave_config); + if (ret) { + dev_err(dev, "Failed to configure DMAC\n"); + goto fail_dma; + } + + desc =3D dmaengine_prep_slave_sg(chan, data->sg, data->sg_count, + slave_config.direction, DMA_CTRL_ACK); + if (!desc) { + dev_err(dev, "Failed to allocate DMA descriptor\n"); + goto fail_dma; + } + + priv->dma_cookie =3D dmaengine_submit(desc); + if (!priv->dma_cookie) { + dev_err(dev, "Failed to submit DMA request\n"); + goto fail_dma; + } + + dma_async_issue_pending(chan); + + return 0; + +fail_dma: + dma_unmap_sg(dev, data->sg, data->sg_len, mmc_get_dma_dir(data)); +fail: + return -EINVAL; +} + +static int rda_mmc_prepare_data(struct mmc_host *host, struct mmc_command = *cmd, + struct mmc_data *data, u32 *cfg) +{ + struct rda_mmc_host *priv =3D mmc_priv(host); + struct device *dev =3D mmc_dev(host); + void __iomem *base =3D priv->base; + int hw_blksz =3D 2; /* 1 word */ + int i =3D 0; + + /* If we're still here, we'll assume there's data ops */ + *cfg |=3D SDMMC_CFG_RD_WT_EN; + + /* Tell the controller we have a write operation */ + if (data->flags & MMC_DATA_WRITE) + *cfg |=3D SDMMC_CFG_RD_WT_SEL; + + /* Multiple data read/write */ + if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { + *cfg |=3D SDMMC_CFG_S_M_SEL; + + /* + * Tell the controller to automatically issue CMD12 when the last block + * transfer is completed on non-SDIO cards. + */ + if (!mmc_card_sdio(host->card)) + *cfg |=3D SDMMC_CFG_AUTO_FLAG_EN; + } + + /* Blocksize on this IP is calculated by how many words are requested */ + if (data->blksz > 4) { + for (i =3D 4; i < data->blksz; i <<=3D 1) + hw_blksz++; + } + + if (unlikely(hw_blksz > 11)) { + dev_err(dev, "Requested %d but hardware can only support 11!\n", hw_blks= z); + return -EINVAL; + } + + writel_relaxed(data->blocks, base + SDMMC_REG_BLOCK_COUNT); + writel_relaxed(hw_blksz, base + SDMMC_REG_BLOCK_SIZE); + + return 0; +} + +static int rda_mmc_send_cmd(struct mmc_host *host, struct mmc_command *cmd, + struct mmc_data *data) +{ + struct rda_mmc_host *priv =3D mmc_priv(host); + void __iomem *base =3D priv->base; + u32 cfg =3D SDMMC_CFG_SENDCMD; + int ret; + + switch (mmc_resp_type(cmd)) { + case MMC_RSP_R2: + cfg |=3D SDMMC_CFG_RSP_EN | FIELD_PREP(SDMMC_CFG_RSP_SEL, 2); + break; + case MMC_RSP_R3: + cfg |=3D SDMMC_CFG_RSP_EN | FIELD_PREP(SDMMC_CFG_RSP_SEL, 1); + break; + default: + cfg |=3D SDMMC_CFG_RSP_EN; + break; + } + + /* No data */ + if (!data) + goto send_to_soc; + + /* Data operations */ + ret =3D rda_mmc_prepare_data(host, cmd, data, &cfg); + if (ret < 0) + return -EINVAL; + + ret =3D rda_mmc_send_data(host, data); + if (ret < 0) + return -EINVAL; + +send_to_soc: + writel(cmd->opcode, base + SDMMC_REG_CMD_INDEX); + writel(cmd->arg, base + SDMMC_REG_CMD_ARG); + writel(cfg, base + SDMMC_REG_CONFIG); + + dev_dbg(priv->dev, "mmc_resp_type =3D %d, cmd->opcode =3D 0x%x, cmd->arg = =3D 0x%x - cfg: 0x%x\n", + mmc_resp_type(cmd), cmd->opcode, cmd->arg, cfg); + + rda_mmc_recv_resp(host, cmd); + + return 0; +} + +/* + * Once data transfer failed (or aborted), the controller needs to be + * cleaned up. + */ +static void rda_mmc_data_abort(struct mmc_host *host, struct mmc_request *= mrq) +{ + struct rda_mmc_host *priv =3D mmc_priv(host); + struct device *dev =3D mmc_dev(host); + void __iomem *base =3D priv->base; + struct mmc_command stop; + int ret; + + writel_relaxed(0, base + SDMMC_REG_BLOCK_COUNT); + writel_relaxed(0, base + SDMMC_REG_BLOCK_SIZE); + + if (!host->card) + return; + + /* + * Issue a stop command first, because if the controller timed out, + * it'll not return an IRQ or any indicator. + */ + if (!mmc_card_sdio(host->card)) { + if (!mrq->stop) { + stop.opcode =3D MMC_STOP_TRANSMISSION; + stop.arg =3D 0; + stop.flags =3D MMC_RSP_R1B | MMC_CMD_AC; + ret =3D rda_mmc_send_cmd(host, &stop, NULL); + } else { + ret =3D rda_mmc_send_cmd(host, mrq->stop, NULL); + } + + if (ret < 0) + dev_err(dev, "Failed to send stop command\n"); + } +} + +static void rda_mmc_request(struct mmc_host *host, struct mmc_request *req) +{ + struct rda_mmc_host *priv =3D mmc_priv(host); + struct device *dev =3D mmc_dev(host); + struct mmc_data *data =3D NULL; + struct dma_chan *chan; + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + + WARN_ON(priv->mrq); + priv->mrq =3D req; + + if (req->data) { + dev_dbg(dev, "Block size =3D %d - Blocks =3D %d - Offset: %d - Length: %= d\n", + req->data->blksz, req->data->blocks, + req->data->sg->offset, req->data->sg->length); + data =3D req->data; + } + + if (rda_mmc_send_cmd(host, req->cmd, data) < 0) { + req->cmd->error =3D -EINVAL; + if (data) + req->data->error =3D -EINVAL; + + goto done_irqunlock; + } + + /* Interrupt will pick up on this */ + if (!data) + goto done_irqunlock; + + spin_unlock_irqrestore(&priv->lock, flags); + + /* + * On a data operation, we rely on our interrupt to tell us + * when the transmission is finished (or failed). + * + * However with this IP, if the operation timed out, it will + * not trigger an IRQ and we'll not return. + */ + if (data) { + if (wait_for_completion_timeout(&priv->c, + msecs_to_jiffies(5000)) =3D=3D 0) { + spin_lock_irqsave(&priv->lock, flags); + priv->mrq =3D NULL; + + dma_unmap_sg(dev, data->sg, data->sg_len, + mmc_get_dma_dir(data)); + + chan =3D rda_mmc_get_dma_chan(priv, data); + + dmaengine_terminate_sync(chan); + rda_mmc_data_abort(host, req); + + req->cmd->error =3D -ETIMEDOUT; + req->data->error =3D -ETIMEDOUT; + goto done_irqunlock; + } + } + + return; + +done_irqunlock: + priv->mrq =3D NULL; + spin_unlock_irqrestore(&priv->lock, flags); + mmc_request_done(host, req); +} + +static void rda_mmc_set_ios(struct mmc_host *host, struct mmc_ios *ios) +{ + struct rda_mmc_host *priv =3D mmc_priv(host); + struct device *dev =3D mmc_dev(host); + void __iomem *base =3D priv->base; + unsigned long mclk_rate; + unsigned int clk_div; + unsigned long flags; + u32 reg_mclk =3D 0; + int ret; + + spin_lock_irqsave(&priv->lock, flags); + + if (priv->bus_width !=3D ios->bus_width) { + priv->bus_width =3D ios->bus_width; + writel(BIT(priv->bus_width), base + SDMMC_REG_DATA_WIDTH); + } + + if (priv->power_mode !=3D ios->power_mode) { + priv->power_mode =3D ios->power_mode; + if (priv->power_mode =3D=3D MMC_POWER_UP) { + ret =3D regulator_enable(priv->vmmc); + if (ret) + dev_err(dev, "Failed to turn on vmmc\n"); + } else if (priv->power_mode =3D=3D MMC_POWER_OFF) { + ret =3D regulator_disable(priv->vmmc); + if (ret) + dev_err(dev, "Failed to turn off vmmc\n"); + } + } + + if (priv->clock !=3D ios->clock) { + priv->clock =3D ios->clock; + if (ios->clock) { + /* trans speed */ + mclk_rate =3D clk_get_rate(priv->clk); + if (mclk_rate =3D=3D 0) { + dev_err(dev, "Invalid APB clock rate\n"); + goto bailout; + } + + clk_div =3D mclk_rate / (2 * ios->clock); + if (mclk_rate % (2 * ios->clock)) + clk_div++; + + if (clk_div >=3D 1) + clk_div -=3D 1; + + if (clk_div > 255) + clk_div =3D 255; + + /* mclk adjust */ + if (priv->mclk_inv) + reg_mclk =3D SDMMC_MCLK_INVERT; + + reg_mclk |=3D priv->mclk_adj; + + writel_relaxed(clk_div, base + SDMMC_REG_TRANS_SPEED); + writel_relaxed(reg_mclk, base + SDMMC_REG_MCLK_ADJUST); + + dev_dbg(dev, "set clk =3D %d - mclk =3D %ld - divider =3D %d\n", + ios->clock, mclk_rate, clk_div); + } else { + writel_relaxed(SDMMC_MCLK_DISABLE, base + SDMMC_REG_MCLK_ADJUST); + } + } + +bailout: + dev_dbg(dev, "buswidth=3D%d, clock=3D%d, power=3D%d\n", + ios->bus_width, ios->clock, ios->power_mode); + + spin_unlock_irqrestore(&priv->lock, flags); +} + +static void rda_mmc_crc_status(struct mmc_host *host) +{ + struct rda_mmc_host *priv =3D mmc_priv(host); + struct device *dev =3D mmc_dev(host); + void __iomem *base =3D priv->base; + const char *crc_error; + u32 status; + + status =3D readl_relaxed(base + SDMMC_REG_STATUS); + + switch (FIELD_GET(SDMMC_STATUS_CRC_STATUS, status)) { + case 0b101: + crc_error =3D "Transmission Error"; + break; + case 0b010: + crc_error =3D "Transmission Right"; + break; + case 0b111: + crc_error =3D "Flash Programming Error"; + break; + default: + crc_error =3D "Unknown"; + break; + } + + dev_err(dev, "CRC Error: %s - DATA_ERROR: 0x%lx\n", crc_error, + FIELD_GET(SDMMC_STATUS_DATA_ERROR, status)); +} + +static irqreturn_t rda_mmc_irq(int irq, void *dev_id) +{ + struct rda_mmc_host *priv =3D dev_id; + struct mmc_host *host =3D mmc_from_priv(priv); + struct device *dev =3D mmc_dev(host); + void __iomem *base =3D priv->base; + struct mmc_request *mrq; + u32 status; + irqreturn_t irqret =3D IRQ_NONE; + + status =3D readl(base + SDMMC_REG_INT_STATUS); + writel((status & 0xFF), base + SDMMC_REG_INT_CLEAR); + + dev_dbg(dev, "IRQ requested - status: 0x%x\n", status); + + if (!priv->mrq || !priv->mrq->data) + goto irq_done; + + mrq =3D priv->mrq; + + if (mrq->data && ((status & SDMMC_INT_RD_ERR) || (status & SDMMC_INT_WR_E= RR))) + mrq->data->error =3D -EILSEQ; + + if (priv->sdio_irq && (status & SDMMC_INT_SDIO)) + priv->sdio_irq_trigger =3D true; + + irqret =3D IRQ_WAKE_THREAD; + + /* We got an error, no need to do the additional checks */ + if (mrq->data->error) + goto irq_done; + + /* + * If we don't have any error but DAT_OVER isn't triggered, then we'll as= sume + * that we got an unexpected IRQ (during a data transfer) + */ + if (!mrq->data->error && !(status & SDMMC_INT_DAT_OVER)) + irqret =3D IRQ_HANDLED; + +irq_done: + if (irqret =3D=3D IRQ_NONE) + dev_info(dev, + "Unexpected IRQ - was a data transfer requested? IRQ: 0x%x\n", status); + + return irqret; +} + +static irqreturn_t rda_mmc_irq_fn(int irq, void *dev_id) +{ + struct rda_mmc_host *priv =3D dev_id; + struct mmc_host *host =3D mmc_from_priv(priv); + struct device *dev =3D mmc_dev(host); + struct mmc_request *mrq; + struct dma_chan *chan; + struct dma_tx_state state; + enum dma_status dma_status; + unsigned long flags; + + if (WARN_ON(!priv->mrq)) + return IRQ_NONE; + + spin_lock_irqsave(&priv->lock, flags); + + mrq =3D priv->mrq; + + if (mrq->data) { + chan =3D rda_mmc_get_dma_chan(priv, mrq->data); + + if (mrq->data->error) { + mrq->data->bytes_xfered =3D 0; + rda_mmc_crc_status(host); + dmaengine_terminate_sync(chan); + rda_mmc_data_abort(host, mrq); + } else { + mrq->data->bytes_xfered =3D + mrq->data->blocks * mrq->data->blksz; + + /* + * With this IP, just because a TXDMA/RXDMA interrupt is triggered, + * doesn't mean the MMC is fully processed. + */ + dma_status =3D dmaengine_tx_status(chan, priv->dma_cookie, &state); + dev_dbg(mmc_dev(host), "DMA Status: %d\n", dma_status); + if (dma_status !=3D DMA_COMPLETE) { + dev_err(dev, "Transmit IRQ triggered but DMA is not finished\n"); + mrq->data->error =3D -ETIMEDOUT; + mrq->data->bytes_xfered =3D 0; + dmaengine_terminate_sync(chan); + rda_mmc_data_abort(host, mrq); + } + } + + /* + * Since we told the controller to automatically send a stop command, + * we don't have to send a stop command here. + */ + dma_unmap_sg(dev, mrq->data->sg, mrq->data->sg_len, + mmc_get_dma_dir(mrq->data)); + dmaengine_terminate_sync(chan); + } + + priv->mrq =3D NULL; + spin_unlock_irqrestore(&priv->lock, flags); + + complete(&priv->c); + mmc_request_done(host, mrq); + + if (priv->sdio_irq && priv->sdio_irq_trigger) + mmc_signal_sdio_irq(host); + + return IRQ_HANDLED; +} + +static int rda_mmc_card_busy(struct mmc_host *host) +{ + struct rda_mmc_host *priv =3D mmc_priv(host); + void __iomem *base =3D priv->base; + u32 status =3D readl(base + SDMMC_REG_STATUS); + + return (status & SDMMC_STATUS_DLBUSY); +} + +static void rda_mmc_sdio_enable_irq(struct mmc_host *host, int enable) +{ + struct rda_mmc_host *priv =3D mmc_priv(host); + void __iomem *base =3D priv->base; + u32 intmask =3D readl(base + SDMMC_REG_INT_MASK); + + if (enable) { + intmask |=3D SDMMC_INT_SDIO; + priv->sdio_irq =3D true; + } else { + intmask &=3D ~SDMMC_INT_SDIO; + priv->sdio_irq =3D false; + } + + priv->sdio_irq_trigger =3D false; + + writel(intmask, base + SDMMC_REG_INT_MASK); +} + +static const struct mmc_host_ops rda_mmc_ops =3D { + .request =3D rda_mmc_request, + .set_ios =3D rda_mmc_set_ios, + .get_cd =3D mmc_gpio_get_cd, + .get_ro =3D mmc_gpio_get_ro, + .card_busy =3D rda_mmc_card_busy, + .enable_sdio_irq =3D rda_mmc_sdio_enable_irq, +}; + +static void rda_mmc_of_parse(struct device_node *np, struct rda_mmc_host *= priv) +{ + bool mclk_inv =3D false; + u8 mclk_adj =3D 1; + + if (of_property_present(np, "rda,mclk-inv")) + mclk_inv =3D true; + + of_property_read_u8(np, "rda,mclk-adj", &mclk_adj); + + priv->mclk_inv =3D mclk_inv; + priv->mclk_adj =3D mclk_adj; +} + +static int rda_mmc_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct rda_mmc_host *priv; + struct mmc_host *mmc; + struct clk *clk; + struct reset_control *reset; + struct dma_chan *tx, *rx; + struct regulator *vmmc; + void __iomem *base; + int irq; + int ret; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return dev_err_probe(dev, PTR_ERR(base), "Cannot get iomap\n"); + + irq =3D platform_get_irq(pdev, 0); + if (irq < 0) + return dev_err_probe(dev, irq, "Cannot get IRQ: %d\n", irq); + + clk =3D devm_clk_get_enabled(dev, "apb"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "Cannot get clock device\n"); + + vmmc =3D devm_regulator_get(dev, "vmmc"); + if (IS_ERR(vmmc)) + return dev_err_probe(dev, PTR_ERR(vmmc), "Failed to obtain regulator\n"); + + reset =3D devm_reset_control_get_by_index(dev, 0); + if (IS_ERR(reset)) + return dev_err_probe(dev, PTR_ERR(reset), "Failed to obtain reset\n"); + + tx =3D dma_request_chan(dev, "tx"); + if (IS_ERR(tx)) + return dev_err_probe(dev, PTR_ERR(tx), "Failed to request tx channel\n"); + + rx =3D dma_request_chan(dev, "rx"); + if (IS_ERR(rx)) + return dev_err_probe(dev, PTR_ERR(rx), "Failed to request rx channel\n"); + + mmc =3D devm_mmc_alloc_host(dev, sizeof(*priv)); + if (IS_ERR(mmc)) { + dev_err(dev, "Cannot allocate memory for MMC\n"); + ret =3D PTR_ERR(mmc); + goto fail_release_dma; + } + + priv =3D mmc_priv(mmc); + priv->dev =3D dev; + priv->base =3D base; + priv->irq =3D irq; + priv->clk =3D clk; + priv->reset =3D reset; + priv->dma_tx =3D tx; + priv->dma_rx =3D rx; + priv->vmmc =3D vmmc; + spin_lock_init(&priv->lock); + init_completion(&priv->c); + + mmc->ops =3D &rda_mmc_ops; + + mmc->max_segs =3D 1; + mmc->max_blk_size =3D 4096; + mmc->max_blk_count =3D 0xFFFF; + mmc->max_req_size =3D 0xFFFF; + mmc->max_seg_size =3D 0xFFFF; + + mmc->f_min =3D 1000000; + mmc->caps =3D MMC_CAP_4_BIT_DATA; + mmc->ocr_avail =3D MMC_VDD_32_33 | MMC_VDD_33_34; + + rda_mmc_of_parse(dev->of_node, priv); + + ret =3D mmc_of_parse(mmc); + if (ret) { + dev_err(dev, "Failed to parse device tree: %d\n", ret); + goto fail_release_dma; + } + + rda_mmc_reset(priv); + rda_mmc_hw_init(priv); + + priv->bus_width =3D -1; + + ret =3D devm_request_threaded_irq(dev, irq, rda_mmc_irq, rda_mmc_irq_fn, + IRQF_ONESHOT, mmc_hostname(mmc), priv); + if (ret) { + dev_err(dev, "Failed to request IRQ: %d\n", ret); + goto fail_release_dma; + } + + ret =3D mmc_add_host(mmc); + if (ret) { + dev_err(dev, "Failed to add MMC host: %d\n", ret); + goto fail_release_dma; + } + + platform_set_drvdata(pdev, mmc); + return 0; + +fail_release_dma: + dma_release_channel(rx); + dma_release_channel(tx); + return ret; +} + +static void rda_mmc_remove(struct platform_device *pdev) +{ + struct rda_mmc_host *host =3D platform_get_drvdata(pdev); + + mmc_remove_host(host->mmc); + dma_release_channel(host->dma_rx); + dma_release_channel(host->dma_tx); +} + +static const struct of_device_id rda_mmc_dt_ids[] =3D { + { .compatible =3D "rda,8810pl-mmc", }, + {}, +}; +MODULE_DEVICE_TABLE(of, rda_mmc_dt_ids); + +static struct platform_driver rda_mmc_driver =3D { + .probe =3D rda_mmc_probe, + .remove =3D rda_mmc_remove, + .driver =3D { + .name =3D "rda-mmc", + .probe_type =3D PROBE_PREFER_ASYNCHRONOUS, + .of_match_table =3D rda_mmc_dt_ids, + }, +}; +module_platform_driver(rda_mmc_driver); + +MODULE_AUTHOR("Dang Huynh "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("MMC/SD driver for RDA platform"); +MODULE_ALIAS("platform:rda-mmc"); --=20 2.51.0 From nobody Thu Oct 2 13:03:51 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96933343202; Tue, 16 Sep 2025 20:25:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054326; cv=none; b=CYcg4Ro9ETHP9BgFtcziy32+sSXUrJRKLIH6p7mdY/cbJsglJtjLI/vHOPvRXZTXXGilgGR1eXG0msHDam9P1QMz8rCWTi8wRo4mPIPcm7Z5heXzeO0qCGuYNdN473NAhImcsIwMkGWHQsBX7mSy4+R5bGUlmlnqsla6vssOBGw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054326; c=relaxed/simple; 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Tue, 16 Sep 2025 20:25:26 +0000 (UTC) From: Dang Huynh via B4 Relay Date: Wed, 17 Sep 2025 03:25:20 +0700 Subject: [PATCH 23/25] dts: unisoc: rda8810pl: Add SDMMC controllers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-rda8810pl-drivers-v1-23-9ca9184ca977@mainlining.org> References: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> In-Reply-To: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> To: Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Alexandre Belloni , Michael Turquette , Stephen Boyd , Philipp Zabel , Sebastian Reichel , Vinod Koul , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, dmaengine@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mmc@vger.kernel.org, Dang Huynh X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758054322; l=1669; i=dang.huynh@mainlining.org; s=20250917; h=from:subject:message-id; bh=+rjfqyC6diLcCcMZpXzmNwIY3Xd0ao4URhi7mY7MeOo=; b=g36+c8BMuiizyAkQU5g2SVhGELtdZOZL7VmLGm9NJ65TH2ylz89Z6tGkVFMsW4PUF6yXDm1fJ gSr5M9xIH80CvABquDEQg1EdtLnBDMt1j/TqnDGY86xGtT9UTnG1g4P X-Developer-Key: i=dang.huynh@mainlining.org; a=ed25519; pk=RyzH4CL4YU/ItXYUurA51EVBidfx4lIy8/E4EKRJCUk= X-Endpoint-Received: by B4 Relay for dang.huynh@mainlining.org/20250917 with auth_id=526 X-Original-From: Dang Huynh Reply-To: dang.huynh@mainlining.org From: Dang Huynh Add SDMMC1 and 2 controllers for the RDA8810PL platform. Signed-off-by: Dang Huynh --- arch/arm/boot/dts/unisoc/rda8810pl.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/unisoc/rda8810pl.dtsi b/arch/arm/boot/dts/un= isoc/rda8810pl.dtsi index 4b3ae19e9da41ee9ffa76dd4fff01824c07ce045..e68f8330ce2c4750b6944612bee= 03b42694137e4 100644 --- a/arch/arm/boot/dts/unisoc/rda8810pl.dtsi +++ b/arch/arm/boot/dts/unisoc/rda8810pl.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include =20 / { compatible =3D "rda,8810pl"; @@ -199,6 +200,30 @@ uart1: serial@0 { status =3D "disabled"; }; =20 + mmc1: mmc@50000 { + compatible =3D "rda,8810pl-mmc"; + reg =3D <0x50000 0x1000>; + interrupts =3D <3 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ap_syscon CLK_APB2>; + clock-names =3D "apb"; + resets =3D <&ap_syscon RST_APB2_SDMMC1>; + dmas =3D <&ifc IFC_SDMMC1_TX>, <&ifc IFC_SDMMC1_RX>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + + mmc2: mmc@60000 { + compatible =3D "rda,8810pl-mmc"; + reg =3D <0x60000 0x1000>; + interrupts =3D <4 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&ap_syscon CLK_APB2>; + clock-names =3D "apb"; + resets =3D <&ap_syscon RST_APB2_SDMMC2>; + dmas =3D <&ifc IFC_SDMMC2_TX>, <&ifc IFC_SDMMC2_RX>; + dma-names =3D "tx", "rx"; + status =3D "disabled"; + }; + uart2: serial@10000 { compatible =3D "rda,8810pl-uart"; reg =3D <0x10000 0x1000>; --=20 2.51.0 From nobody Thu Oct 2 13:03:51 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A723B34AAEA; Tue, 16 Sep 2025 20:25:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054326; cv=none; b=t4IEB2jwEPStCz9DA9iY5NE4xyAH4uw/KDZ+8i6t41mb306FXV/jJ9iA6SMlSMpRNsgtYHjG/14VLeuBTvD22Vh/UhYZqvzJ9HkwLzEhRqhAIRam+whT4i2ISpBLczqh2DU2d8r1EABPsm+AtdPDWVOQ/7wLmJBbU4TYak2WpDM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054326; c=relaxed/simple; bh=egTQGUBp0zFp2qNCGSUCro/O1z1FHKCYNAt7sLfWf4g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=r1Dt8btQG13DijgjcMMmo21zj9V+nfGeW5EEyQMn2pChCDri2GJPSUT4hETwJqanfV3oK1tMvIYQlnQEXGgApQkD4KgxS3B/KEtFqc1kffkLCrbjWHotIp/z7Coo85l80cXkHbW5mSSHVlNS4vrZd08YWnBPMsciMak9eVzgVYI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PN8jXzDi; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PN8jXzDi" Received: by smtp.kernel.org (Postfix) with ESMTPS id 71FE2C4AF4D; Tue, 16 Sep 2025 20:25:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758054326; bh=egTQGUBp0zFp2qNCGSUCro/O1z1FHKCYNAt7sLfWf4g=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=PN8jXzDiDi9RozSEc6nSjwEzFHkYUrxdOnlOCyBKdZRd3FeqaHOj7f9TSeGhDbDPQ Bh+pruy+oFlyn8G66wx9fSMwzO3BB+TsMB1T/9ciN9wjtWYhURBu5oJ/ncynx4l4up GTXS36TSR0vmOTjHOo+AMpbGkL42nXNg5hK1n9q9mIc5qwtlQlHbpqUWPLThUsix5w MF5bqD6KbunnstwbY91QvngVbXPdwSBbTjFMBCf64FdwFNunRQMBm5M9If9iZmMPmr FBoeEHUqRWxzic7nngnRXOFUyf3NKkh5Y+HraPxrIF/9jR5Kre2Rs7pbkdgfhpDA5n 5aZBo5+WDL+9w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63D2BCAC5A0; Tue, 16 Sep 2025 20:25:26 +0000 (UTC) From: Dang Huynh via B4 Relay Date: Wed, 17 Sep 2025 03:25:21 +0700 Subject: [PATCH 24/25] dts: unisoc: orangepi-2g: Enable SD Card Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-rda8810pl-drivers-v1-24-9ca9184ca977@mainlining.org> References: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> In-Reply-To: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> To: Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Alexandre Belloni , Michael Turquette , Stephen Boyd , Philipp Zabel , Sebastian Reichel , Vinod Koul , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, dmaengine@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mmc@vger.kernel.org, Dang Huynh X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758054322; l=1448; i=dang.huynh@mainlining.org; s=20250917; h=from:subject:message-id; bh=iqvLAp/eBqg4tchfSTl6yDHm7EVu5zj7yTK/oizm9Es=; b=QXCXdxinmO64Z8OEcHD6iLAWXpR3hIxrGFI6QsUVZCxUpj/VSQLgKvdaeJIkNysS7nwTiLnj9 xsF1lHezVDzAWUeqcnf8tySkrThcdRIcADq/RFZ6wAUb/o0O+FlLD6O X-Developer-Key: i=dang.huynh@mainlining.org; a=ed25519; pk=RyzH4CL4YU/ItXYUurA51EVBidfx4lIy8/E4EKRJCUk= X-Endpoint-Received: by B4 Relay for dang.huynh@mainlining.org/20250917 with auth_id=526 X-Original-From: Dang Huynh Reply-To: dang.huynh@mainlining.org From: Dang Huynh Since we have a SDMMC controller, we can use the SD card slot on the Orange Pi 2G-IOT. Signed-off-by: Dang Huynh --- .../boot/dts/unisoc/rda8810pl-orangepi-2g-iot.dts | 20 ++++++++++++++++= ++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/unisoc/rda8810pl-orangepi-2g-iot.dts b/arch/= arm/boot/dts/unisoc/rda8810pl-orangepi-2g-iot.dts index 46ccb9ad510c0df142b845d6fc5633b69c2298dd..f6b1a1485645f5714cdf14447cb= ee50e28e3c076 100644 --- a/arch/arm/boot/dts/unisoc/rda8810pl-orangepi-2g-iot.dts +++ b/arch/arm/boot/dts/unisoc/rda8810pl-orangepi-2g-iot.dts @@ -6,6 +6,7 @@ =20 /dts-v1/; =20 +#include #include "rda8810pl.dtsi" =20 / { @@ -27,6 +28,13 @@ memory@80000000 { reg =3D <0x80000000 0x10000000>; }; =20 + vdd_sdmmc: regulator-fixed { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_sdmmc"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + }; + uart_clk: uart-clk { compatible =3D "fixed-clock"; clock-frequency =3D <921600>; @@ -34,6 +42,18 @@ uart_clk: uart-clk { }; }; =20 +&mmc1 { + status =3D "okay"; + no-sdio; + no-mmc; + bus-width =3D <4>; + max-frequency =3D <30000000>; + cd-gpios =3D <&gpiob 4 GPIO_ACTIVE_LOW>; + vmmc-supply =3D <&vdd_sdmmc>; + rda,mclk-adj =3D /bits/ 8 <1>; + rda,mclk-inv; +}; + &uart3 { status =3D "okay"; clocks =3D <&uart_clk>; --=20 2.51.0 From nobody Thu Oct 2 13:03:51 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B7E613705BF; Tue, 16 Sep 2025 20:25:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054326; cv=none; b=MyCAsV6gUL+PIc3010s3xoDl8Qa+eRlZTVFjcxot1LrXKXH477LcfRycTJkh8A1ckg0N6O51wzJaKGC3ZXmFINWZPcj7aRoUpO4QA+wu/BGBIBHe8ZC3h65LtQxLaYjQBbkDBay6CIlvOQH4hDr3IPogNvPQaBIywCfHXOVQTxo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758054326; c=relaxed/simple; bh=D+uWf9FTrNZ5XT1lEEynxKDh80jQlO2m6fXZN2h5Ado=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MSyw3juPPeGYt/yYZNAXNWfCH2cNBmsD2xp8U/MMtwslsCpbgTls0+zt6MGz/hyjMY+PWB/idZuQ0Vf4OmdYzHzPL/mMQCmNMy4keT8qmBbTweOsjqyDO5PhlaY7Ls7l8Id9ZFYczIedsetBtA52iUOg+fED8UoLtmtuGx6Qr7I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=V20q9Xo0; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="V20q9Xo0" Received: by smtp.kernel.org (Postfix) with ESMTPS id 83E3EC16AAE; Tue, 16 Sep 2025 20:25:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758054326; bh=D+uWf9FTrNZ5XT1lEEynxKDh80jQlO2m6fXZN2h5Ado=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=V20q9Xo0lEzJgC99QAWvPWoDp0uogcKMcJnek1L79qqlUGGQ261tuwpDhAOgLsEHm +/tF95jnMFPm2QpOSoV67ZI5lFw8xviG0H5ygJTmY/jIc0ayFm4qy1Smb92PdWOs3o ugJ9YsmRmOHAua+SedbO9iv1k+pAu9lHK1bAuIuFvLrPn0i8Ksix1FFXfUpJTH7ZPD aMe21cQVNlTDpyTi9OT/pOOrdJ1zjAZ+7hhWfI/pJhnP8GcjDuS33zNyDIjA8tDN8N wZGfAIbRYlpZ26df4gGH5HWGXsJ+uF3r8TxCMPNtqr8VEUk3KspQoASsUrTCH2Xs3J c+Csr1N5RV1QA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72FF1CAC598; Tue, 16 Sep 2025 20:25:26 +0000 (UTC) From: Dang Huynh via B4 Relay Date: Wed, 17 Sep 2025 03:25:22 +0700 Subject: [PATCH 25/25] dts: unisoc: orangepi-i96: Enable SD Card Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-rda8810pl-drivers-v1-25-9ca9184ca977@mainlining.org> References: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> In-Reply-To: <20250917-rda8810pl-drivers-v1-0-9ca9184ca977@mainlining.org> To: Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Bartosz Golaszewski , Alexandre Belloni , Michael Turquette , Stephen Boyd , Philipp Zabel , Sebastian Reichel , Vinod Koul , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, dmaengine@vger.kernel.org, linux-hardening@vger.kernel.org, linux-mmc@vger.kernel.org, Dang Huynh X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1758054322; l=1432; i=dang.huynh@mainlining.org; s=20250917; h=from:subject:message-id; bh=qcvVxoXavmL/qbncOuYL4/AA9pp1j7YRntSv1snSw4A=; b=TmsiEoRuyNtRCinPmNRJPzsRLAOD+OfUVej7sM4TKuiv/lAlcCXOZO2yuj/YlaqpZKI2qoRoe gli9x6SUlcyCqeLBNQVNnFpfLrzGx9+fwjvYNgu+FokiMeRoJphyvZF X-Developer-Key: i=dang.huynh@mainlining.org; a=ed25519; pk=RyzH4CL4YU/ItXYUurA51EVBidfx4lIy8/E4EKRJCUk= X-Endpoint-Received: by B4 Relay for dang.huynh@mainlining.org/20250917 with auth_id=526 X-Original-From: Dang Huynh Reply-To: dang.huynh@mainlining.org From: Dang Huynh Since we have a SDMMC controller, we can use the SD card slot on the Orange Pi i96. Signed-off-by: Dang Huynh --- arch/arm/boot/dts/unisoc/rda8810pl-orangepi-i96.dts | 20 +++++++++++++++++= +++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/unisoc/rda8810pl-orangepi-i96.dts b/arch/arm= /boot/dts/unisoc/rda8810pl-orangepi-i96.dts index a1d61ef138d12bb3ecb4b24513cc1a7dfbac3107..fbb7b5be62051627e80d940cb5e= 5ccff9047c13c 100644 --- a/arch/arm/boot/dts/unisoc/rda8810pl-orangepi-i96.dts +++ b/arch/arm/boot/dts/unisoc/rda8810pl-orangepi-i96.dts @@ -6,6 +6,7 @@ =20 /dts-v1/; =20 +#include #include "rda8810pl.dtsi" =20 / { @@ -27,6 +28,13 @@ memory@80000000 { reg =3D <0x80000000 0x10000000>; }; =20 + vdd_sdmmc: regulator-fixed { + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_sdmmc"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + }; + uart_clk: uart-clk { compatible =3D "fixed-clock"; clock-frequency =3D <921600>; @@ -34,6 +42,18 @@ uart_clk: uart-clk { }; }; =20 +&mmc1 { + status =3D "okay"; + no-sdio; + no-mmc; + bus-width =3D <4>; + max-frequency =3D <30000000>; + cd-gpios =3D <&gpiob 4 GPIO_ACTIVE_LOW>; + vmmc-supply =3D <&vdd_sdmmc>; + rda,mclk-adj =3D /bits/ 8 <1>; + rda,mclk-inv; +}; + &uart3 { status =3D "okay"; clocks =3D <&uart_clk>; --=20 2.51.0