From nobody Thu Oct 2 10:39:58 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9702912B73 for ; Thu, 18 Sep 2025 00:43:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758156212; cv=none; b=PV9DWBOTHcjtNtAfGqwAVo6bjx4Dzm2OmztYkg7MIerZL6CEDtCkzK+wosqJG+VmatE3EQd0cigMqTrDlZaciFpK63veyqr+tgJd1kuoQ8wXJCpfjA1mESS836Tkcc3EexzzU4pMX/FEHN5MCIpkI9GPCyn4d7/MSs9jA3Xw7aI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758156212; c=relaxed/simple; bh=/0mpBbdAEWX/vOdWoDChg/5XjulmnR5K1jdXZOMdla0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TepJZoSe4tqN4UV+W+ug9ATrImJP/ysITnC4yRJ7gwyxPEGGrfqLsrFbjEbzYbv0lCAbQ2ueHKv5cxxmS/U77LagvDyfLlDEI0ZYWUqc9cMjfI9JSuVDbDEGiRbAwPw3CRMBaQujFHnDBEI6d3A3dKNYyayXiC/ijZZ8JpTXOSg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=ljWOjq5D; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="ljWOjq5D" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1758156208; bh=/0mpBbdAEWX/vOdWoDChg/5XjulmnR5K1jdXZOMdla0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=ljWOjq5D83YR6fnv5Sipc6h1icUQO5e9fk3y2zaAG8JVkJbr4j1nObFFgWI9Eea+F hDL4iyFj5CBWhCSXiCg4XcIf3HTjZnXGCf9MzrtMmUt3ayD8uz9xyF2pW7vIKMrdcZ IqLsOhxyX6br0BFuS5RHpm6EHk33OQMOj6m4uSIYtlYP8M6a7wqd0nXqqdM97GohZd SQ3KXCkCVHSFITar9aVb/poyzudc2QXeH9nWD3NkM5IhG09yYPDRo9s7Axajm0ESxc wPqwc7TKNEq3SBPvPNvTTT65JwM+fmkgydfkodJ9bCfCS0zOF/SfADzSofFLTD6XkS GRZAWeSQTFOUA== Received: from [127.0.1.1] (unknown [IPv6:2600:4041:5b1a:9400:62f0:406e:ac79:4a96]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by bali.collaboradmins.com (Postfix) with ESMTPSA id E666917E0147; Thu, 18 Sep 2025 02:43:21 +0200 (CEST) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Wed, 17 Sep 2025 20:43:10 -0400 Subject: [PATCH RFC v2 01/20] drm/crtc: Add color pipeline to CRTC state Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-mtk-post-blend-color-pipeline-v2-1-ac4471b44758@collabora.com> References: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> In-Reply-To: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Haneen Mohammed , Melissa Wen Cc: Alex Hung , wayland-devel@lists.freedesktop.org, harry.wentland@amd.com, leo.liu@amd.com, ville.syrjala@linux.intel.com, pekka.paalanen@collabora.com, contact@emersion.fr, mwen@igalia.com, jadahl@redhat.com, sebastian.wick@redhat.com, shashank.sharma@amd.com, agoins@nvidia.com, joshua@froggi.es, mdaenzer@redhat.com, aleixpol@kde.org, xaver.hugl@gmail.com, victoria@system76.com, uma.shankar@intel.com, quic_naseer@quicinc.com, quic_cbraga@quicinc.com, quic_abhinavk@quicinc.com, marcan@marcan.st, Liviu.Dudau@arm.com, sashamcintosh@google.com, chaitanya.kumar.borah@intel.com, louis.chauvet@bootlin.com, mcanal@igalia.com, kernel@collabora.com, daniels@collabora.com, leandro.ribeiro@collabora.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Simona Vetter X-Mailer: b4 0.14.2 Add a color pipeline to the CRTC state to allow post-blend color pipelines. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Harry Wentland Reviewed-by: Louis Chauvet --- include/drm/drm_crtc.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index caa56e039da2a748cf40ebf45b37158acda439d9..77c0c04a5910a2263923e06cf37= 535697e20e1c9 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -274,6 +274,14 @@ struct drm_crtc_state { */ struct drm_property_blob *gamma_lut; =20 + /** + * @color_pipeline: + * + * The first colorop of the active color pipeline, or NULL, if no + * color pipeline is active. + */ + struct drm_colorop *color_pipeline; + /** * @target_vblank: * --=20 2.50.1 From nobody Thu Oct 2 10:39:58 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69DCE12B73 for ; Thu, 18 Sep 2025 00:43:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 18 Sep 2025 02:43:29 +0200 (CEST) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Wed, 17 Sep 2025 20:43:11 -0400 Subject: [PATCH RFC v2 02/20] drm/colorop: Allow parenting colorop to CRTC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-mtk-post-blend-color-pipeline-v2-2-ac4471b44758@collabora.com> References: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> In-Reply-To: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Haneen Mohammed , Melissa Wen Cc: Alex Hung , wayland-devel@lists.freedesktop.org, harry.wentland@amd.com, leo.liu@amd.com, ville.syrjala@linux.intel.com, pekka.paalanen@collabora.com, contact@emersion.fr, mwen@igalia.com, jadahl@redhat.com, sebastian.wick@redhat.com, shashank.sharma@amd.com, agoins@nvidia.com, joshua@froggi.es, mdaenzer@redhat.com, aleixpol@kde.org, xaver.hugl@gmail.com, victoria@system76.com, uma.shankar@intel.com, quic_naseer@quicinc.com, quic_cbraga@quicinc.com, quic_abhinavk@quicinc.com, marcan@marcan.st, Liviu.Dudau@arm.com, sashamcintosh@google.com, chaitanya.kumar.borah@intel.com, louis.chauvet@bootlin.com, mcanal@igalia.com, kernel@collabora.com, daniels@collabora.com, leandro.ribeiro@collabora.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Simona Vetter X-Mailer: b4 0.14.2 In order to allow for post-blend color pipelines, colorops need to be assigned to a crtc rather than a plane. Add a crtc to the colorop struct to enable this. Either the plane or the crtc will be set for any given colorop depending on whether it is part of a pre- or post-blend color pipeline. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Harry Wentland Reviewed-by: Louis Chauvet --- include/drm/drm_colorop.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/include/drm/drm_colorop.h b/include/drm/drm_colorop.h index d61c6c40e47162cb8b1e7db58b6746c43ac5d202..7a4e0d0c4a3d594abecef304b1d= 5990434cdb231 100644 --- a/include/drm/drm_colorop.h +++ b/include/drm/drm_colorop.h @@ -206,10 +206,16 @@ struct drm_colorop { /** * @plane: * - * The plane on which the colorop sits. A drm_colorop is always unique - * to a plane. + * The plane on which the colorop sits if it is a pre-blend colorop. + * In this case it is unique to the plane. + * + * @crtc: + * + * The CRTC on which the colorop sits if it is a post-blend colorop. + * In this case it is unique to the CRTC. */ struct drm_plane *plane; + struct drm_crtc *crtc; =20 /** * @state: --=20 2.50.1 From nobody Thu Oct 2 10:39:58 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 961CC4315A for ; Thu, 18 Sep 2025 00:43:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758156226; cv=none; b=sNeyJcUAQC60bXhe9ZJp8P4WUoDUqwHgFY9SB1fYdC8pgBbbmSCswYVPGgQeyiGxUEE0U/klP3ZrfsWqxMQX38nmoFZICGHkNUp9MagfTRqP6esNrVD7EiClWK9Ardc+lV3ZUoSBOSxsDbJuhIOpjCEHCVwImqyi4QNbNHcmflg= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-mtk-post-blend-color-pipeline-v2-3-ac4471b44758@collabora.com> References: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> In-Reply-To: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Haneen Mohammed , Melissa Wen Cc: Alex Hung , wayland-devel@lists.freedesktop.org, harry.wentland@amd.com, leo.liu@amd.com, ville.syrjala@linux.intel.com, pekka.paalanen@collabora.com, contact@emersion.fr, mwen@igalia.com, jadahl@redhat.com, sebastian.wick@redhat.com, shashank.sharma@amd.com, agoins@nvidia.com, joshua@froggi.es, mdaenzer@redhat.com, aleixpol@kde.org, xaver.hugl@gmail.com, victoria@system76.com, uma.shankar@intel.com, quic_naseer@quicinc.com, quic_cbraga@quicinc.com, quic_abhinavk@quicinc.com, marcan@marcan.st, Liviu.Dudau@arm.com, sashamcintosh@google.com, chaitanya.kumar.borah@intel.com, louis.chauvet@bootlin.com, mcanal@igalia.com, kernel@collabora.com, daniels@collabora.com, leandro.ribeiro@collabora.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Simona Vetter X-Mailer: b4 0.14.2 In preparation for sharing the initialization code for the color pipeline property between pre- and post-blend color pipelines, factor out the common initialization to a separate function. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Harry Wentland Reviewed-by: Louis Chauvet --- drivers/gpu/drm/drm_crtc.c | 44 +++++++++++++++++++++++++++++++++= ++++ drivers/gpu/drm/drm_crtc_internal.h | 5 +++++ drivers/gpu/drm/drm_plane.c | 36 +++++------------------------- 3 files changed, 54 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 46655339003db2a1b43441434839e26f61d79b4e..94e60cffd29972aa979ac2f1932= be7a6a97f3ada 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -959,3 +959,47 @@ bool drm_crtc_in_clone_mode(struct drm_crtc_state *crt= c_state) return hweight32(crtc_state->encoder_mask) > 1; } EXPORT_SYMBOL(drm_crtc_in_clone_mode); + +struct drm_property * +drm_common_create_color_pipeline_property(struct drm_device *dev, struct d= rm_mode_object *obj, + const struct drm_prop_enum_list *pipelines, + int num_pipelines) +{ + struct drm_prop_enum_list *all_pipelines; + struct drm_property *prop; + int len =3D 0; + int i; + + all_pipelines =3D kcalloc(num_pipelines + 1, + sizeof(*all_pipelines), + GFP_KERNEL); + + if (!all_pipelines) { + drm_err(dev, "failed to allocate color pipeline\n"); + return ERR_PTR(-ENOMEM); + } + + /* Create default Bypass color pipeline */ + all_pipelines[len].type =3D 0; + all_pipelines[len].name =3D "Bypass"; + len++; + + /* Add all other color pipelines */ + for (i =3D 0; i < num_pipelines; i++, len++) { + all_pipelines[len].type =3D pipelines[i].type; + all_pipelines[len].name =3D pipelines[i].name; + } + + prop =3D drm_property_create_enum(dev, DRM_MODE_PROP_ATOMIC, + "COLOR_PIPELINE", + all_pipelines, len); + if (IS_ERR(prop)) { + kfree(all_pipelines); + return prop; + } + + drm_object_attach_property(obj, prop, 0); + + kfree(all_pipelines); + return prop; +} diff --git a/drivers/gpu/drm/drm_crtc_internal.h b/drivers/gpu/drm/drm_crtc= _internal.h index c094092296448093c5cd192ecdc8ea9a50769c90..e3dbdcbfa385b940ec0b5476add= e6146fe4afde1 100644 --- a/drivers/gpu/drm/drm_crtc_internal.h +++ b/drivers/gpu/drm/drm_crtc_internal.h @@ -35,6 +35,7 @@ #ifndef __DRM_CRTC_INTERNAL_H__ #define __DRM_CRTC_INTERNAL_H__ =20 +#include #include #include =20 @@ -79,6 +80,10 @@ int drm_crtc_check_viewport(const struct drm_crtc *crtc, int drm_crtc_register_all(struct drm_device *dev); void drm_crtc_unregister_all(struct drm_device *dev); int drm_crtc_force_disable(struct drm_crtc *crtc); +struct drm_property * +drm_common_create_color_pipeline_property(struct drm_device *dev, struct d= rm_mode_object *obj, + const struct drm_prop_enum_list *pipelines, + int num_pipelines); =20 struct dma_fence *drm_crtc_create_fence(struct drm_crtc *crtc); =20 diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c index f6cfa8ac090c7bc49c7f276993bba7e9800da140..60dbfcab495600dd44c15260a1f= a6135db59c6e2 100644 --- a/drivers/gpu/drm/drm_plane.c +++ b/drivers/gpu/drm/drm_plane.c @@ -1839,43 +1839,17 @@ int drm_plane_create_color_pipeline_property(struct= drm_plane *plane, const struct drm_prop_enum_list *pipelines, int num_pipelines) { - struct drm_prop_enum_list *all_pipelines; struct drm_property *prop; - int len =3D 0; - int i; - - all_pipelines =3D kcalloc(num_pipelines + 1, - sizeof(*all_pipelines), - GFP_KERNEL); - - if (!all_pipelines) { - drm_err(plane->dev, "failed to allocate color pipeline\n"); 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Thu, 18 Sep 2025 02:43:42 +0200 (CEST) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Wed, 17 Sep 2025 20:43:13 -0400 Subject: [PATCH RFC v2 04/20] drm/crtc: Add COLOR_PIPELINE property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-mtk-post-blend-color-pipeline-v2-4-ac4471b44758@collabora.com> References: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> In-Reply-To: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Haneen Mohammed , Melissa Wen Cc: Alex Hung , wayland-devel@lists.freedesktop.org, harry.wentland@amd.com, leo.liu@amd.com, ville.syrjala@linux.intel.com, pekka.paalanen@collabora.com, contact@emersion.fr, mwen@igalia.com, jadahl@redhat.com, sebastian.wick@redhat.com, shashank.sharma@amd.com, agoins@nvidia.com, joshua@froggi.es, mdaenzer@redhat.com, aleixpol@kde.org, xaver.hugl@gmail.com, victoria@system76.com, uma.shankar@intel.com, quic_naseer@quicinc.com, quic_cbraga@quicinc.com, quic_abhinavk@quicinc.com, marcan@marcan.st, Liviu.Dudau@arm.com, sashamcintosh@google.com, chaitanya.kumar.borah@intel.com, louis.chauvet@bootlin.com, mcanal@igalia.com, kernel@collabora.com, daniels@collabora.com, leandro.ribeiro@collabora.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Simona Vetter X-Mailer: b4 0.14.2 Add a COLOR_PIPELINE property to the CRTC to allow userspace to set a post-blend color pipeline analogously to how pre-blend color pipelines are set on planes. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Harry Wentland --- drivers/gpu/drm/drm_atomic_uapi.c | 49 +++++++++++++++++++++++++++++++++++= ---- drivers/gpu/drm/drm_crtc.c | 33 ++++++++++++++++++++++++++ include/drm/drm_atomic_uapi.h | 2 ++ include/drm/drm_crtc.h | 11 +++++++++ 4 files changed, 91 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic= _uapi.c index b7cc6945864274bedd21dd5b73494f9aae216888..063c142fd9b656e228cfc660d00= 5a3fbb4640d32 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -287,6 +287,33 @@ drm_atomic_set_colorop_for_plane(struct drm_plane_stat= e *plane_state, } EXPORT_SYMBOL(drm_atomic_set_colorop_for_plane); =20 +/** + * drm_atomic_set_colorop_for_crtc - set colorop for crtc + * @crtc_state: atomic state object for the crtc + * @colorop: colorop to use for the crtc + * + * Helper function to select the color pipeline on a crtc by setting + * it to the first drm_colorop element of the pipeline. + */ +void +drm_atomic_set_colorop_for_crtc(struct drm_crtc_state *crtc_state, + struct drm_colorop *colorop) +{ + struct drm_crtc *crtc =3D crtc_state->crtc; + + if (colorop) + drm_dbg_atomic(crtc->dev, + "Set [COLOROP:%d] for [CRTC:%d:%s] state %p\n", + colorop->base.id, crtc->base.id, crtc->name, + crtc_state); + else + drm_dbg_atomic(crtc->dev, + "Set [NOCOLOROP] for [CRTC:%d:%s] state %p\n", + crtc->base.id, crtc->name, crtc_state); + + crtc_state->color_pipeline =3D colorop; +} +EXPORT_SYMBOL(drm_atomic_set_colorop_for_crtc); =20 /** * drm_atomic_set_crtc_for_connector - set CRTC for connector @@ -396,8 +423,8 @@ static s32 __user *get_out_fence_for_connector(struct d= rm_atomic_state *state, } =20 static int drm_atomic_crtc_set_property(struct drm_crtc *crtc, - struct drm_crtc_state *state, struct drm_property *property, - uint64_t val) + struct drm_crtc_state *state, struct drm_file *file_priv, + struct drm_property *property, uint64_t val) { struct drm_device *dev =3D crtc->dev; struct drm_mode_config *config =3D &dev->mode_config; @@ -406,7 +433,17 @@ static int drm_atomic_crtc_set_property(struct drm_crt= c *crtc, =20 if (property =3D=3D config->prop_active) state->active =3D val; - else if (property =3D=3D config->prop_mode_id) { + else if (property =3D=3D crtc->color_pipeline_property) { + /* find DRM colorop object */ + struct drm_colorop *colorop =3D NULL; + + colorop =3D drm_colorop_find(dev, file_priv, val); + + if (val && !colorop) + return -EACCES; + + drm_atomic_set_colorop_for_crtc(state, colorop); + } else if (property =3D=3D config->prop_mode_id) { struct drm_property_blob *mode =3D drm_property_lookup_blob(dev, val); ret =3D drm_atomic_set_mode_prop_for_crtc(state, mode); @@ -487,6 +524,8 @@ drm_atomic_crtc_get_property(struct drm_crtc *crtc, *val =3D 0; else if (property =3D=3D crtc->scaling_filter_property) *val =3D state->scaling_filter; + else if (property =3D=3D crtc->color_pipeline_property) + *val =3D (state->color_pipeline) ? state->color_pipeline->base.id : 0; else if (crtc->funcs->atomic_get_property) return crtc->funcs->atomic_get_property(crtc, state, property, val); else { @@ -1047,6 +1086,8 @@ int drm_atomic_get_property(struct drm_mode_object *o= bj, =20 if (colorop->plane) WARN_ON(!drm_modeset_is_locked(&colorop->plane->mutex)); + else if (colorop->crtc) + WARN_ON(!drm_modeset_is_locked(&colorop->crtc->mutex)); =20 ret =3D drm_atomic_colorop_get_property(colorop, colorop->state, property, val); @@ -1204,7 +1245,7 @@ int drm_atomic_set_property(struct drm_atomic_state *= state, } =20 ret =3D drm_atomic_crtc_set_property(crtc, - crtc_state, prop, prop_value); + crtc_state, file_priv, prop, prop_value); break; } case DRM_MODE_OBJECT_PLANE: { diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index 94e60cffd29972aa979ac2f1932be7a6a97f3ada..94238163ff1254c721df39c030b= c99a31d3bb92a 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -1003,3 +1003,36 @@ drm_common_create_color_pipeline_property(struct drm= _device *dev, struct drm_mod kfree(all_pipelines); return prop; } + +/** + * drm_crtc_create_color_pipeline_property - create a new color pipeline + * property + * + * @crtc: drm CRTC + * @pipelines: list of pipelines + * @num_pipelines: number of pipelines + * + * Create the COLOR_PIPELINE CRTC property to specify color pipelines on + * the CRTC. + * + * RETURNS: + * Zero for success or -errno + */ +int drm_crtc_create_color_pipeline_property(struct drm_crtc *crtc, + const struct drm_prop_enum_list *pipelines, + int num_pipelines) +{ + struct drm_property *prop; + + prop =3D drm_common_create_color_pipeline_property(crtc->dev, + &crtc->base, + pipelines, + num_pipelines); + if (IS_ERR(prop)) + return PTR_ERR(prop); + + crtc->color_pipeline_property =3D prop; + + return 0; +} +EXPORT_SYMBOL(drm_crtc_create_color_pipeline_property); diff --git a/include/drm/drm_atomic_uapi.h b/include/drm/drm_atomic_uapi.h index 4363155233267b93767c895fa6085544e2277442..4dc191f6f929d73deee9812025c= 48275a33cf770 100644 --- a/include/drm/drm_atomic_uapi.h +++ b/include/drm/drm_atomic_uapi.h @@ -52,6 +52,8 @@ void drm_atomic_set_fb_for_plane(struct drm_plane_state *= plane_state, struct drm_framebuffer *fb); void drm_atomic_set_colorop_for_plane(struct drm_plane_state *plane_state, struct drm_colorop *colorop); +void drm_atomic_set_colorop_for_crtc(struct drm_crtc_state *crtc_state, + struct drm_colorop *colorop); int __must_check drm_atomic_set_crtc_for_connector(struct drm_connector_state *conn_state, struct drm_crtc *crtc); diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index 77c0c04a5910a2263923e06cf37535697e20e1c9..df03637ca25abd45e96b5944229= 297f776fd046d 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -1096,6 +1096,14 @@ struct drm_crtc { */ struct drm_property *scaling_filter_property; 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Thu, 18 Sep 2025 02:43:50 +0200 (CEST) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Wed, 17 Sep 2025 20:43:14 -0400 Subject: [PATCH RFC v2 05/20] drm: Introduce DRM_CAP_POST_BLEND_COLOR_PIPELINE Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-mtk-post-blend-color-pipeline-v2-5-ac4471b44758@collabora.com> References: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> In-Reply-To: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Haneen Mohammed , Melissa Wen Cc: Alex Hung , wayland-devel@lists.freedesktop.org, harry.wentland@amd.com, leo.liu@amd.com, ville.syrjala@linux.intel.com, pekka.paalanen@collabora.com, contact@emersion.fr, mwen@igalia.com, jadahl@redhat.com, sebastian.wick@redhat.com, shashank.sharma@amd.com, agoins@nvidia.com, joshua@froggi.es, mdaenzer@redhat.com, aleixpol@kde.org, xaver.hugl@gmail.com, victoria@system76.com, uma.shankar@intel.com, quic_naseer@quicinc.com, quic_cbraga@quicinc.com, quic_abhinavk@quicinc.com, marcan@marcan.st, Liviu.Dudau@arm.com, sashamcintosh@google.com, chaitanya.kumar.borah@intel.com, louis.chauvet@bootlin.com, mcanal@igalia.com, kernel@collabora.com, daniels@collabora.com, leandro.ribeiro@collabora.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Simona Vetter X-Mailer: b4 0.14.2 Add a new cap that drivers can set to signal they support post-blend color pipelines. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Harry Wentland Reviewed-by: Louis Chauvet --- drivers/gpu/drm/drm_ioctl.c | 3 +++ include/drm/drm_drv.h | 6 ++++++ include/uapi/drm/drm.h | 6 ++++++ 3 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c index ff193155129e7e863888d8958458978566b144f8..01592d10e3465ddceddef94bc41= 7f98d3ec12087 100644 --- a/drivers/gpu/drm/drm_ioctl.c +++ b/drivers/gpu/drm/drm_ioctl.c @@ -304,6 +304,9 @@ static int drm_getcap(struct drm_device *dev, void *dat= a, struct drm_file *file_ req->value =3D drm_core_check_feature(dev, DRIVER_ATOMIC) && dev->mode_config.async_page_flip; break; + case DRM_CAP_POST_BLEND_COLOR_PIPELINE: + req->value =3D drm_core_check_feature(dev, DRIVER_POST_BLEND_COLOR_PIPEL= INE); + break; default: return -EINVAL; } diff --git a/include/drm/drm_drv.h b/include/drm/drm_drv.h index 42fc085f986dee9261f8b08c4fc7d93b8d6d9769..6b0f4904e69766232283d430c25= 40d30afef850f 100644 --- a/include/drm/drm_drv.h +++ b/include/drm/drm_drv.h @@ -122,6 +122,12 @@ enum drm_driver_feature { * the cursor planes to work correctly). */ DRIVER_CURSOR_HOTSPOT =3D BIT(9), + /** + * @DRIVER_POST_BLEND_COLOR_PIPELINE: + * + * Driver supports post-blend color pipeline. + */ + DRIVER_POST_BLEND_COLOR_PIPELINE =3D BIT(10), =20 /* IMPORTANT: Below are all the legacy flags, add new ones above. */ =20 diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h index 27cc159c1d275c7a7fe057840ef792f30a582bb7..c6c53e57958e951204154ce41a6= 9696a6876f0e8 100644 --- a/include/uapi/drm/drm.h +++ b/include/uapi/drm/drm.h @@ -812,6 +812,12 @@ struct drm_gem_change_handle { * commits. */ #define DRM_CAP_ATOMIC_ASYNC_PAGE_FLIP 0x15 +/** + * DRM_CAP_POST_BLEND_COLOR_PIPELINE + * + * If set to 1, the driver supports post-blend color pipelines. + */ +#define DRM_CAP_POST_BLEND_COLOR_PIPELINE 0x16 =20 /* DRM_IOCTL_GET_CAP ioctl argument type */ struct drm_get_cap { --=20 2.50.1 From nobody Thu Oct 2 10:39:58 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24717201266 for ; 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Thu, 18 Sep 2025 02:43:57 +0200 (CEST) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Wed, 17 Sep 2025 20:43:15 -0400 Subject: [PATCH RFC v2 06/20] drm: Introduce DRM_CLIENT_CAP_POST_BLEND_COLOR_PIPELINE Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-mtk-post-blend-color-pipeline-v2-6-ac4471b44758@collabora.com> References: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> In-Reply-To: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Haneen Mohammed , Melissa Wen Cc: Alex Hung , wayland-devel@lists.freedesktop.org, harry.wentland@amd.com, leo.liu@amd.com, ville.syrjala@linux.intel.com, pekka.paalanen@collabora.com, contact@emersion.fr, mwen@igalia.com, jadahl@redhat.com, sebastian.wick@redhat.com, shashank.sharma@amd.com, agoins@nvidia.com, joshua@froggi.es, mdaenzer@redhat.com, aleixpol@kde.org, xaver.hugl@gmail.com, victoria@system76.com, uma.shankar@intel.com, quic_naseer@quicinc.com, quic_cbraga@quicinc.com, quic_abhinavk@quicinc.com, marcan@marcan.st, Liviu.Dudau@arm.com, sashamcintosh@google.com, chaitanya.kumar.borah@intel.com, louis.chauvet@bootlin.com, mcanal@igalia.com, kernel@collabora.com, daniels@collabora.com, leandro.ribeiro@collabora.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Simona Vetter X-Mailer: b4 0.14.2 Introduce DRM_CLIENT_CAP_POST_BLEND_COLOR_PIPELINE which a DRM client can set to enable the usage of post-blend color pipelines instead of the now deprecated CRTC color management properties: "GAMMA_LUT", "DEGAMMA_LUT" and "CTM". Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Harry Wentland Reviewed-by: Louis Chauvet --- drivers/gpu/drm/drm_atomic_uapi.c | 15 +++++++++++++++ drivers/gpu/drm/drm_connector.c | 1 + drivers/gpu/drm/drm_crtc_internal.h | 1 + drivers/gpu/drm/drm_ioctl.c | 9 +++++++++ drivers/gpu/drm/drm_mode_object.c | 9 +++++++++ include/drm/drm_file.h | 7 +++++++ include/uapi/drm/drm.h | 19 +++++++++++++++++++ 7 files changed, 61 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic= _uapi.c index 063c142fd9b656e228cfc660d005a3fbb4640d32..f5125fa3fa28ff2a6ff07fd7cf0= 7d4bdf77ab738 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -452,6 +452,11 @@ static int drm_atomic_crtc_set_property(struct drm_crt= c *crtc, } else if (property =3D=3D config->prop_vrr_enabled) { state->vrr_enabled =3D val; } else if (property =3D=3D config->degamma_lut_property) { + if (file_priv->post_blend_color_pipeline) { + drm_dbg_atomic(dev, + "Setting DEGAMMA_LUT CRTC property not permitted with DRM_CLIENT_CAP_P= OST_BLEND_COLOR_PIPELINE client cap\n"); + return -EINVAL; + } ret =3D drm_property_replace_blob_from_id(dev, &state->degamma_lut, val, @@ -460,6 +465,11 @@ static int drm_atomic_crtc_set_property(struct drm_crt= c *crtc, state->color_mgmt_changed |=3D replaced; return ret; } else if (property =3D=3D config->ctm_property) { + if (file_priv->post_blend_color_pipeline) { + drm_dbg_atomic(dev, + "Setting CTM CRTC property not permitted with DRM_CLIENT_CAP_POST_BLEN= D_COLOR_PIPELINE client cap\n"); + return -EINVAL; + } ret =3D drm_property_replace_blob_from_id(dev, &state->ctm, val, @@ -468,6 +478,11 @@ static int drm_atomic_crtc_set_property(struct drm_crt= c *crtc, state->color_mgmt_changed |=3D replaced; return ret; } else if (property =3D=3D config->gamma_lut_property) { + if (file_priv->post_blend_color_pipeline) { + drm_dbg_atomic(dev, + "Setting GAMMA_LUT CRTC property not permitted with DRM_CLIENT_CAP_POS= T_BLEND_COLOR_PIPELINE client cap\n"); + return -EINVAL; + } ret =3D drm_property_replace_blob_from_id(dev, &state->gamma_lut, val, diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connecto= r.c index 4d6dc9ebfdb5bc730b1aff7a184448af7b93f078..f58cfd2131139ff3e613adc4dbb= 9ddbedf724dc7 100644 --- a/drivers/gpu/drm/drm_connector.c +++ b/drivers/gpu/drm/drm_connector.c @@ -3440,6 +3440,7 @@ int drm_mode_getconnector(struct drm_device *dev, voi= d *data, */ ret =3D drm_mode_object_get_properties(&connector->base, file_priv->atomi= c, file_priv->plane_color_pipeline, + file_priv->post_blend_color_pipeline, (uint32_t __user *)(unsigned long)(out_resp->props_ptr), (uint64_t __user *)(unsigned long)(out_resp->prop_values_ptr), &out_resp->count_props); diff --git a/drivers/gpu/drm/drm_crtc_internal.h b/drivers/gpu/drm/drm_crtc= _internal.h index e3dbdcbfa385b940ec0b5476adde6146fe4afde1..c53f154e5392a10c326c844b732= 1666275f9ac02 100644 --- a/drivers/gpu/drm/drm_crtc_internal.h +++ b/drivers/gpu/drm/drm_crtc_internal.h @@ -169,6 +169,7 @@ void drm_mode_object_unregister(struct drm_device *dev, struct drm_mode_object *object); int drm_mode_object_get_properties(struct drm_mode_object *obj, bool atomi= c, bool plane_color_pipeline, + bool post_blend_color_pipeline, uint32_t __user *prop_ptr, uint64_t __user *prop_values, uint32_t *arg_count_props); diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c index 01592d10e3465ddceddef94bc417f98d3ec12087..ea9600f5392f520a2b42ba7ef36= 3d2f08ce19812 100644 --- a/drivers/gpu/drm/drm_ioctl.c +++ b/drivers/gpu/drm/drm_ioctl.c @@ -383,6 +383,15 @@ drm_setclientcap(struct drm_device *dev, void *data, s= truct drm_file *file_priv) return -EINVAL; file_priv->plane_color_pipeline =3D req->value; break; + case DRM_CLIENT_CAP_POST_BLEND_COLOR_PIPELINE: + if (!file_priv->atomic) + return -EINVAL; + if (req->value > 1) + return -EINVAL; + if (!drm_core_check_feature(dev, DRIVER_POST_BLEND_COLOR_PIPELINE)) + return -EINVAL; + file_priv->post_blend_color_pipeline =3D req->value; + break; default: return -EINVAL; } diff --git a/drivers/gpu/drm/drm_mode_object.c b/drivers/gpu/drm/drm_mode_o= bject.c index b45d501b10c868c6d9b7a5a8760eadbd7b372a6a..5e6c3de9456b997985142a68b9c= ef57771a58bdc 100644 --- a/drivers/gpu/drm/drm_mode_object.c +++ b/drivers/gpu/drm/drm_mode_object.c @@ -388,6 +388,7 @@ EXPORT_SYMBOL(drm_object_property_get_default_value); /* helper for getconnector and getproperties ioctls */ int drm_mode_object_get_properties(struct drm_mode_object *obj, bool atomi= c, bool plane_color_pipeline, + bool post_blend_color_pipeline, uint32_t __user *prop_ptr, uint64_t __user *prop_values, uint32_t *arg_count_props) @@ -416,6 +417,13 @@ int drm_mode_object_get_properties(struct drm_mode_obj= ect *obj, bool atomic, continue; } =20 + if (!post_blend_color_pipeline && obj->type =3D=3D DRM_MODE_OBJECT_CRTC)= { + struct drm_crtc *crtc =3D obj_to_crtc(obj); + + if (prop =3D=3D crtc->color_pipeline_property) + continue; + } + if (*arg_count_props > count) { ret =3D __drm_object_property_get_value(obj, prop, &val); if (ret) @@ -475,6 +483,7 @@ int drm_mode_obj_get_properties_ioctl(struct drm_device= *dev, void *data, =20 ret =3D drm_mode_object_get_properties(obj, file_priv->atomic, file_priv->plane_color_pipeline, + file_priv->post_blend_color_pipeline, (uint32_t __user *)(unsigned long)(arg->props_ptr), (uint64_t __user *)(unsigned long)(arg->prop_values_ptr), &arg->count_props); diff --git a/include/drm/drm_file.h b/include/drm/drm_file.h index 1a3018e4a537b3341acb50187d47371f6b781b9d..42b9a43baa18079af8ec2ea5b14= 84b23c497beb0 100644 --- a/include/drm/drm_file.h +++ b/include/drm/drm_file.h @@ -213,6 +213,13 @@ struct drm_file { */ bool plane_color_pipeline; =20 + /** + * @post_blend_color_pipeline: + * + * True if client understands post-blend color pipelines + */ + bool post_blend_color_pipeline; + /** * @was_master: * diff --git a/include/uapi/drm/drm.h b/include/uapi/drm/drm.h index c6c53e57958e951204154ce41a69696a6876f0e8..f9ac10b3e4876f71005a87dedef= a4aed320566f0 100644 --- a/include/uapi/drm/drm.h +++ b/include/uapi/drm/drm.h @@ -927,6 +927,25 @@ struct drm_get_cap { */ #define DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE 7 =20 +/** + * DRM_CLIENT_CAP_POST_BLEND_COLOR_PIPELINE + * + * If set to 1 the DRM core will allow setting the COLOR_PIPELINE + * property on a &drm_crtc, as well as drm_colorop properties. + * + * Setting of these crtc properties will be rejected when this client + * cap is set: + * - GAMMA_LUT + * - DEGAMMA_LUT + * - CTM + * + * The client must enable &DRM_CLIENT_CAP_ATOMIC first. + * + * This client cap can only be set if the driver sets the corresponding dr= iver + * cap &DRM_CAP_POST_BLEND_COLOR_PIPELINE. + */ +#define DRM_CLIENT_CAP_POST_BLEND_COLOR_PIPELINE 8 + /* DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */ struct drm_set_client_cap { __u64 capability; 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Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Harry Wentland Reviewed-by: Louis Chauvet --- drivers/gpu/drm/drm_atomic_uapi.c | 1 + include/drm/drm_atomic.h | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic= _uapi.c index f5125fa3fa28ff2a6ff07fd7cf07d4bdf77ab738..56a440a9390c7730c4c41b491f2= 9b933a2bbb889 100644 --- a/drivers/gpu/drm/drm_atomic_uapi.c +++ b/drivers/gpu/drm/drm_atomic_uapi.c @@ -1660,6 +1660,7 @@ int drm_mode_atomic_ioctl(struct drm_device *dev, state->acquire_ctx =3D &ctx; state->allow_modeset =3D !!(arg->flags & DRM_MODE_ATOMIC_ALLOW_MODESET); state->plane_color_pipeline =3D file_priv->plane_color_pipeline; + state->post_blend_color_pipeline =3D file_priv->post_blend_color_pipeline; =20 retry: copied_objs =3D 0; diff --git a/include/drm/drm_atomic.h b/include/drm/drm_atomic.h index 678708df9cdb90b4266127193a92183069f18688..8c42c584aefbf0034b2163d9053= 8e80099b0dadb 100644 --- a/include/drm/drm_atomic.h +++ b/include/drm/drm_atomic.h @@ -482,6 +482,26 @@ struct drm_atomic_state { */ bool plane_color_pipeline : 1; =20 + /** + * @post_blend_color_pipeline: + * + * Indicates whether this atomic state originated with a client that + * set the DRM_CLIENT_CAP_POST_BLEND_COLOR_PIPELINE. + * + * Drivers and helper functions should use this to ignore legacy + * properties that are incompatible with the drm_crtc COLOR_PIPELINE + * behavior, such as: + * + * - GAMMA_LUT + * - DEGAMMA_LUT + * - GAMMA_LUT_SIZE + * - CTM + * + * or any other driver-specific properties that might affect pixel + * values. + */ + bool post_blend_color_pipeline : 1; + /** * @colorops: * --=20 2.50.1 From nobody Thu Oct 2 10:39:58 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0F411DFD96 for ; Thu, 18 Sep 2025 00:44:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; 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Thu, 18 Sep 2025 02:44:12 +0200 (CEST) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Wed, 17 Sep 2025 20:43:17 -0400 Subject: [PATCH RFC v2 08/20] drm/atomic: Print the color pipeline as part of the CRTC state print Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-mtk-post-blend-color-pipeline-v2-8-ac4471b44758@collabora.com> References: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> In-Reply-To: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Haneen Mohammed , Melissa Wen Cc: Alex Hung , wayland-devel@lists.freedesktop.org, harry.wentland@amd.com, leo.liu@amd.com, ville.syrjala@linux.intel.com, pekka.paalanen@collabora.com, contact@emersion.fr, mwen@igalia.com, jadahl@redhat.com, sebastian.wick@redhat.com, shashank.sharma@amd.com, agoins@nvidia.com, joshua@froggi.es, mdaenzer@redhat.com, aleixpol@kde.org, xaver.hugl@gmail.com, victoria@system76.com, uma.shankar@intel.com, quic_naseer@quicinc.com, quic_cbraga@quicinc.com, quic_abhinavk@quicinc.com, marcan@marcan.st, Liviu.Dudau@arm.com, sashamcintosh@google.com, chaitanya.kumar.borah@intel.com, louis.chauvet@bootlin.com, mcanal@igalia.com, kernel@collabora.com, daniels@collabora.com, leandro.ribeiro@collabora.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Simona Vetter X-Mailer: b4 0.14.2 Print the value of the color pipeline in the CRTC state as part of the CRTC state print. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Harry Wentland Reviewed-by: Louis Chauvet --- drivers/gpu/drm/drm_atomic.c | 8 +++++--- drivers/gpu/drm/drm_colorop.c | 26 ++++++++++++++++++++++++++ include/drm/drm_colorop.h | 3 +++ 3 files changed, 34 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index 3ab32fe7fe1cbf9057c3763d979638dce013d82b..6982c978dc530b838353ace60f7= 48660c3b4524d 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -472,6 +472,8 @@ static void drm_atomic_crtc_print_state(struct drm_prin= ter *p, drm_printf(p, "\tplane_mask=3D%x\n", state->plane_mask); drm_printf(p, "\tconnector_mask=3D%x\n", state->connector_mask); drm_printf(p, "\tencoder_mask=3D%x\n", state->encoder_mask); + drm_printf(p, "\tcolor-pipeline=3D%d\n", + state->color_pipeline ? state->color_pipeline->base.id : 0); drm_printf(p, "\tmode: " DRM_MODE_FMT "\n", DRM_MODE_ARG(&state->mode)); =20 if (crtc->funcs->atomic_print_state) @@ -617,7 +619,7 @@ drm_atomic_get_colorop_state(struct drm_atomic_state *s= tate, if (colorop_state) return colorop_state; =20 - ret =3D drm_modeset_lock(&colorop->plane->mutex, state->acquire_ctx); + ret =3D drm_colorop_modeset_lock(colorop, state->acquire_ctx); if (ret) return ERR_PTR(ret); =20 @@ -2004,10 +2006,10 @@ static void __drm_state_dump(struct drm_device *dev= , struct drm_printer *p, =20 list_for_each_entry(colorop, &config->colorop_list, head) { if (take_locks) - drm_modeset_lock(&colorop->plane->mutex, NULL); + drm_colorop_modeset_lock(colorop, NULL); drm_atomic_colorop_print_state(p, colorop->state); if (take_locks) - drm_modeset_unlock(&colorop->plane->mutex); + drm_colorop_modeset_unlock(colorop); } =20 list_for_each_entry(plane, &config->plane_list, head) { diff --git a/drivers/gpu/drm/drm_colorop.c b/drivers/gpu/drm/drm_colorop.c index a1b36cd488f0a014425a9192ffe5fcc4d2c1afaa..1384a259605fa4945aa74402901= 886d7e1fde0d1 100644 --- a/drivers/gpu/drm/drm_colorop.c +++ b/drivers/gpu/drm/drm_colorop.c @@ -24,6 +24,7 @@ * */ =20 +#include #include #include #include @@ -595,3 +596,28 @@ void drm_colorop_set_next_property(struct drm_colorop = *colorop, struct drm_color colorop->next =3D next; } EXPORT_SYMBOL(drm_colorop_set_next_property); + +int drm_colorop_modeset_lock(struct drm_colorop *colorop, struct drm_modes= et_acquire_ctx *ctx) +{ + if (colorop->plane) + return drm_modeset_lock(&colorop->plane->mutex, ctx); + + if (colorop->crtc) + return drm_modeset_lock(&colorop->crtc->mutex, ctx); + + drm_err(colorop->dev, "Dangling colorop, it must be attached to a plane o= r a CRTC\n"); + return -EINVAL; +} +EXPORT_SYMBOL(drm_colorop_modeset_lock); + + +void drm_colorop_modeset_unlock(struct drm_colorop *colorop) +{ + if (colorop->plane) + drm_modeset_unlock(&colorop->plane->mutex); + else if (colorop->crtc) + drm_modeset_unlock(&colorop->crtc->mutex); + else + drm_err(colorop->dev, "Dangling colorop, it must be attached to a plane = or a CRTC\n"); +} +EXPORT_SYMBOL(drm_colorop_modeset_unlock); diff --git a/include/drm/drm_colorop.h b/include/drm/drm_colorop.h index 7a4e0d0c4a3d594abecef304b1d5990434cdb231..3e223f3b3597978c5d702ce7622= ae30b8aa9dddb 100644 --- a/include/drm/drm_colorop.h +++ b/include/drm/drm_colorop.h @@ -29,6 +29,7 @@ =20 #include #include +#include #include =20 /* DRM colorop flags */ @@ -444,5 +445,7 @@ const char *drm_get_colorop_lut1d_interpolation_name(en= um drm_colorop_lut1d_inte const char *drm_get_colorop_lut3d_interpolation_name(enum drm_colorop_lut3= d_interpolation_type type); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-mtk-post-blend-color-pipeline-v2-9-ac4471b44758@collabora.com> References: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> In-Reply-To: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Haneen Mohammed , Melissa Wen Cc: Alex Hung , wayland-devel@lists.freedesktop.org, harry.wentland@amd.com, leo.liu@amd.com, ville.syrjala@linux.intel.com, pekka.paalanen@collabora.com, contact@emersion.fr, mwen@igalia.com, jadahl@redhat.com, sebastian.wick@redhat.com, shashank.sharma@amd.com, agoins@nvidia.com, joshua@froggi.es, mdaenzer@redhat.com, aleixpol@kde.org, xaver.hugl@gmail.com, victoria@system76.com, uma.shankar@intel.com, quic_naseer@quicinc.com, quic_cbraga@quicinc.com, quic_abhinavk@quicinc.com, marcan@marcan.st, Liviu.Dudau@arm.com, sashamcintosh@google.com, chaitanya.kumar.borah@intel.com, louis.chauvet@bootlin.com, mcanal@igalia.com, kernel@collabora.com, daniels@collabora.com, leandro.ribeiro@collabora.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Simona Vetter X-Mailer: b4 0.14.2 Factor out the common code paths from the colorop helpers so they can be reused by the post-blend colorop helpers. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Harry Wentland Reviewed-by: Louis Chauvet --- drivers/gpu/drm/drm_colorop.c | 145 ++++++++++++++++++++++++++++----------= ---- 1 file changed, 99 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/drm_colorop.c b/drivers/gpu/drm/drm_colorop.c index 1384a259605fa4945aa74402901886d7e1fde0d1..db137169effa6cd9e6d5805f65b= dfd1cc6882075 100644 --- a/drivers/gpu/drm/drm_colorop.c +++ b/drivers/gpu/drm/drm_colorop.c @@ -91,8 +91,9 @@ static const struct drm_prop_enum_list drm_colorop_lut3d_= interpolation_list[] =3D =20 /* Init Helpers */ =20 -static int drm_plane_colorop_init(struct drm_device *dev, struct drm_color= op *colorop, - struct drm_plane *plane, enum drm_colorop_type type, uint32_t flags) +static int drm_common_colorop_init(struct drm_device *dev, + struct drm_colorop *colorop, + enum drm_colorop_type type, uint32_t flags) { struct drm_mode_config *config =3D &dev->mode_config; struct drm_property *prop; @@ -105,7 +106,6 @@ static int drm_plane_colorop_init(struct drm_device *de= v, struct drm_colorop *co colorop->base.properties =3D &colorop->properties; colorop->dev =3D dev; colorop->type =3D type; - colorop->plane =3D plane; colorop->next =3D NULL; =20 list_add_tail(&colorop->head, &config->colorop_list); @@ -154,6 +154,20 @@ static int drm_plane_colorop_init(struct drm_device *d= ev, struct drm_colorop *co return ret; } =20 +static int drm_plane_colorop_init(struct drm_device *dev, + struct drm_colorop *colorop, + struct drm_plane *plane, + enum drm_colorop_type type, uint32_t flags) +{ + int ret; + + ret =3D drm_common_colorop_init(dev, colorop, type, flags); + + colorop->plane =3D plane; + + return ret; +} + /** * drm_colorop_cleanup - Cleanup a drm_colorop object in color_pipeline * @@ -206,31 +220,13 @@ EXPORT_SYMBOL(drm_colorop_pipeline_destroy); * @flags: bitmask of misc, see DRM_COLOROP_FLAG_* defines. * @return zero on success, -E value on failure */ -int drm_plane_colorop_curve_1d_init(struct drm_device *dev, struct drm_col= orop *colorop, - struct drm_plane *plane, u64 supported_tfs, uint32_t flags) +static int drm_common_colorop_curve_1d_init(struct drm_device *dev, struct= drm_colorop *colorop, + u64 supported_tfs, uint32_t flags) { struct drm_prop_enum_list enum_list[DRM_COLOROP_1D_CURVE_COUNT]; int i, len; =20 struct drm_property *prop; - int ret; - - if (!supported_tfs) { - drm_err(dev, - "No supported TFs for new 1D curve colorop on [PLANE:%d:%s]\n", - plane->base.id, plane->name); - return -EINVAL; - } - - if ((supported_tfs & -BIT(DRM_COLOROP_1D_CURVE_COUNT)) !=3D 0) { - drm_err(dev, "Unknown TF provided on [PLANE:%d:%s]\n", - plane->base.id, plane->name); - return -EINVAL; - } - - ret =3D drm_plane_colorop_init(dev, colorop, plane, DRM_COLOROP_1D_CURVE,= flags); - if (ret) - return ret; =20 len =3D 0; for (i =3D 0; i < DRM_COLOROP_1D_CURVE_COUNT; i++) { @@ -260,6 +256,41 @@ int drm_plane_colorop_curve_1d_init(struct drm_device = *dev, struct drm_colorop * =20 return 0; } + +static int drm_colorop_has_supported_tf(struct drm_device *dev, struct drm= _mode_object *obj, + const char *name, u64 supported_tfs) +{ + if (!supported_tfs) { + drm_err(dev, + "No supported TFs for new 1D curve colorop on [PLANE:%d:%s]\n", + obj->id, name); + return -EINVAL; + } + + if ((supported_tfs & -BIT(DRM_COLOROP_1D_CURVE_COUNT)) !=3D 0) { + drm_err(dev, "Unknown TF provided on [PLANE:%d:%s]\n", + obj->id, name); + return -EINVAL; + } + + return 0; +} + +int drm_plane_colorop_curve_1d_init(struct drm_device *dev, struct drm_col= orop *colorop, + struct drm_plane *plane, u64 supported_tfs, uint32_t flags) +{ + int ret; + + ret =3D drm_colorop_has_supported_tf(dev, &plane->base, plane->name, supp= orted_tfs); + if (ret) + return ret; + + ret =3D drm_plane_colorop_init(dev, colorop, plane, DRM_COLOROP_1D_CURVE,= flags); + if (ret) + return ret; + + return drm_common_colorop_curve_1d_init(dev, colorop, supported_tfs, flag= s); +} EXPORT_SYMBOL(drm_plane_colorop_curve_1d_init); =20 static int drm_colorop_create_data_prop(struct drm_device *dev, struct drm= _colorop *colorop) @@ -280,29 +311,16 @@ static int drm_colorop_create_data_prop(struct drm_de= vice *dev, struct drm_color return 0; } =20 -/** - * drm_plane_colorop_curve_1d_lut_init - Initialize a DRM_COLOROP_1D_LUT - * - * @dev: DRM device - * @colorop: The drm_colorop object to initialize - * @plane: The associated drm_plane - * @lut_size: LUT size supported by driver - * @lut1d_interpolation: 1D LUT interpolation type - * @flags: bitmask of misc, see DRM_COLOROP_FLAG_* defines. - * @return zero on success, -E value on failure - */ -int drm_plane_colorop_curve_1d_lut_init(struct drm_device *dev, struct drm= _colorop *colorop, - struct drm_plane *plane, uint32_t lut_size, - enum drm_colorop_lut1d_interpolation_type lut1d_interpolation, - uint32_t flags) +static int +drm_common_colorop_curve_1d_lut_init(struct drm_device *dev, + struct drm_colorop *colorop, + uint32_t lut_size, + enum drm_colorop_lut1d_interpolation_type lut1d_interpolation, + uint32_t flags) { struct drm_property *prop; int ret; =20 - ret =3D drm_plane_colorop_init(dev, colorop, plane, DRM_COLOROP_1D_LUT, f= lags); - if (ret) - return ret; - /* initialize 1D LUT only attribute */ /* LUT size */ prop =3D drm_property_create_range(dev, DRM_MODE_PROP_IMMUTABLE | DRM_MOD= E_PROP_ATOMIC, @@ -334,17 +352,40 @@ int drm_plane_colorop_curve_1d_lut_init(struct drm_de= vice *dev, struct drm_color =20 return 0; } -EXPORT_SYMBOL(drm_plane_colorop_curve_1d_lut_init); =20 -int drm_plane_colorop_ctm_3x4_init(struct drm_device *dev, struct drm_colo= rop *colorop, - struct drm_plane *plane, uint32_t flags) +/** + * drm_plane_colorop_curve_1d_lut_init - Initialize a DRM_COLOROP_1D_LUT + * + * @dev: DRM device + * @colorop: The drm_colorop object to initialize + * @plane: The associated drm_plane + * @lut_size: LUT size supported by driver + * @lut1d_interpolation: 1D LUT interpolation type + * @flags: bitmask of misc, see DRM_COLOROP_FLAG_* defines. + * @return zero on success, -E value on failure + */ +int +drm_plane_colorop_curve_1d_lut_init(struct drm_device *dev, struct drm_col= orop *colorop, + struct drm_plane *plane, uint32_t lut_size, + enum drm_colorop_lut1d_interpolation_type lut1d_interpolation, + uint32_t flags) { int ret; =20 - ret =3D drm_plane_colorop_init(dev, colorop, plane, DRM_COLOROP_CTM_3X4, = flags); + ret =3D drm_plane_colorop_init(dev, colorop, plane, DRM_COLOROP_1D_LUT, f= lags); if (ret) return ret; =20 + return drm_common_colorop_curve_1d_lut_init(dev, colorop, lut_size, + lut1d_interpolation, flags); +} +EXPORT_SYMBOL(drm_plane_colorop_curve_1d_lut_init); + +static int drm_common_colorop_ctm_3x4_init(struct drm_device *dev, struct = drm_colorop *colorop, + uint32_t flags) +{ + int ret; + ret =3D drm_colorop_create_data_prop(dev, colorop); if (ret) return ret; @@ -353,6 +394,18 @@ int drm_plane_colorop_ctm_3x4_init(struct drm_device *= dev, struct drm_colorop *c =20 return 0; } + +int drm_plane_colorop_ctm_3x4_init(struct drm_device *dev, struct drm_colo= rop *colorop, + struct drm_plane *plane, uint32_t flags) +{ + int ret; + + ret =3D drm_plane_colorop_init(dev, colorop, plane, DRM_COLOROP_CTM_3X4, = flags); + if (ret) + return ret; + + return drm_common_colorop_ctm_3x4_init(dev, colorop, flags); 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Thu, 18 Sep 2025 02:44:27 +0200 (CEST) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Wed, 17 Sep 2025 20:43:19 -0400 Subject: [PATCH RFC v2 10/20] drm/colorop: Introduce colorop helpers for crtc Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-mtk-post-blend-color-pipeline-v2-10-ac4471b44758@collabora.com> References: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> In-Reply-To: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Haneen Mohammed , Melissa Wen Cc: Alex Hung , wayland-devel@lists.freedesktop.org, harry.wentland@amd.com, leo.liu@amd.com, ville.syrjala@linux.intel.com, pekka.paalanen@collabora.com, contact@emersion.fr, mwen@igalia.com, jadahl@redhat.com, sebastian.wick@redhat.com, shashank.sharma@amd.com, agoins@nvidia.com, joshua@froggi.es, mdaenzer@redhat.com, aleixpol@kde.org, xaver.hugl@gmail.com, victoria@system76.com, uma.shankar@intel.com, quic_naseer@quicinc.com, quic_cbraga@quicinc.com, quic_abhinavk@quicinc.com, marcan@marcan.st, Liviu.Dudau@arm.com, sashamcintosh@google.com, chaitanya.kumar.borah@intel.com, louis.chauvet@bootlin.com, mcanal@igalia.com, kernel@collabora.com, daniels@collabora.com, leandro.ribeiro@collabora.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Simona Vetter X-Mailer: b4 0.14.2 Introduce colorop helper counterparts for post-blend color pipelines that take a CRTC instead of a plane. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Harry Wentland Reviewed-by: Louis Chauvet --- drivers/gpu/drm/drm_colorop.c | 73 +++++++++++++++++++++++++++++++++++++++= ++++ include/drm/drm_colorop.h | 8 +++++ 2 files changed, 81 insertions(+) diff --git a/drivers/gpu/drm/drm_colorop.c b/drivers/gpu/drm/drm_colorop.c index db137169effa6cd9e6d5805f65bdfd1cc6882075..b0c3216f4dac22f3408cbd537a2= 0f38d03abc0a7 100644 --- a/drivers/gpu/drm/drm_colorop.c +++ b/drivers/gpu/drm/drm_colorop.c @@ -168,6 +168,20 @@ static int drm_plane_colorop_init(struct drm_device *d= ev, return ret; } =20 +static int drm_crtc_colorop_init(struct drm_device *dev, + struct drm_colorop *colorop, + struct drm_crtc *crtc, + enum drm_colorop_type type, uint32_t flags) +{ + int ret; + + ret =3D drm_common_colorop_init(dev, colorop, type, flags); + + colorop->crtc =3D crtc; + + return ret; +} + /** * drm_colorop_cleanup - Cleanup a drm_colorop object in color_pipeline * @@ -293,6 +307,23 @@ int drm_plane_colorop_curve_1d_init(struct drm_device = *dev, struct drm_colorop * } EXPORT_SYMBOL(drm_plane_colorop_curve_1d_init); =20 +int drm_crtc_colorop_curve_1d_init(struct drm_device *dev, struct drm_colo= rop *colorop, + struct drm_crtc *crtc, u64 supported_tfs, uint32_t flags) +{ + int ret; + + ret =3D drm_colorop_has_supported_tf(dev, &crtc->base, crtc->name, suppor= ted_tfs); + if (ret) + return ret; + + ret =3D drm_crtc_colorop_init(dev, colorop, crtc, DRM_COLOROP_1D_CURVE, f= lags); + if (ret) + return ret; + + return drm_common_colorop_curve_1d_init(dev, colorop, supported_tfs, flag= s); +} +EXPORT_SYMBOL(drm_crtc_colorop_curve_1d_init); + static int drm_colorop_create_data_prop(struct drm_device *dev, struct drm= _colorop *colorop) { struct drm_property *prop; @@ -381,6 +412,35 @@ drm_plane_colorop_curve_1d_lut_init(struct drm_device = *dev, struct drm_colorop * } EXPORT_SYMBOL(drm_plane_colorop_curve_1d_lut_init); =20 +/** + * drm_crtc_colorop_curve_1d_lut_init - Initialize a DRM_COLOROP_1D_LUT + * + * @dev: DRM device + * @colorop: The drm_colorop object to initialize + * @crtc: The associated drm_crtc + * @lut_size: LUT size supported by driver + * @lut1d_interpolation: 1D LUT interpolation type + * @flags: bitmask of misc, see DRM_COLOROP_FLAG_* defines. + * @return zero on success, -E value on failure + */ +int +drm_crtc_colorop_curve_1d_lut_init(struct drm_device *dev, + struct drm_colorop *colorop, + struct drm_crtc *crtc, uint32_t lut_size, + enum drm_colorop_lut1d_interpolation_type lut1d_interpolation, + uint32_t flags) +{ + int ret; + + ret =3D drm_crtc_colorop_init(dev, colorop, crtc, DRM_COLOROP_1D_LUT, fla= gs); + if (ret) + return ret; + + return drm_common_colorop_curve_1d_lut_init(dev, colorop, lut_size, + lut1d_interpolation, flags); +} +EXPORT_SYMBOL(drm_crtc_colorop_curve_1d_lut_init); + static int drm_common_colorop_ctm_3x4_init(struct drm_device *dev, struct = drm_colorop *colorop, uint32_t flags) { @@ -408,6 +468,19 @@ int drm_plane_colorop_ctm_3x4_init(struct drm_device *= dev, struct drm_colorop *c } EXPORT_SYMBOL(drm_plane_colorop_ctm_3x4_init); =20 +int drm_crtc_colorop_ctm_3x4_init(struct drm_device *dev, struct drm_color= op *colorop, + struct drm_crtc *crtc, uint32_t flags) +{ + int ret; + + ret =3D drm_crtc_colorop_init(dev, colorop, crtc, DRM_COLOROP_CTM_3X4, fl= ags); + if (ret) + return ret; + + return drm_common_colorop_ctm_3x4_init(dev, colorop, flags); +} +EXPORT_SYMBOL(drm_crtc_colorop_ctm_3x4_init); + /** * drm_plane_colorop_mult_init - Initialize a DRM_COLOROP_MULTIPLIER * diff --git a/include/drm/drm_colorop.h b/include/drm/drm_colorop.h index 3e223f3b3597978c5d702ce7622ae30b8aa9dddb..e7d1e5e95a901b1bd91fd8580e2= fcb367c0253ce 100644 --- a/include/drm/drm_colorop.h +++ b/include/drm/drm_colorop.h @@ -377,14 +377,22 @@ static inline struct drm_colorop *drm_colorop_find(st= ruct drm_device *dev, =20 void drm_colorop_pipeline_destroy(struct drm_device *dev); =20 +int drm_crtc_colorop_curve_1d_lut_init(struct drm_device *dev, struct drm_= colorop *colorop, + struct drm_crtc *crtc, uint32_t lut_size, + enum drm_colorop_lut1d_interpolation_type lut1d_interpolation, + uint32_t flags); int drm_plane_colorop_curve_1d_init(struct drm_device *dev, struct drm_col= orop *colorop, struct drm_plane *plane, u64 supported_tfs, uint32_t flags); +int drm_crtc_colorop_curve_1d_init(struct drm_device *dev, struct drm_colo= rop *colorop, + struct drm_crtc *crtc, u64 supported_tfs, uint32_t flags); int drm_plane_colorop_curve_1d_lut_init(struct drm_device *dev, struct drm= _colorop *colorop, struct drm_plane *plane, uint32_t lut_size, enum drm_colorop_lut1d_interpolation_type lut1d_interpolation, uint32_t flags); int drm_plane_colorop_ctm_3x4_init(struct drm_device *dev, struct drm_colo= rop *colorop, struct drm_plane *plane, uint32_t flags); +int drm_crtc_colorop_ctm_3x4_init(struct drm_device *dev, struct drm_color= op *colorop, + struct drm_crtc *crtc, uint32_t flags); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-mtk-post-blend-color-pipeline-v2-11-ac4471b44758@collabora.com> References: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> In-Reply-To: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Haneen Mohammed , Melissa Wen Cc: Alex Hung , wayland-devel@lists.freedesktop.org, harry.wentland@amd.com, leo.liu@amd.com, ville.syrjala@linux.intel.com, pekka.paalanen@collabora.com, contact@emersion.fr, mwen@igalia.com, jadahl@redhat.com, sebastian.wick@redhat.com, shashank.sharma@amd.com, agoins@nvidia.com, joshua@froggi.es, mdaenzer@redhat.com, aleixpol@kde.org, xaver.hugl@gmail.com, victoria@system76.com, uma.shankar@intel.com, quic_naseer@quicinc.com, quic_cbraga@quicinc.com, quic_abhinavk@quicinc.com, marcan@marcan.st, Liviu.Dudau@arm.com, sashamcintosh@google.com, chaitanya.kumar.borah@intel.com, louis.chauvet@bootlin.com, mcanal@igalia.com, kernel@collabora.com, daniels@collabora.com, leandro.ribeiro@collabora.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Simona Vetter X-Mailer: b4 0.14.2 Export drm_colorop_cleanup() so drivers subclassing drm_colorop can reuse this function in subclass cleanup routines. Reviewed-by: Louis Chauvet Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Harry Wentland --- drivers/gpu/drm/drm_colorop.c | 3 ++- include/drm/drm_colorop.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_colorop.c b/drivers/gpu/drm/drm_colorop.c index b0c3216f4dac22f3408cbd537a20f38d03abc0a7..83deb2bc6f50fe030664548365d= 22de9b45f486b 100644 --- a/drivers/gpu/drm/drm_colorop.c +++ b/drivers/gpu/drm/drm_colorop.c @@ -187,7 +187,7 @@ static int drm_crtc_colorop_init(struct drm_device *dev, * * @colorop: The drm_colorop object to be cleaned */ -static void drm_colorop_cleanup(struct drm_colorop *colorop) +void drm_colorop_cleanup(struct drm_colorop *colorop) { struct drm_device *dev =3D colorop->dev; struct drm_mode_config *config =3D &dev->mode_config; @@ -202,6 +202,7 @@ static void drm_colorop_cleanup(struct drm_colorop *col= orop) =20 kfree(colorop->state); } +EXPORT_SYMBOL(drm_colorop_cleanup); =20 /** * drm_colorop_pipeline_destroy - Helper for color pipeline destruction diff --git a/include/drm/drm_colorop.h b/include/drm/drm_colorop.h index e7d1e5e95a901b1bd91fd8580e2fcb367c0253ce..f7472ece00cdb09ae204d0c2339= eb35c3246874e 100644 --- a/include/drm/drm_colorop.h +++ b/include/drm/drm_colorop.h @@ -375,6 +375,7 @@ static inline struct drm_colorop *drm_colorop_find(stru= ct drm_device *dev, return mo ? obj_to_colorop(mo) : NULL; } =20 +void drm_colorop_cleanup(struct drm_colorop *colorop); void drm_colorop_pipeline_destroy(struct drm_device *dev); =20 int drm_crtc_colorop_curve_1d_lut_init(struct drm_device *dev, struct drm_= colorop *colorop, --=20 2.50.1 From nobody Thu Oct 2 10:39:58 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 30840212566 for ; Thu, 18 Sep 2025 00:44:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758156292; cv=none; b=VVyWhyn5Cz47fz6PpjzfDwy0R+RDU4hHGD77jidkPYZ76XKAMRnNp2ZP0chX7DEosKDpTdPnApZbenkGZZRorJ0RUYJ53625n0OEGzmkOvbX/P+nSSf2iPVkjrRxbSrsnWaqJ+Yv+AIXQPxrJhf0dtfisUnUCbLAPKCDg5Zs5Tw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758156292; c=relaxed/simple; bh=wN/Y3+uhPOPTYnZ+MKX1igI1SlXFFgW5cU2DrgN+pT8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VIfcNIgP0MD6uaDQP+cm6RZBCeRsZdKzgJMh77viintSpc7CLwuB5CUbsGzWsDuOiplUsGu64DZ1nNhSV85n0jNe78ftyxN4H7DdQMWr5Zz7TSPrED8rM03ZVcZgfWvY+BpG5wEr5zQbQ2JA0rsRRt/LYFqFSY/rDy++NievK+A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=mu48ew3S; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="mu48ew3S" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1758156289; bh=wN/Y3+uhPOPTYnZ+MKX1igI1SlXFFgW5cU2DrgN+pT8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=mu48ew3SbUxjspIiN/XBMmjzibf8zkbqhf/CEoTkObxJX2V66hVLBsTm1PqBVZ+ci mhEjiwMW6BLzmYJvpMJMDcjv+DjL46YX7B7O5s2zIcYYCyIzBzpoN8oyxZ/nmfQUas ODEZRMcr/oItClvW5VWnRMxJ896SxqfGTfgmEUMoTs2jVzwWEOIPAPyNxFGGDpsRo2 ZHg1j0LvC43PEmGKmCRKdOk2vS5EHw6DetwCjrLHgDFGHPE3TBiSCLXh4fGvBIKdxd WxBH0peLuqgxHSo1VKmnm7QV2YHUVRKDMA0Ed4Fn9M2PXy80hQirsUiz3/DO9UZor7 Eza66KRKx2VPQ== Received: from [127.0.1.1] (unknown [IPv6:2600:4041:5b1a:9400:62f0:406e:ac79:4a96]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by bali.collaboradmins.com (Postfix) with ESMTPSA id D864C17E1067; Thu, 18 Sep 2025 02:44:41 +0200 (CEST) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Wed, 17 Sep 2025 20:43:21 -0400 Subject: [PATCH RFC v2 12/20] drm/crtc: Track post-blend color pipeline client cap in drm_crtc_state Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-mtk-post-blend-color-pipeline-v2-12-ac4471b44758@collabora.com> References: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> In-Reply-To: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Haneen Mohammed , Melissa Wen Cc: Alex Hung , wayland-devel@lists.freedesktop.org, harry.wentland@amd.com, leo.liu@amd.com, ville.syrjala@linux.intel.com, pekka.paalanen@collabora.com, contact@emersion.fr, mwen@igalia.com, jadahl@redhat.com, sebastian.wick@redhat.com, shashank.sharma@amd.com, agoins@nvidia.com, joshua@froggi.es, mdaenzer@redhat.com, aleixpol@kde.org, xaver.hugl@gmail.com, victoria@system76.com, uma.shankar@intel.com, quic_naseer@quicinc.com, quic_cbraga@quicinc.com, quic_abhinavk@quicinc.com, marcan@marcan.st, Liviu.Dudau@arm.com, sashamcintosh@google.com, chaitanya.kumar.borah@intel.com, louis.chauvet@bootlin.com, mcanal@igalia.com, kernel@collabora.com, daniels@collabora.com, leandro.ribeiro@collabora.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Simona Vetter X-Mailer: b4 0.14.2 Some drivers, like VKMS, only have access to the drm_crtc_state but not the drm_atomic_state during composition of the output framebuffer. Store the state of the post-blend color pipeline client cap in the drm_crtc_state so those drivers can decide whether to look at the color pipeline or the legacy properties for the color management settings to apply. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Harry Wentland Reviewed-by: Louis Chauvet --- drivers/gpu/drm/drm_atomic.c | 1 + include/drm/drm_crtc.h | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index 6982c978dc530b838353ace60f748660c3b4524d..bbfa35c800240722785a6db440e= b3d47ef9c8ed6 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -386,6 +386,7 @@ drm_atomic_get_crtc_state(struct drm_atomic_state *stat= e, state->crtcs[index].new_state =3D crtc_state; state->crtcs[index].ptr =3D crtc; crtc_state->state =3D state; + crtc_state->color_pipeline_enabled =3D state->post_blend_color_pipeline; =20 drm_dbg_atomic(state->dev, "Added [CRTC:%d:%s] %p state to %p\n", crtc->base.id, crtc->name, crtc_state, state); diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h index df03637ca25abd45e96b5944229297f776fd046d..cb9eda6335e0d6728d99d67cc69= 16ad2d0e1d94e 100644 --- a/include/drm/drm_crtc.h +++ b/include/drm/drm_crtc.h @@ -282,6 +282,14 @@ struct drm_crtc_state { */ struct drm_colorop *color_pipeline; =20 + /** + * @color_pipeline_enabled: + * + * Whether color management should be done based on the &color_pipeline + * or the legacy color properties (&ctm, &gamma_lut and °amma_lut). + */ + bool color_pipeline_enabled; + /** * @target_vblank: * --=20 2.50.1 From nobody Thu Oct 2 10:39:58 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B32720371E for ; Thu, 18 Sep 2025 00:44:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758156301; cv=none; b=o8T6+LqLb0TSZRgw7FKIe7DS+YkkB6+WzgNfDUdsBIWGiJMhwWPTLoCtepL6r4wZlkhNCxYtAF9TPQE23I7OhkRRRy67AMCr7PUBqNcmMEMh++GGeLWbXYTvQntUcDKjas9pqNKSEPmEyaT/P6MzKR6N8GONESq42lV2LjPw1Bc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-mtk-post-blend-color-pipeline-v2-13-ac4471b44758@collabora.com> References: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> In-Reply-To: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Haneen Mohammed , Melissa Wen Cc: Alex Hung , wayland-devel@lists.freedesktop.org, harry.wentland@amd.com, leo.liu@amd.com, ville.syrjala@linux.intel.com, pekka.paalanen@collabora.com, contact@emersion.fr, mwen@igalia.com, jadahl@redhat.com, sebastian.wick@redhat.com, shashank.sharma@amd.com, agoins@nvidia.com, joshua@froggi.es, mdaenzer@redhat.com, aleixpol@kde.org, xaver.hugl@gmail.com, victoria@system76.com, uma.shankar@intel.com, quic_naseer@quicinc.com, quic_cbraga@quicinc.com, quic_abhinavk@quicinc.com, marcan@marcan.st, Liviu.Dudau@arm.com, sashamcintosh@google.com, chaitanya.kumar.borah@intel.com, louis.chauvet@bootlin.com, mcanal@igalia.com, kernel@collabora.com, daniels@collabora.com, leandro.ribeiro@collabora.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Simona Vetter X-Mailer: b4 0.14.2 Allow configuring the gamma and ccorr blocks through the post-blend color pipeline API instead of the GAMMA_LUT and CTM properties. In order to achieve this, initialize the color pipeline property and colorops on the CRTC based on the DDP components available in the CRTC path. Then introduce a struct mtk_drm_colorop that extends drm_colorop and tracks the mtk_ddp_comp that implements it in hardware, and include new ddp_comp helper functions for setting gamma and ctm through the new API. These helpers will then be called during commit flush for every updated colorop if the DRM client supports the post-blend color pipeline API. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Harry Wentland --- drivers/gpu/drm/mediatek/mtk_crtc.c | 208 ++++++++++++++++++++++++++++= +++- drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 2 + 2 files changed, 205 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek= /mtk_crtc.c index bc7527542fdc6fb89fc36794cee7d6dc26f7dcce..9ab2c2b77392839a1b03d6cb016= 70bf252bf68a5 100644 --- a/drivers/gpu/drm/mediatek/mtk_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_crtc.c @@ -82,6 +82,12 @@ struct mtk_crtc_state { unsigned int pending_vrefresh; }; =20 +struct mtk_drm_colorop { + struct drm_colorop colorop; + struct mtk_ddp_comp *comp; + uint32_t data_id; +}; + static inline struct mtk_crtc *to_mtk_crtc(struct drm_crtc *c) { return container_of(c, struct mtk_crtc, base); @@ -92,6 +98,11 @@ static inline struct mtk_crtc_state *to_mtk_crtc_state(s= truct drm_crtc_state *s) return container_of(s, struct mtk_crtc_state, base); } =20 +static inline struct mtk_drm_colorop *to_mtk_colorop(struct drm_colorop *c= olorop) +{ + return container_of(colorop, struct mtk_drm_colorop, colorop); +} + static void mtk_crtc_finish_page_flip(struct mtk_crtc *mtk_crtc) { struct drm_crtc *crtc =3D &mtk_crtc->base; @@ -125,6 +136,19 @@ static void mtk_drm_finish_page_flip(struct mtk_crtc *= mtk_crtc) spin_unlock_irqrestore(&mtk_crtc->config_lock, flags); } =20 +static void mtk_drm_colorop_pipeline_destroy(struct drm_device *dev) +{ + struct drm_mode_config *config =3D &dev->mode_config; + struct drm_colorop *colorop, *next; + struct mtk_drm_colorop *mtk_colorop; + + list_for_each_entry_safe(colorop, next, &config->colorop_list, head) { + drm_colorop_cleanup(colorop); + mtk_colorop =3D to_mtk_colorop(colorop); + kfree(mtk_colorop); + } +} + static void mtk_crtc_destroy(struct drm_crtc *crtc) { struct mtk_crtc *mtk_crtc =3D to_mtk_crtc(crtc); @@ -146,6 +170,8 @@ static void mtk_crtc_destroy(struct drm_crtc *crtc) mtk_ddp_comp_unregister_vblank_cb(comp); } =20 + mtk_drm_colorop_pipeline_destroy(crtc->dev); + drm_crtc_cleanup(crtc); } =20 @@ -854,20 +880,103 @@ static void mtk_crtc_atomic_begin(struct drm_crtc *c= rtc, } } =20 +static bool colorop_data_update_flush_status(struct drm_colorop_state *col= orop_state) +{ + struct drm_colorop *colorop =3D colorop_state->colorop; + struct mtk_drm_colorop *mtk_colorop =3D to_mtk_colorop(colorop); + struct drm_property_blob *data_blob =3D colorop_state->data; + uint32_t data_id =3D colorop_state->bypass ? 0 : data_blob->base.id; + bool needs_flush =3D mtk_colorop->data_id !=3D data_id; + + mtk_colorop->data_id =3D data_id; + + return needs_flush; +} + +static void mtk_crtc_ddp_comp_apply_colorop(struct drm_colorop_state *colo= rop_state) +{ + struct drm_colorop *colorop =3D colorop_state->colorop; + struct mtk_drm_colorop *mtk_colorop =3D to_mtk_colorop(colorop); + struct drm_property_blob *data_blob =3D colorop_state->data; + struct mtk_ddp_comp *ddp_comp =3D mtk_colorop->comp; + struct drm_color_ctm_3x4 *ctm =3D NULL; + struct drm_color_lut32 *lut =3D NULL; + + switch (colorop->type) { + case DRM_COLOROP_1D_LUT: + if (!colorop_data_update_flush_status(colorop_state)) + return; + + if (!colorop_state->bypass) + lut =3D (struct drm_color_lut32 *)data_blob->data; + + ddp_comp->funcs->gamma_set_color_pipeline(ddp_comp->dev, lut); + break; + case DRM_COLOROP_CTM_3X4: + if (!colorop_data_update_flush_status(colorop_state)) + return; + + if (!colorop_state->bypass) + ctm =3D (struct drm_color_ctm_3x4 *)data_blob->data; + + ddp_comp->funcs->ctm_set_color_pipeline(ddp_comp->dev, ctm); + break; + default: + /* If this happens the driver is broken */ + drm_WARN(colorop->dev, 1, + "Trying to atomic flush COLOROP of type unsupported by driver: %d\n", + colorop->type); + break; + } +} + static void mtk_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *state) { struct mtk_crtc *mtk_crtc =3D to_mtk_crtc(crtc); + struct drm_colorop_state *new_colorop_state; + struct drm_colorop *colorop; int i; =20 - if (crtc->state->color_mgmt_changed) - for (i =3D 0; i < mtk_crtc->ddp_comp_nr; i++) { - mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state); - mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state); - } + if (state->post_blend_color_pipeline) { + for_each_new_colorop_in_state(state, colorop, new_colorop_state, i) + mtk_crtc_ddp_comp_apply_colorop(new_colorop_state); + } else { + if (crtc->state->color_mgmt_changed) + for (i =3D 0; i < mtk_crtc->ddp_comp_nr; i++) { + mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state); + mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state); + } + } mtk_crtc_update_config(mtk_crtc, !!mtk_crtc->event); } =20 +static int mtk_crtc_atomic_check(struct drm_crtc *crtc, + struct drm_atomic_state *state) +{ + struct drm_colorop_state *new_colorop_state; + struct drm_colorop *colorop; + int i; + + for_each_new_colorop_in_state(state, colorop, new_colorop_state, i) { + switch (colorop->type) { + case DRM_COLOROP_1D_LUT: + case DRM_COLOROP_CTM_3X4: + if (!new_colorop_state->bypass && !new_colorop_state->data) { + drm_dbg_atomic(crtc->dev, + "Missing required DATA property for COLOROP:%d\n", + colorop->base.id); + return -EINVAL; + } + break; + default: + break; + } + } + + return 0; +} + static const struct drm_crtc_funcs mtk_crtc_funcs =3D { .set_config =3D drm_atomic_helper_set_config, .page_flip =3D drm_atomic_helper_page_flip, @@ -885,6 +994,7 @@ static const struct drm_crtc_helper_funcs mtk_crtc_help= er_funcs =3D { .mode_valid =3D mtk_crtc_mode_valid, .atomic_begin =3D mtk_crtc_atomic_begin, .atomic_flush =3D mtk_crtc_atomic_flush, + .atomic_check =3D mtk_crtc_atomic_check, .atomic_enable =3D mtk_crtc_atomic_enable, .atomic_disable =3D mtk_crtc_atomic_disable, }; @@ -987,6 +1097,92 @@ struct device *mtk_crtc_dma_dev_get(struct drm_crtc *= crtc) return mtk_crtc->dma_dev; } =20 +#define MAX_COLOR_PIPELINE_OPS 2 +#define MAX_COLOR_PIPELINES 1 + +static int mtk_colorop_init(struct mtk_crtc *mtk_crtc, + struct mtk_drm_colorop *mtk_colorop, + struct mtk_ddp_comp *ddp_comp) +{ + struct drm_colorop *colorop =3D &mtk_colorop->colorop; + int ret =3D 0; + + if (ddp_comp->funcs->gamma_set_color_pipeline) { + unsigned int lut_sz =3D mtk_ddp_gamma_get_lut_size(ddp_comp); + + ret =3D drm_crtc_colorop_curve_1d_lut_init(mtk_crtc->base.dev, colorop, + &mtk_crtc->base, + lut_sz, + DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR, + DRM_COLOROP_FLAG_ALLOW_BYPASS); + } else if (ddp_comp->funcs->ctm_set_color_pipeline) { + ret =3D drm_crtc_colorop_ctm_3x4_init(mtk_crtc->base.dev, + colorop, + &mtk_crtc->base, + DRM_COLOROP_FLAG_ALLOW_BYPASS); + } + + mtk_colorop->comp =3D ddp_comp; + + return ret; +} + +static int mtk_crtc_init_post_blend_color_pipeline(struct mtk_crtc *mtk_cr= tc, + unsigned int gamma_lut_size) +{ + struct drm_prop_enum_list pipelines[MAX_COLOR_PIPELINES]; + struct drm_colorop *ops[MAX_COLOR_PIPELINE_OPS]; + struct mtk_drm_colorop *mtk_colorop; + unsigned int num_pipelines =3D 0; + unsigned int op_idx =3D 0; + int ret; + + memset(ops, 0, sizeof(ops)); + + for (unsigned int i =3D 0; + i < mtk_crtc->ddp_comp_nr && op_idx < MAX_COLOR_PIPELINE_OPS; + i++) { + struct mtk_ddp_comp *ddp_comp =3D mtk_crtc->ddp_comp[i]; + + if (!(ddp_comp->funcs->gamma_set_color_pipeline || + ddp_comp->funcs->ctm_set_color_pipeline)) + continue; + + mtk_colorop =3D kzalloc(sizeof(struct mtk_drm_colorop), GFP_KERNEL); + if (!mtk_colorop) { + ret =3D -ENOMEM; + goto cleanup; + } + + ops[op_idx] =3D &mtk_colorop->colorop; + + ret =3D mtk_colorop_init(mtk_crtc, mtk_colorop, ddp_comp); + if (ret) + goto cleanup; + + if (op_idx > 0) + drm_colorop_set_next_property(ops[op_idx-1], ops[op_idx]); + + op_idx++; + } + + if (op_idx > 0) { + pipelines[0].type =3D ops[0]->base.id; + pipelines[0].name =3D kasprintf(GFP_KERNEL, "Color Pipeline %d", ops[0]-= >base.id); + num_pipelines =3D 1; + } + + /* Create COLOR_PIPELINE property and attach */ + drm_crtc_create_color_pipeline_property(&mtk_crtc->base, pipelines, num_p= ipelines); + + return 0; + +cleanup: + mtk_drm_colorop_pipeline_destroy(mtk_crtc->base.dev); + + return ret; +} + int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path, unsigned int path_len, int priv_data_index, const struct mtk_drm_route *conn_routes, @@ -1103,6 +1299,8 @@ int mtk_crtc_create(struct drm_device *drm_dev, const= unsigned int *path, if (ret < 0) return ret; =20 + mtk_crtc_init_post_blend_color_pipeline(mtk_crtc, gamma_lut_size); + if (gamma_lut_size) drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size); drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size); diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.h index 7289b3dcf22f22f344016beee0c7c144cf7b93c8..554c3cc8ad7b266b8b8eee74ceb= 8f7383fe2f8df 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h @@ -75,10 +75,12 @@ struct mtk_ddp_comp_funcs { unsigned int (*gamma_get_lut_size)(struct device *dev); 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Thu, 18 Sep 2025 02:44:57 +0200 (CEST) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Wed, 17 Sep 2025 20:43:23 -0400 Subject: [PATCH RFC v2 14/20] drm/mediatek: ccorr: Support post-blend color pipeline API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-mtk-post-blend-color-pipeline-v2-14-ac4471b44758@collabora.com> References: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> In-Reply-To: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Haneen Mohammed , Melissa Wen Cc: Alex Hung , wayland-devel@lists.freedesktop.org, harry.wentland@amd.com, leo.liu@amd.com, ville.syrjala@linux.intel.com, pekka.paalanen@collabora.com, contact@emersion.fr, mwen@igalia.com, jadahl@redhat.com, sebastian.wick@redhat.com, shashank.sharma@amd.com, agoins@nvidia.com, joshua@froggi.es, mdaenzer@redhat.com, aleixpol@kde.org, xaver.hugl@gmail.com, victoria@system76.com, uma.shankar@intel.com, quic_naseer@quicinc.com, quic_cbraga@quicinc.com, quic_abhinavk@quicinc.com, marcan@marcan.st, Liviu.Dudau@arm.com, sashamcintosh@google.com, chaitanya.kumar.borah@intel.com, louis.chauvet@bootlin.com, mcanal@igalia.com, kernel@collabora.com, daniels@collabora.com, leandro.ribeiro@collabora.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Simona Vetter X-Mailer: b4 0.14.2 Implement the ctm_set_color_pipeline DDP component function to allow configuring the CTM through the color pipeline API. The color pipeline API only defines a 3x4 matrix, while the driver currently only supports setting the coefficients for a 3x3 matrix. However the underlying hardware does support setting the offset coefficients that make up a 3x4 matrix, so implement support for setting them so the 3x4 matrix structure for the API can be used as is. Also make sure to enable or disable the CTM function depending on whether the block should be bypassed or not. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Harry Wentland --- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 3 +- drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 100 ++++++++++++++++++++++++++= ---- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 3 +- 3 files changed, 93 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.c index ac6620e10262e3b9a4a82093f13c3101f79520de..c873b527423f51733058cbc3d0a= d2a719e26bfe1 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -284,7 +284,8 @@ static const struct mtk_ddp_comp_funcs ddp_ccorr =3D { .config =3D mtk_ccorr_config, .start =3D mtk_ccorr_start, .stop =3D mtk_ccorr_stop, - .ctm_set =3D mtk_ccorr_ctm_set, + .ctm_set =3D mtk_ccorr_ctm_set_legacy, + .ctm_set_color_pipeline =3D mtk_ccorr_ctm_set_color_pipeline, }; =20 static const struct mtk_ddp_comp_funcs ddp_color =3D { diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/me= diatek/mtk_disp_ccorr.c index 10d60d2c2a568ebbe09f90e8f42a73e4c2366662..f69a7d8b97f741f0c5461e8cd6f= 38f70b0690e7e 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c @@ -28,6 +28,11 @@ #define DISP_CCORR_COEF_2 0x0088 #define DISP_CCORR_COEF_3 0x008C #define DISP_CCORR_COEF_4 0x0090 +#define DISP_CCORR_OFFSET_0 0x0100 +#define CCORR_OFFSET_EN BIT(31) +#define DISP_CCORR_OFFSET_1 0x0104 +#define DISP_CCORR_OFFSET_2 0x0108 +#define DISP_CCORR_OFFSET_MASK GENMASK(26, 14) =20 struct mtk_disp_ccorr_data { u32 matrix_bits; @@ -101,25 +106,48 @@ static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n) return r; } =20 -void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state) +static void mtk_ccorr_ctm_set(struct device *dev, struct cmdq_pkt *cmdq_pk= t, + void *ctm, bool ctm_3x4) { struct mtk_disp_ccorr *ccorr =3D dev_get_drvdata(dev); - struct drm_property_blob *blob =3D state->ctm; - struct drm_color_ctm *ctm; - const u64 *input; + u64 coeffs_in[9]; + u64 coeffs_offset_in[3]; uint16_t coeffs[9] =3D { 0 }; + uint16_t coeffs_offset[3]; int i; - struct cmdq_pkt *cmdq_pkt =3D NULL; u32 matrix_bits =3D ccorr->data->matrix_bits; + u32 val; + + if (ctm_3x4) { + struct drm_color_ctm_3x4 *ctm_3x4 =3D (struct drm_color_ctm_3x4 *)ctm; + + coeffs_in[0] =3D ctm_3x4->matrix[0]; + coeffs_in[1] =3D ctm_3x4->matrix[1]; + coeffs_in[2] =3D ctm_3x4->matrix[2]; + coeffs_in[3] =3D ctm_3x4->matrix[4]; + coeffs_in[4] =3D ctm_3x4->matrix[5]; + coeffs_in[5] =3D ctm_3x4->matrix[6]; + coeffs_in[6] =3D ctm_3x4->matrix[8]; + coeffs_in[7] =3D ctm_3x4->matrix[9]; + coeffs_in[8] =3D ctm_3x4->matrix[10]; + + coeffs_offset_in[0] =3D ctm_3x4->matrix[3]; + coeffs_offset_in[1] =3D ctm_3x4->matrix[7]; + coeffs_offset_in[2] =3D ctm_3x4->matrix[11]; + } else { + struct drm_color_ctm *ctm_3x3 =3D (struct drm_color_ctm *)ctm; =20 - if (!blob) - return; - - ctm =3D (struct drm_color_ctm *)blob->data; - input =3D ctm->matrix; + for (i =3D 0; i < ARRAY_SIZE(coeffs_in); i++) + coeffs_in[i] =3D ctm_3x3->matrix[i]; + } =20 for (i =3D 0; i < ARRAY_SIZE(coeffs); i++) - coeffs[i] =3D mtk_ctm_s31_32_to_s1_n(input[i], matrix_bits); + coeffs[i] =3D mtk_ctm_s31_32_to_s1_n(coeffs_in[i], matrix_bits); + + if (ctm_3x4) { + for (i =3D 0; i < ARRAY_SIZE(coeffs_offset); i++) + coeffs_offset[i] =3D mtk_ctm_s31_32_to_s1_n(coeffs_offset_in[i], matrix= _bits); + } =20 mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0); @@ -131,6 +159,56 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_= crtc_state *state) &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_3); mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_4); + + if (ctm_3x4) { + val =3D CCORR_OFFSET_EN; + val |=3D FIELD_PREP(DISP_CCORR_OFFSET_MASK, coeffs_offset[0]); + mtk_ddp_write(cmdq_pkt, val, &ccorr->cmdq_reg, + ccorr->regs, DISP_CCORR_OFFSET_0); + val =3D FIELD_PREP(DISP_CCORR_OFFSET_MASK, coeffs_offset[1]); + mtk_ddp_write(cmdq_pkt, val, &ccorr->cmdq_reg, + ccorr->regs, DISP_CCORR_OFFSET_1); + val =3D FIELD_PREP(DISP_CCORR_OFFSET_MASK, coeffs_offset[2]); + mtk_ddp_write(cmdq_pkt, val, &ccorr->cmdq_reg, + ccorr->regs, DISP_CCORR_OFFSET_2); + } else { + mtk_ddp_write_mask(cmdq_pkt, 0, &ccorr->cmdq_reg, + ccorr->regs, DISP_CCORR_OFFSET_0, + CCORR_OFFSET_EN); + } + + mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, + ccorr->regs, DISP_CCORR_CFG); +} + +void mtk_ccorr_ctm_set_legacy(struct device *dev, struct drm_crtc_state *s= tate) +{ + struct drm_property_blob *blob =3D state->ctm; + struct cmdq_pkt *cmdq_pkt =3D NULL; + struct drm_color_ctm *ctm; + + if (!blob) + return; + + ctm =3D (struct drm_color_ctm *)blob->data; + + mtk_ccorr_ctm_set(dev, cmdq_pkt, ctm, false); +} + +void mtk_ccorr_ctm_set_color_pipeline(struct device *dev, struct drm_color= _ctm_3x4 *ctm) +{ + struct mtk_disp_ccorr *ccorr =3D dev_get_drvdata(dev); + struct cmdq_pkt *cmdq_pkt =3D NULL; + + /* Configure block to be bypassed */ + if (!ctm) { + mtk_ddp_write_mask(cmdq_pkt, CCORR_RELAY_MODE, &ccorr->cmdq_reg, + ccorr->regs, DISP_CCORR_CFG, + CCORR_RELAY_MODE | CCORR_ENGINE_EN); + return; + } + + mtk_ccorr_ctm_set(dev, cmdq_pkt, ctm, true); } =20 static int mtk_disp_ccorr_bind(struct device *dev, struct device *master, diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/medi= atek/mtk_disp_drv.h index 679d413bf10be1e2fc4804a60a3fbe5d734614f6..ac84cf579150fd0535c79f43ad5= 942f8d412d450 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -22,7 +22,8 @@ void mtk_aal_gamma_set(struct device *dev, struct drm_crt= c_state *state); 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Thu, 18 Sep 2025 02:45:04 +0200 (CEST) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Wed, 17 Sep 2025 20:43:24 -0400 Subject: [PATCH RFC v2 15/20] drm/mediatek: gamma: Support post-blend color pipeline API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-mtk-post-blend-color-pipeline-v2-15-ac4471b44758@collabora.com> References: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> In-Reply-To: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Haneen Mohammed , Melissa Wen Cc: Alex Hung , wayland-devel@lists.freedesktop.org, harry.wentland@amd.com, leo.liu@amd.com, ville.syrjala@linux.intel.com, pekka.paalanen@collabora.com, contact@emersion.fr, mwen@igalia.com, jadahl@redhat.com, sebastian.wick@redhat.com, shashank.sharma@amd.com, agoins@nvidia.com, joshua@froggi.es, mdaenzer@redhat.com, aleixpol@kde.org, xaver.hugl@gmail.com, victoria@system76.com, uma.shankar@intel.com, quic_naseer@quicinc.com, quic_cbraga@quicinc.com, quic_abhinavk@quicinc.com, marcan@marcan.st, Liviu.Dudau@arm.com, sashamcintosh@google.com, chaitanya.kumar.borah@intel.com, louis.chauvet@bootlin.com, mcanal@igalia.com, kernel@collabora.com, daniels@collabora.com, leandro.ribeiro@collabora.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Simona Vetter X-Mailer: b4 0.14.2 Implement the gamma_set_color_pipeline DDP component function to allow configuring the gamma LUT through the post-blend color pipeline API. The color pipeline API uses a 32-bit long, rather than 16-bit long, LUT, so also update the functions to handle both cases. Also make sure to enable or disable the LUT function depending on whether the block should be bypassed or not. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Harry Wentland --- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 3 +- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 3 +- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 107 +++++++++++++++++++++++++-= ---- 3 files changed, 94 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.c index c873b527423f51733058cbc3d0ad2a719e26bfe1..d253906546506ecf1f1e2a23123= b80e774e981ae 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -327,7 +327,8 @@ static const struct mtk_ddp_comp_funcs ddp_gamma =3D { .clk_enable =3D mtk_gamma_clk_enable, .clk_disable =3D mtk_gamma_clk_disable, .gamma_get_lut_size =3D mtk_gamma_get_lut_size, - .gamma_set =3D mtk_gamma_set, + .gamma_set =3D mtk_gamma_set_legacy, + .gamma_set_color_pipeline =3D mtk_gamma_set_color_pipeline, .config =3D mtk_gamma_config, .start =3D mtk_gamma_start, .stop =3D mtk_gamma_stop, diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/medi= atek/mtk_disp_drv.h index ac84cf579150fd0535c79f43ad5942f8d412d450..7795aa5bc057fc09597cbd582f0= 4e4dc76d3ecba 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -58,7 +58,8 @@ void mtk_gamma_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); unsigned int mtk_gamma_get_lut_size(struct device *dev); -void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state); +void mtk_gamma_set_legacy(struct device *dev, struct drm_crtc_state *state= ); +void mtk_gamma_set_color_pipeline(struct device *dev, struct drm_color_lut= 32 *lut); void mtk_gamma_start(struct device *dev); void mtk_gamma_stop(struct device *dev); =20 diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/me= diatek/mtk_disp_gamma.c index 8afd15006df2a21f3f52fe00eca3c5501f4fb76a..dec9eeb53cb8539e49ecc1087e0= 37645c792ee3d 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -87,13 +87,34 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) return 0; } =20 -static bool mtk_gamma_lut_is_descending(struct drm_color_lut *lut, u32 lut= _size) +static bool mtk_gamma_lut_is_descending(void *lut, bool bits32, u32 lut_si= ze) { u64 first, last; int last_entry =3D lut_size - 1; + u32 lutr_first, lutg_first, lutb_first, lutr_last, lutg_last, lutb_last; + struct drm_color_lut32 *lut32; + struct drm_color_lut *lut16; + + if (bits32) { + lut32 =3D (struct drm_color_lut32 *)lut; + lutr_first =3D lut32[0].red; + lutg_first =3D lut32[0].green; + lutb_first =3D lut32[0].blue; + lutr_last =3D lut32[last_entry].red; + lutg_last =3D lut32[last_entry].green; + lutb_last =3D lut32[last_entry].blue; + } else { + lut16 =3D (struct drm_color_lut *)lut; + lutr_first =3D lut16[0].red; + lutg_first =3D lut16[0].green; + lutb_first =3D lut16[0].blue; + lutr_last =3D lut16[last_entry].red; + lutg_last =3D lut16[last_entry].green; + lutb_last =3D lut16[last_entry].blue; + } =20 - first =3D lut[0].red + lut[0].green + lut[0].blue; - last =3D lut[last_entry].red + lut[last_entry].green + lut[last_entry].bl= ue; + first =3D lutr_first + lutg_first + lutb_first; + last =3D lutr_last + lutg_last + lutb_last; =20 return !!(first > last); } @@ -113,7 +134,7 @@ static bool mtk_gamma_lut_is_descending(struct drm_colo= r_lut *lut, u32 lut_size) * - 12-bits LUT supported * - 10-its LUT not supported */ -void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) +static void mtk_gamma_set(struct device *dev, void *lut, bool bits32) { struct mtk_disp_gamma *gamma =3D dev_get_drvdata(dev); void __iomem *lut0_base =3D gamma->regs + DISP_GAMMA_LUT; @@ -121,19 +142,20 @@ void mtk_gamma_set(struct device *dev, struct drm_crt= c_state *state) u32 cfg_val, data_mode, lbank_val, word[2]; u8 lut_bits =3D gamma->data->lut_bits; int cur_bank, num_lut_banks; - struct drm_color_lut *lut; unsigned int i; - - /* If there's no gamma lut there's nothing to do here. */ - if (!state->gamma_lut) - return; + struct drm_color_lut32 *lut32; + struct drm_color_lut *lut16; =20 num_lut_banks =3D gamma->data->lut_size / gamma->data->lut_bank_size; - lut =3D (struct drm_color_lut *)state->gamma_lut->data; =20 /* Switch to 12 bits data mode if supported */ data_mode =3D FIELD_PREP(DISP_GAMMA_BANK_DATA_MODE, !!(lut_bits =3D=3D 12= )); =20 + if (bits32) + lut32 =3D (struct drm_color_lut32 *)lut; + else + lut16 =3D (struct drm_color_lut *)lut; + for (cur_bank =3D 0; cur_bank < num_lut_banks; cur_bank++) { =20 /* Switch gamma bank and set data mode before writing LUT */ @@ -146,10 +168,21 @@ void mtk_gamma_set(struct device *dev, struct drm_crt= c_state *state) for (i =3D 0; i < gamma->data->lut_bank_size; i++) { int n =3D cur_bank * gamma->data->lut_bank_size + i; struct drm_color_lut diff, hwlut; + u32 lutr, lutg, lutb; + + if (bits32) { + lutr =3D lut32[n].red; + lutg =3D lut32[n].green; + lutb =3D lut32[n].blue; + } else { + lutr =3D lut16[n].red; + lutg =3D lut16[n].green; + lutb =3D lut16[n].blue; + } =20 - hwlut.red =3D drm_color_lut_extract(lut[n].red, lut_bits); - hwlut.green =3D drm_color_lut_extract(lut[n].green, lut_bits); - hwlut.blue =3D drm_color_lut_extract(lut[n].blue, lut_bits); + hwlut.red =3D drm_color_lut_extract(lutr, lut_bits); + hwlut.green =3D drm_color_lut_extract(lutg, lut_bits); + hwlut.blue =3D drm_color_lut_extract(lutb, lut_bits); =20 if (!gamma->data->lut_diff || (i % 2 =3D=3D 0)) { if (lut_bits =3D=3D 12) { @@ -162,13 +195,25 @@ void mtk_gamma_set(struct device *dev, struct drm_crt= c_state *state) word[0] |=3D FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); } } else { - diff.red =3D lut[n].red - lut[n - 1].red; + u32 lutr_prev, lutg_prev, lutb_prev; + + if (bits32) { + lutr_prev =3D lut32[n-1].red; + lutg_prev =3D lut32[n-1].green; + lutb_prev =3D lut32[n-1].blue; + } else { + lutr_prev =3D lut16[n-1].red; + lutg_prev =3D lut16[n-1].green; + lutb_prev =3D lut16[n-1].blue; + } + + diff.red =3D lutr - lutr_prev; diff.red =3D drm_color_lut_extract(diff.red, lut_bits); =20 - diff.green =3D lut[n].green - lut[n - 1].green; + diff.green =3D lutg - lutg_prev; diff.green =3D drm_color_lut_extract(diff.green, lut_bits); =20 - diff.blue =3D lut[n].blue - lut[n - 1].blue; + diff.blue =3D lutb - lutb_prev; diff.blue =3D drm_color_lut_extract(diff.blue, lut_bits); =20 if (lut_bits =3D=3D 12) { @@ -191,7 +236,7 @@ void mtk_gamma_set(struct device *dev, struct drm_crtc_= state *state) =20 if (!gamma->data->has_dither) { /* Descending or Rising LUT */ - if (mtk_gamma_lut_is_descending(lut, gamma->data->lut_size - 1)) + if (mtk_gamma_lut_is_descending(lut, bits32, gamma->data->lut_size - 1)) cfg_val |=3D FIELD_PREP(GAMMA_LUT_TYPE, 1); else cfg_val &=3D ~GAMMA_LUT_TYPE; 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Thu, 18 Sep 2025 02:45:12 +0200 (CEST) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Wed, 17 Sep 2025 20:43:25 -0400 Subject: [PATCH RFC v2 16/20] drm/mediatek: Set post-blend color pipeline driver cap Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-mtk-post-blend-color-pipeline-v2-16-ac4471b44758@collabora.com> References: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> In-Reply-To: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Haneen Mohammed , Melissa Wen Cc: Alex Hung , wayland-devel@lists.freedesktop.org, harry.wentland@amd.com, leo.liu@amd.com, ville.syrjala@linux.intel.com, pekka.paalanen@collabora.com, contact@emersion.fr, mwen@igalia.com, jadahl@redhat.com, sebastian.wick@redhat.com, shashank.sharma@amd.com, agoins@nvidia.com, joshua@froggi.es, mdaenzer@redhat.com, aleixpol@kde.org, xaver.hugl@gmail.com, victoria@system76.com, uma.shankar@intel.com, quic_naseer@quicinc.com, quic_cbraga@quicinc.com, quic_abhinavk@quicinc.com, marcan@marcan.st, Liviu.Dudau@arm.com, sashamcintosh@google.com, chaitanya.kumar.borah@intel.com, louis.chauvet@bootlin.com, mcanal@igalia.com, kernel@collabora.com, daniels@collabora.com, leandro.ribeiro@collabora.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Simona Vetter X-Mailer: b4 0.14.2 Now that the driver implements post-blend color pipelines, set the driver cap so they can be used from userspace. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Harry Wentland Reviewed-by: Louis Chauvet --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index d5e6bab364143540e1f59df481b9a9d559c39199..73c0f448d7fcf25e473e2c3c6dd= aaf28446570cf 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -611,7 +611,8 @@ static struct drm_gem_object *mtk_gem_prime_import(stru= ct drm_device *dev, } =20 static const struct drm_driver mtk_drm_driver =3D { - .driver_features =3D DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, + .driver_features =3D DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC | + DRIVER_POST_BLEND_COLOR_PIPELINE, =20 .dumb_create =3D mtk_gem_dumb_create, DRM_FBDEV_DMA_DRIVER_OPS, --=20 2.50.1 From nobody Thu Oct 2 10:39:58 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09A011F4C8C for ; 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Thu, 18 Sep 2025 02:45:19 +0200 (CEST) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Wed, 17 Sep 2025 20:43:26 -0400 Subject: [PATCH RFC v2 17/20] drm/vkms: Rename existing color pipeline helpers to contain "pre_blend" Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-mtk-post-blend-color-pipeline-v2-17-ac4471b44758@collabora.com> References: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> In-Reply-To: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Haneen Mohammed , Melissa Wen Cc: Alex Hung , wayland-devel@lists.freedesktop.org, harry.wentland@amd.com, leo.liu@amd.com, ville.syrjala@linux.intel.com, pekka.paalanen@collabora.com, contact@emersion.fr, mwen@igalia.com, jadahl@redhat.com, sebastian.wick@redhat.com, shashank.sharma@amd.com, agoins@nvidia.com, joshua@froggi.es, mdaenzer@redhat.com, aleixpol@kde.org, xaver.hugl@gmail.com, victoria@system76.com, uma.shankar@intel.com, quic_naseer@quicinc.com, quic_cbraga@quicinc.com, quic_abhinavk@quicinc.com, marcan@marcan.st, Liviu.Dudau@arm.com, sashamcintosh@google.com, chaitanya.kumar.borah@intel.com, louis.chauvet@bootlin.com, mcanal@igalia.com, kernel@collabora.com, daniels@collabora.com, leandro.ribeiro@collabora.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Simona Vetter X-Mailer: b4 0.14.2 Rename the existing color pipeline helpers so they contain "pre_blend" in the name to make them clearly distinguishable from the post-blend helpers when they're introduced. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Harry Wentland Reviewed-by: Louis Chauvet --- drivers/gpu/drm/vkms/vkms_colorop.c | 8 +++++--- drivers/gpu/drm/vkms/vkms_drv.h | 2 +- drivers/gpu/drm/vkms/vkms_plane.c | 2 +- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/vkms/vkms_colorop.c b/drivers/gpu/drm/vkms/vkm= s_colorop.c index 0191ac44dec0a9513e001b304f6ead32a96cdb8c..5924ae2bd40fc904048f99bc9b9= 6308140709e25 100644 --- a/drivers/gpu/drm/vkms/vkms_colorop.c +++ b/drivers/gpu/drm/vkms/vkms_colorop.c @@ -14,7 +14,9 @@ static const u64 supported_tfs =3D =20 #define MAX_COLOR_PIPELINE_OPS 4 =20 -static int vkms_initialize_color_pipeline(struct drm_plane *plane, struct = drm_prop_enum_list *list) +static int +vkms_initialize_pre_blend_color_pipeline(struct drm_plane *plane, + struct drm_prop_enum_list *list) { struct drm_colorop *ops[MAX_COLOR_PIPELINE_OPS]; struct drm_device *dev =3D plane->dev; @@ -96,13 +98,13 @@ static int vkms_initialize_color_pipeline(struct drm_pl= ane *plane, struct drm_pr return ret; } =20 -int vkms_initialize_colorops(struct drm_plane *plane) +int vkms_initialize_pre_blend_colorops(struct drm_plane *plane) { struct drm_prop_enum_list pipeline; int ret; =20 /* Add color pipeline */ - ret =3D vkms_initialize_color_pipeline(plane, &pipeline); + ret =3D vkms_initialize_pre_blend_color_pipeline(plane, &pipeline); if (ret) return ret; =20 diff --git a/drivers/gpu/drm/vkms/vkms_drv.h b/drivers/gpu/drm/vkms/vkms_dr= v.h index 55440ec6db5209741af1443d4e49e9471e6795c9..37ee569474223b2cf01e3cc0e4f= 119777533ae23 100644 --- a/drivers/gpu/drm/vkms/vkms_drv.h +++ b/drivers/gpu/drm/vkms/vkms_drv.h @@ -305,6 +305,6 @@ void vkms_writeback_row(struct vkms_writeback_job *wb, = const struct line_buffer int vkms_enable_writeback_connector(struct vkms_device *vkmsdev, struct vk= ms_output *vkms_out); =20 /* Colorops */ -int vkms_initialize_colorops(struct drm_plane *plane); +int vkms_initialize_pre_blend_colorops(struct drm_plane *plane); =20 #endif /* _VKMS_DRV_H_ */ diff --git a/drivers/gpu/drm/vkms/vkms_plane.c b/drivers/gpu/drm/vkms/vkms_= plane.c index db8d26810afa8d8fcab48a6db2e691255f26a8a6..8e63a07a7e1b0a350361d0b03b7= 911bfa9ce3dcc 100644 --- a/drivers/gpu/drm/vkms/vkms_plane.c +++ b/drivers/gpu/drm/vkms/vkms_plane.c @@ -232,7 +232,7 @@ struct vkms_plane *vkms_plane_init(struct vkms_device *= vkmsdev, DRM_COLOR_YCBCR_BT601, DRM_COLOR_YCBCR_FULL_RANGE); =20 - vkms_initialize_colorops(&plane->base); + vkms_initialize_pre_blend_colorops(&plane->base); =20 return plane; } --=20 2.50.1 From nobody Thu Oct 2 10:39:58 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CE201386C9 for ; Thu, 18 Sep 2025 00:45:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758156338; cv=none; b=ss9JfDbJrG9lA0b9dWvHRthATbCXjSIj3NnHfoIi2ja1XhX/phOEmSZHv57kpV+/tT3d22kXSJArf4g+wWdVliysXn+rSs5pN76CA58Y1huWWiOwOnfzJB4r8/HrGXrGso6bILa817Jr89dDcfRvMsCw4GhvbleBJSqIu4qimgY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758156338; c=relaxed/simple; bh=63UDJCYYZKejAD7rK2QDvVeqxIbIk1HH1HrY2XmPNcY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Thu, 18 Sep 2025 02:45:27 +0200 (CEST) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Wed, 17 Sep 2025 20:43:27 -0400 Subject: [PATCH RFC v2 18/20] drm/vkms: Prepare pre_blend_color_transform() for post-blend pipelines Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-mtk-post-blend-color-pipeline-v2-18-ac4471b44758@collabora.com> References: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> In-Reply-To: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Haneen Mohammed , Melissa Wen Cc: Alex Hung , wayland-devel@lists.freedesktop.org, harry.wentland@amd.com, leo.liu@amd.com, ville.syrjala@linux.intel.com, pekka.paalanen@collabora.com, contact@emersion.fr, mwen@igalia.com, jadahl@redhat.com, sebastian.wick@redhat.com, shashank.sharma@amd.com, agoins@nvidia.com, joshua@froggi.es, mdaenzer@redhat.com, aleixpol@kde.org, xaver.hugl@gmail.com, victoria@system76.com, uma.shankar@intel.com, quic_naseer@quicinc.com, quic_cbraga@quicinc.com, quic_abhinavk@quicinc.com, marcan@marcan.st, Liviu.Dudau@arm.com, sashamcintosh@google.com, chaitanya.kumar.borah@intel.com, louis.chauvet@bootlin.com, mcanal@igalia.com, kernel@collabora.com, daniels@collabora.com, leandro.ribeiro@collabora.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Simona Vetter X-Mailer: b4 0.14.2 As a preparatory step for supporting post-blend color pipelines in VKMS, rename pre_blend_color_transform() to color_transform() and make it take the first colorop instead of a plane state, so it can be shared by both pre- and post-blend color pipeline code paths. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Harry Wentland Reviewed-by: Louis Chauvet --- drivers/gpu/drm/vkms/vkms_composer.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/vkms/vkms_composer.c b/drivers/gpu/drm/vkms/vk= ms_composer.c index 31b1dd3cd115d930ec3ed498403a8f44208d76c3..05e1551d6330e4dc14563d3a399= b3544d11c6576 100644 --- a/drivers/gpu/drm/vkms/vkms_composer.c +++ b/drivers/gpu/drm/vkms/vkms_composer.c @@ -189,13 +189,13 @@ static void apply_colorop(struct pixel_argb_s32 *pixe= l, struct drm_colorop *colo } } =20 -static void pre_blend_color_transform(const struct vkms_plane_state *plane= _state, - struct line_buffer *output_buffer) +static void color_transform(struct drm_colorop *first_colorop, + struct line_buffer *output_buffer) { struct pixel_argb_s32 pixel; =20 for (size_t x =3D 0; x < output_buffer->n_pixels; x++) { - struct drm_colorop *colorop =3D plane_state->base.base.color_pipeline; + struct drm_colorop *colorop =3D first_colorop; =20 /* * Some operations, such as applying a BT709 encoding matrix, @@ -449,7 +449,7 @@ static void blend_line(struct vkms_plane_state *current= _plane, int y, */ current_plane->pixel_read_line(current_plane, src_x_start, src_y_start, d= irection, pixel_count, &stage_buffer->pixels[dst_x_start]); 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-mtk-post-blend-color-pipeline-v2-19-ac4471b44758@collabora.com> References: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> In-Reply-To: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Haneen Mohammed , Melissa Wen Cc: Alex Hung , wayland-devel@lists.freedesktop.org, harry.wentland@amd.com, leo.liu@amd.com, ville.syrjala@linux.intel.com, pekka.paalanen@collabora.com, contact@emersion.fr, mwen@igalia.com, jadahl@redhat.com, sebastian.wick@redhat.com, shashank.sharma@amd.com, agoins@nvidia.com, joshua@froggi.es, mdaenzer@redhat.com, aleixpol@kde.org, xaver.hugl@gmail.com, victoria@system76.com, uma.shankar@intel.com, quic_naseer@quicinc.com, quic_cbraga@quicinc.com, quic_abhinavk@quicinc.com, marcan@marcan.st, Liviu.Dudau@arm.com, sashamcintosh@google.com, chaitanya.kumar.borah@intel.com, louis.chauvet@bootlin.com, mcanal@igalia.com, kernel@collabora.com, daniels@collabora.com, leandro.ribeiro@collabora.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Simona Vetter X-Mailer: b4 0.14.2 Introduce a post-blend color pipeline with the same colorop blocks as the pre-blend color pipeline. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Harry Wentland --- drivers/gpu/drm/vkms/vkms_colorop.c | 98 ++++++++++++++++++++++++++++++++= ++++ drivers/gpu/drm/vkms/vkms_composer.c | 5 +- drivers/gpu/drm/vkms/vkms_crtc.c | 1 + drivers/gpu/drm/vkms/vkms_drv.h | 1 + 4 files changed, 104 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/vkms/vkms_colorop.c b/drivers/gpu/drm/vkms/vkm= s_colorop.c index 5924ae2bd40fc904048f99bc9b96308140709e25..54c512db68eef16435d5f794537= 84f7784d540fb 100644 --- a/drivers/gpu/drm/vkms/vkms_colorop.c +++ b/drivers/gpu/drm/vkms/vkms_colorop.c @@ -98,6 +98,86 @@ vkms_initialize_pre_blend_color_pipeline(struct drm_plan= e *plane, return ret; } =20 +static int +vkms_initialize_post_blend_color_pipeline(struct drm_crtc *crtc, + struct drm_prop_enum_list *list) +{ + struct drm_colorop *ops[MAX_COLOR_PIPELINE_OPS]; + struct drm_device *dev =3D crtc->dev; + int ret; + int i =3D 0; + + memset(ops, 0, sizeof(ops)); + + /* 1st op: 1d curve */ + ops[i] =3D kzalloc(sizeof(*ops[i]), GFP_KERNEL); + if (!ops[i]) { + ret =3D -ENOMEM; + goto cleanup; + } + + ret =3D drm_crtc_colorop_curve_1d_init(dev, ops[i], crtc, supported_tfs, + DRM_COLOROP_FLAG_ALLOW_BYPASS); + if (ret) + goto cleanup; + + list->type =3D ops[i]->base.id; + list->name =3D kasprintf(GFP_KERNEL, "Color Pipeline %d", ops[i]->base.id= ); + + i++; + + /* 2nd op: 3x4 matrix */ + ops[i] =3D kzalloc(sizeof(*ops[i]), GFP_KERNEL); + if (!ops[i]) { + ret =3D -ENOMEM; + goto cleanup; + } + + ret =3D drm_crtc_colorop_ctm_3x4_init(dev, ops[i], crtc, DRM_COLOROP_FLAG= _ALLOW_BYPASS); + if (ret) + goto cleanup; + + drm_colorop_set_next_property(ops[i - 1], ops[i]); + + i++; + + /* 3rd op: 3x4 matrix */ + ops[i] =3D kzalloc(sizeof(*ops[i]), GFP_KERNEL); + if (!ops[i]) { + ret =3D -ENOMEM; + goto cleanup; + } + + ret =3D drm_crtc_colorop_ctm_3x4_init(dev, ops[i], crtc, DRM_COLOROP_FLAG= _ALLOW_BYPASS); + if (ret) + goto cleanup; + + drm_colorop_set_next_property(ops[i - 1], ops[i]); + + i++; + + /* 4th op: 1d curve */ + ops[i] =3D kzalloc(sizeof(*ops[i]), GFP_KERNEL); + if (!ops[i]) { + ret =3D -ENOMEM; + goto cleanup; + } + + ret =3D drm_crtc_colorop_curve_1d_init(dev, ops[i], crtc, supported_tfs, + DRM_COLOROP_FLAG_ALLOW_BYPASS); + if (ret) + goto cleanup; + + drm_colorop_set_next_property(ops[i - 1], ops[i]); + + return 0; + +cleanup: + drm_colorop_pipeline_destroy(dev); + + return ret; +} + int vkms_initialize_pre_blend_colorops(struct drm_plane *plane) { struct drm_prop_enum_list pipeline; @@ -115,3 +195,21 @@ int vkms_initialize_pre_blend_colorops(struct drm_plan= e *plane) =20 return 0; } + +int vkms_initialize_post_blend_colorops(struct drm_crtc *crtc) +{ + struct drm_prop_enum_list pipeline; + int ret; + + /* Add color pipeline */ + ret =3D vkms_initialize_post_blend_color_pipeline(crtc, &pipeline); + if (ret) + return ret; + + /* Create COLOR_PIPELINE property and attach */ + ret =3D drm_crtc_create_color_pipeline_property(crtc, &pipeline, 1); + if (ret) + return ret; + + return 0; +} diff --git a/drivers/gpu/drm/vkms/vkms_composer.c b/drivers/gpu/drm/vkms/vk= ms_composer.c index 05e1551d6330e4dc14563d3a399b3544d11c6576..efe09538768b01108a305f0ace7= 65246220b487b 100644 --- a/drivers/gpu/drm/vkms/vkms_composer.c +++ b/drivers/gpu/drm/vkms/vkms_composer.c @@ -495,7 +495,10 @@ static void blend(struct vkms_writeback_job *wb, blend_line(plane[i], y, crtc_x_limit, stage_buffer, output_buffer); } =20 - apply_lut(crtc_state, output_buffer); + if (crtc_state->base.color_pipeline_enabled) + color_transform(crtc_state->base.color_pipeline, output_buffer); + else + apply_lut(crtc_state, output_buffer); =20 *crc32 =3D crc32_le(*crc32, (void *)output_buffer->pixels, row_size); =20 diff --git a/drivers/gpu/drm/vkms/vkms_crtc.c b/drivers/gpu/drm/vkms/vkms_c= rtc.c index e60573e0f3e9510252e1f198b00e28bcc7987620..04737c1fb70e4f0aef480a180e5= 7a76fbc279dfa 100644 --- a/drivers/gpu/drm/vkms/vkms_crtc.c +++ b/drivers/gpu/drm/vkms/vkms_crtc.c @@ -295,6 +295,7 @@ struct vkms_output *vkms_crtc_init(struct drm_device *d= ev, struct drm_plane *pri } =20 drm_crtc_enable_color_mgmt(crtc, 0, false, VKMS_LUT_SIZE); + vkms_initialize_post_blend_colorops(crtc); =20 spin_lock_init(&vkms_out->lock); spin_lock_init(&vkms_out->composer_lock); diff --git a/drivers/gpu/drm/vkms/vkms_drv.h b/drivers/gpu/drm/vkms/vkms_dr= v.h index 37ee569474223b2cf01e3cc0e4f119777533ae23..a0308c2263d1858a72906853960= ea7d1bbecd03e 100644 --- a/drivers/gpu/drm/vkms/vkms_drv.h +++ b/drivers/gpu/drm/vkms/vkms_drv.h @@ -306,5 +306,6 @@ int vkms_enable_writeback_connector(struct vkms_device = *vkmsdev, struct vkms_out =20 /* Colorops */ int vkms_initialize_pre_blend_colorops(struct drm_plane *plane); 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Thu, 18 Sep 2025 02:45:41 +0200 (CEST) From: =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= Date: Wed, 17 Sep 2025 20:43:29 -0400 Subject: [PATCH RFC v2 20/20] drm/vkms: Set post-blend color pipeline driver cap Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-mtk-post-blend-color-pipeline-v2-20-ac4471b44758@collabora.com> References: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> In-Reply-To: <20250917-mtk-post-blend-color-pipeline-v2-0-ac4471b44758@collabora.com> To: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Haneen Mohammed , Melissa Wen Cc: Alex Hung , wayland-devel@lists.freedesktop.org, harry.wentland@amd.com, leo.liu@amd.com, ville.syrjala@linux.intel.com, pekka.paalanen@collabora.com, contact@emersion.fr, mwen@igalia.com, jadahl@redhat.com, sebastian.wick@redhat.com, shashank.sharma@amd.com, agoins@nvidia.com, joshua@froggi.es, mdaenzer@redhat.com, aleixpol@kde.org, xaver.hugl@gmail.com, victoria@system76.com, uma.shankar@intel.com, quic_naseer@quicinc.com, quic_cbraga@quicinc.com, quic_abhinavk@quicinc.com, marcan@marcan.st, Liviu.Dudau@arm.com, sashamcintosh@google.com, chaitanya.kumar.borah@intel.com, louis.chauvet@bootlin.com, mcanal@igalia.com, kernel@collabora.com, daniels@collabora.com, leandro.ribeiro@collabora.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?N=C3=ADcolas_F=2E_R=2E_A=2E_Prado?= , Simona Vetter X-Mailer: b4 0.14.2 Now that the driver implements post-blend color pipelines, set the driver cap so they can be used from userspace. Signed-off-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: Harry Wentland Reviewed-by: Louis Chauvet --- drivers/gpu/drm/vkms/vkms_drv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/vkms/vkms_drv.c b/drivers/gpu/drm/vkms/vkms_dr= v.c index e8472d9b6e3b2b5d6d497763288bf3dc6fde5987..4cc67a789d28288575235b7efc8= 7bc5e45d668cc 100644 --- a/drivers/gpu/drm/vkms/vkms_drv.c +++ b/drivers/gpu/drm/vkms/vkms_drv.c @@ -80,7 +80,8 @@ static void vkms_atomic_commit_tail(struct drm_atomic_sta= te *old_state) } =20 static const struct drm_driver vkms_driver =3D { - .driver_features =3D DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_GEM, + .driver_features =3D DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_GEM | + DRIVER_POST_BLEND_COLOR_PIPELINE, .fops =3D &vkms_driver_fops, DRM_GEM_SHMEM_DRIVER_OPS, DRM_FBDEV_SHMEM_DRIVER_OPS, --=20 2.50.1