From nobody Thu Oct 2 12:06:48 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C70931A7F8; Wed, 17 Sep 2025 12:23:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758111844; cv=pass; b=IBSW/uM+PF5XwY2EZ5+LKORrsxvpzhlDp53G73dZXROsZoPVwg32HlHng8eUTVGqqhPTVo6mHD4YVKfJPvsfHv/e0vvLULwXxTQl9G6ocwbKMwFXs8EVWS8DDj0Nwdeu7GfSVNUkXCVwR8uu6Wwn+/KJGdSkp2D/DHYQMBVYW44= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758111844; c=relaxed/simple; bh=hNHMmIz6jcEA3/Yt5j8PNNjkdw1tXRlPD7BnSP+FpDQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=igFiuG2mWBhkQDssNbsggeht8oGJy2zaq9CJXdmGMfDpyvGhbC/5OPbouc98UoLAPm4f97uFgBu99XVQkvy8gY/kMpZfax851UugZP9e8KBlCwII8OeS923UXOk5G+fEmZ8zg55t4g7kjUcGlJyCw2Y/Dwk1YnadjpWv/Z7NfRg= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=QPMUjIHQ; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="QPMUjIHQ" ARC-Seal: i=1; a=rsa-sha256; t=1758111806; cv=none; d=zohomail.com; s=zohoarc; b=a8XoYQt60pePKrnVirjs/CoerURRZ1a9yNEbQflRUOUPUPyEBhumR6nPQvmZwREZOETwh9mpuO0KDmYIKhOEYT58Z7ijl015V/Tnwk/ZTDwJVdZ6kPFSAzMO2XbJculnEu2fRe8qa7cTbFE2t7mgQu/xsZTH19wbU51XWyKxZHw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758111806; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=uurEV4t79lUgHGzzrcapEhqlS/tLXxa4Px+GQkvoJNc=; b=Fa9KS/3tG/7o0wvNrltzeUXLfzZkuxEY9fnKPqlxsqOlMWtmroTNzz1h9Pt3pqmCLY+ugWokOo0h0GGMrNRW2U4jWBI5pnAzTaf6f3FRRWuhxTMg38Yq2Mi5YhVQlxX91A1wKpNUaeDIXejpmRVz+dw7KbSz3snKH/Vk0lFRx/U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1758111806; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=uurEV4t79lUgHGzzrcapEhqlS/tLXxa4Px+GQkvoJNc=; b=QPMUjIHQbBr8IpCEw43ARVZSwMwQHVOXEsxxUvhD9v9orGxJEBzNLj2r0GNIdeJV QkE42+0jmvOZ0T3uNIN5r8HpnEFOHzMGLJ/Xpc0AwRR5uKNYkc8XSMlax1lGXSuV59q QZXoxjTkAE73UL1/UznAb4a4isRrFfA1PVzmIXBI= Received: by mx.zohomail.com with SMTPS id 1758111803957814.8917413770764; Wed, 17 Sep 2025 05:23:23 -0700 (PDT) From: Nicolas Frattaroli Date: Wed, 17 Sep 2025 14:22:35 +0200 Subject: [PATCH v3 04/10] dt-bindings: mailbox: Add MT8196 GPUEB Mailbox Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-mt8196-gpufreq-v3-4-c4ede4b4399e@collabora.com> References: <20250917-mt8196-gpufreq-v3-0-c4ede4b4399e@collabora.com> In-Reply-To: <20250917-mt8196-gpufreq-v3-0-c4ede4b4399e@collabora.com> To: AngeloGioacchino Del Regno , Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Jassi Brar , Kees Cook , "Gustavo A. R. Silva" , Chia-I Wu , Chen-Yu Tsai Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, linux-hardening@vger.kernel.org, Nicolas Frattaroli , Conor Dooley X-Mailer: b4 0.14.2 The MediaTek MT8196 SoC includes an embedded MCU referred to as "GPUEB", acting as glue logic to control power and frequency of the Mali GPU. This MCU runs special-purpose firmware for this use, and the main application processor communicates with it through a mailbox. Add a binding that describes this mailbox. Acked-by: Conor Dooley Signed-off-by: Nicolas Frattaroli Reviewed-by: AngeloGioacchino Del Regno --- .../mailbox/mediatek,mt8196-gpueb-mbox.yaml | 64 ++++++++++++++++++= ++++ 1 file changed, 64 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/mediatek,mt8196-gpue= b-mbox.yaml b/Documentation/devicetree/bindings/mailbox/mediatek,mt8196-gpu= eb-mbox.yaml new file mode 100644 index 0000000000000000000000000000000000000000..ab5b780cb83a708a3897ca1a440= 131d97b56c3a6 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/mediatek,mt8196-gpueb-mbox.= yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/mediatek,mt8196-gpueb-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MFlexGraphics GPUEB Mailbox Controller + +maintainers: + - Nicolas Frattaroli + +properties: + compatible: + enum: + - mediatek,mt8196-gpueb-mbox + + reg: + items: + - description: mailbox data registers + - description: mailbox control registers + + reg-names: + items: + - const: data + - const: ctl + + clocks: + items: + - description: main clock of the GPUEB MCU + + interrupts: + items: + - description: fires when a new message is received + + "#mbox-cells": + const: 1 + description: + The number of the mailbox channel. + +required: + - compatible + - reg + - reg-names + - clocks + - interrupts + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + #include + #include + #include + + mailbox@4b09fd80 { + compatible =3D "mediatek,mt8196-gpueb-mbox"; + reg =3D <0x4b09fd80 0x280>, + <0x4b170000 0x7c>; + reg-names =3D "data", "ctl"; + clocks =3D <&topckgen CLK_TOP_MFG_EB>; + interrupts =3D ; + #mbox-cells =3D <1>; + }; --=20 2.51.0