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R. Silva" , Chia-I Wu , Chen-Yu Tsai Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, linux-hardening@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 The Mali-based GPU on the MediaTek MT8196 SoC uses a separate MCU to control the power and frequency of the GPU. It lets us omit the OPP tables from the device tree, as those can now be enumerated at runtime from the MCU. It also means the mali GPU node described in this binding does not have any clocks in this case, as all clock control is delegated to the MCU. Add the mediatek,mt8196-mali compatible, and a performance-domains property which points to the MCU's device tree node in this case. It's required on mt8196 devices. Signed-off-by: Nicolas Frattaroli --- .../bindings/gpu/arm,mali-valhall-csf.yaml | 32 ++++++++++++++++++= ++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yam= l b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml index 7ad5a3ffc5f5c753322eda9e74cc65de89d11c73..ccab2dd0ea852187e3ab75923e1= 9739622b2b3b8 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml @@ -38,7 +38,6 @@ properties: - const: gpu =20 clocks: - minItems: 1 maxItems: 3 =20 clock-names: @@ -54,6 +53,9 @@ properties: opp-table: type: object =20 + performance-domains: + maxItems: 1 + power-domains: minItems: 1 maxItems: 5 @@ -92,7 +94,6 @@ required: - interrupts - interrupt-names - clocks - - mali-supply =20 additionalProperties: false =20 @@ -106,9 +107,26 @@ allOf: properties: clocks: minItems: 3 + performance-domains: false power-domains: maxItems: 1 power-domain-names: false + required: + - mali-supply + - if: + properties: + compatible: + contains: + const: mediatek,mt8196-mali + then: + properties: + mali-supply: false + sram-supply: false + operating-points-v2: false + clocks: false + clock-names: false + required: + - performance-domains =20 examples: - | @@ -144,5 +162,15 @@ examples: }; }; }; + - | + gpu@48000000 { + compatible =3D "mediatek,mt8196-mali", "arm,mali-valhall-csf"; + reg =3D <0x48000000 0x480000>; + interrupts =3D , + , + ; + interrupt-names =3D "job", "mmu", "gpu"; + performance-domains =3D <&gpufreq>; + }; =20 ... --=20 2.51.0 From nobody Thu Oct 2 10:55:24 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CF952FBDF1; Wed, 17 Sep 2025 12:23:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758111820; cv=pass; b=Ur1GPT1eB05Tnwe8yEkAYVf+UO9iGv1RlkapM3IWdogyJc46UyqHtpZP/QYVEkWNgaBZsAY0alGbkhgn+AfvdJHaD1jA9LVbacSZzFuzBIno8ZGAoLdFgLmXP4KWnDxc0bJQg5npnaXEFMRDL9BThJouSC4MemoX5idPeA/UP7I= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; 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h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=TSOOSd0q3nKiD0MBVwkJ48zGfTq+ks978YmNhkmC9YQ=; b=S5CaLcumJ7rs6Md6yy14/YJvYczWvvUpwNFjmMUjD0g7S1Wj+04QKuS1T0IUFd9B GgHD85qqt9/veXEPcVgF+sjXfLQ6Wc0UdNrcB4N2T1YiW82lXghQczAKnqqoJ/C4xkK PKqkvKOS80BM9h8ZjVE4oEEyRJRUEKkb2qU/rt0M= Received: by mx.zohomail.com with SMTPS id 1758111789568560.3619392555413; Wed, 17 Sep 2025 05:23:09 -0700 (PDT) From: Nicolas Frattaroli Date: Wed, 17 Sep 2025 14:22:33 +0200 Subject: [PATCH v3 02/10] dt-bindings: devfreq: add mt8196-gpufreq binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-mt8196-gpufreq-v3-2-c4ede4b4399e@collabora.com> References: <20250917-mt8196-gpufreq-v3-0-c4ede4b4399e@collabora.com> In-Reply-To: <20250917-mt8196-gpufreq-v3-0-c4ede4b4399e@collabora.com> To: AngeloGioacchino Del Regno , Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Jassi Brar , Kees Cook , "Gustavo A. R. Silva" , Chia-I Wu , Chen-Yu Tsai Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, linux-hardening@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 On the MediaTek MT8196 SoC, the GPU has its power and frequency dynamically controlled by an embedded special-purpose MCU. This MCU is in charge of powering up the GPU silicon. It also provides us with a list of available OPPs at runtime, and is fully in control of all the regulator and clock fiddling it takes to reach a certain level of performance. It's also in charge of enforcing limits on power draw or temperature. Add a binding for this device in the devfreq subdirectory, where it seems to fit in best considering its tasks. Signed-off-by: Nicolas Frattaroli Reviewed-by: Krzysztof Kozlowski --- .../bindings/devfreq/mediatek,mt8196-gpufreq.yaml | 112 +++++++++++++++++= ++++ 1 file changed, 112 insertions(+) diff --git a/Documentation/devicetree/bindings/devfreq/mediatek,mt8196-gpuf= req.yaml b/Documentation/devicetree/bindings/devfreq/mediatek,mt8196-gpufre= q.yaml new file mode 100644 index 0000000000000000000000000000000000000000..b1c6751662c085eccdead038a2e= dc61e4bfc5f5f --- /dev/null +++ b/Documentation/devicetree/bindings/devfreq/mediatek,mt8196-gpufreq.yaml @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/devfreq/mediatek,mt8196-gpufreq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MFlexGraphics Performance Controller + +maintainers: + - Nicolas Frattaroli + +description: | + A special-purpose embedded MCU to control power and frequency of GPU dev= ices + using MediaTek Flexible Graphics integration hardware. + +properties: + $nodename: + pattern: '^performance-controller@[a-f0-9]+$' + + compatible: + enum: + - mediatek,mt8196-gpufreq + + reg: + items: + - description: GPR memory area + - description: RPC memory area + - description: SoC variant ID register + + reg-names: + items: + - const: gpr + - const: rpc + - const: hw-revision + + clocks: + items: + - description: main clock of the embedded controller (EB) + - description: core PLL + - description: stack 0 PLL + - description: stack 1 PLL + + clock-names: + items: + - const: eb + - const: core + - const: stack0 + - const: stack1 + + mboxes: + items: + - description: FastDVFS events + - description: frequency control + - description: sleep control + - description: timer control + - description: frequency hopping control + - description: hardware voter control + - description: FastDVFS control + + mbox-names: + items: + - const: fast-dvfs-event + - const: gpufreq + - const: sleep + - const: timer + - const: fhctl + - const: ccf + - const: fast-dvfs + + shmem: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the shared memory region of the GPUEB MCU + + "#performance-domain-cells": + const: 0 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - mboxes + - mbox-names + - shmem + - "#performance-domain-cells" + +additionalProperties: false + +examples: + - | + #include + + performance-controller@4b09fd00 { + compatible =3D "mediatek,mt8196-gpufreq"; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-mt8196-gpufreq-v3-3-c4ede4b4399e@collabora.com> References: <20250917-mt8196-gpufreq-v3-0-c4ede4b4399e@collabora.com> In-Reply-To: <20250917-mt8196-gpufreq-v3-0-c4ede4b4399e@collabora.com> To: AngeloGioacchino Del Regno , Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Jassi Brar , Kees Cook , "Gustavo A. R. Silva" , Chia-I Wu , Chen-Yu Tsai Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, linux-hardening@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 This compatible is used for an SRAM section that's shared between the MT8196's application processor cores and the embedded GPUEB MCU that controls the GPU frequency. Through this SRAM section, things about the GPU frequency controller like the OPP table can be read. Acked-by: Rob Herring (Arm) Signed-off-by: Nicolas Frattaroli Reviewed-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/sram/sram.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentati= on/devicetree/bindings/sram/sram.yaml index 7c1337e159f2371401ae99313375656fff014ed4..6ba0dd6a66def11f56a1d5276d7= 397b655bff11e 100644 --- a/Documentation/devicetree/bindings/sram/sram.yaml +++ b/Documentation/devicetree/bindings/sram/sram.yaml @@ -89,6 +89,7 @@ patternProperties: - arm,juno-scp-shmem - arm,scmi-shmem - arm,scp-shmem + - mediatek,mt8196-gpufreq-sram - renesas,smp-sram - rockchip,rk3066-smp-sram - samsung,exynos4210-sysram --=20 2.51.0 From nobody Thu Oct 2 10:55:24 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C70931A7F8; Wed, 17 Sep 2025 12:23:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758111844; cv=pass; b=IBSW/uM+PF5XwY2EZ5+LKORrsxvpzhlDp53G73dZXROsZoPVwg32HlHng8eUTVGqqhPTVo6mHD4YVKfJPvsfHv/e0vvLULwXxTQl9G6ocwbKMwFXs8EVWS8DDj0Nwdeu7GfSVNUkXCVwR8uu6Wwn+/KJGdSkp2D/DHYQMBVYW44= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758111844; c=relaxed/simple; bh=hNHMmIz6jcEA3/Yt5j8PNNjkdw1tXRlPD7BnSP+FpDQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=igFiuG2mWBhkQDssNbsggeht8oGJy2zaq9CJXdmGMfDpyvGhbC/5OPbouc98UoLAPm4f97uFgBu99XVQkvy8gY/kMpZfax851UugZP9e8KBlCwII8OeS923UXOk5G+fEmZ8zg55t4g7kjUcGlJyCw2Y/Dwk1YnadjpWv/Z7NfRg= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=QPMUjIHQ; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="QPMUjIHQ" ARC-Seal: i=1; a=rsa-sha256; t=1758111806; cv=none; d=zohomail.com; s=zohoarc; b=a8XoYQt60pePKrnVirjs/CoerURRZ1a9yNEbQflRUOUPUPyEBhumR6nPQvmZwREZOETwh9mpuO0KDmYIKhOEYT58Z7ijl015V/Tnwk/ZTDwJVdZ6kPFSAzMO2XbJculnEu2fRe8qa7cTbFE2t7mgQu/xsZTH19wbU51XWyKxZHw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1758111806; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=uurEV4t79lUgHGzzrcapEhqlS/tLXxa4Px+GQkvoJNc=; b=Fa9KS/3tG/7o0wvNrltzeUXLfzZkuxEY9fnKPqlxsqOlMWtmroTNzz1h9Pt3pqmCLY+ugWokOo0h0GGMrNRW2U4jWBI5pnAzTaf6f3FRRWuhxTMg38Yq2Mi5YhVQlxX91A1wKpNUaeDIXejpmRVz+dw7KbSz3snKH/Vk0lFRx/U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1758111806; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=uurEV4t79lUgHGzzrcapEhqlS/tLXxa4Px+GQkvoJNc=; b=QPMUjIHQbBr8IpCEw43ARVZSwMwQHVOXEsxxUvhD9v9orGxJEBzNLj2r0GNIdeJV QkE42+0jmvOZ0T3uNIN5r8HpnEFOHzMGLJ/Xpc0AwRR5uKNYkc8XSMlax1lGXSuV59q QZXoxjTkAE73UL1/UznAb4a4isRrFfA1PVzmIXBI= Received: by mx.zohomail.com with SMTPS id 1758111803957814.8917413770764; Wed, 17 Sep 2025 05:23:23 -0700 (PDT) From: Nicolas Frattaroli Date: Wed, 17 Sep 2025 14:22:35 +0200 Subject: [PATCH v3 04/10] dt-bindings: mailbox: Add MT8196 GPUEB Mailbox Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-mt8196-gpufreq-v3-4-c4ede4b4399e@collabora.com> References: <20250917-mt8196-gpufreq-v3-0-c4ede4b4399e@collabora.com> In-Reply-To: <20250917-mt8196-gpufreq-v3-0-c4ede4b4399e@collabora.com> To: AngeloGioacchino Del Regno , Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Jassi Brar , Kees Cook , "Gustavo A. R. Silva" , Chia-I Wu , Chen-Yu Tsai Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, linux-hardening@vger.kernel.org, Nicolas Frattaroli , Conor Dooley X-Mailer: b4 0.14.2 The MediaTek MT8196 SoC includes an embedded MCU referred to as "GPUEB", acting as glue logic to control power and frequency of the Mali GPU. This MCU runs special-purpose firmware for this use, and the main application processor communicates with it through a mailbox. Add a binding that describes this mailbox. Acked-by: Conor Dooley Signed-off-by: Nicolas Frattaroli Reviewed-by: AngeloGioacchino Del Regno --- .../mailbox/mediatek,mt8196-gpueb-mbox.yaml | 64 ++++++++++++++++++= ++++ 1 file changed, 64 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/mediatek,mt8196-gpue= b-mbox.yaml b/Documentation/devicetree/bindings/mailbox/mediatek,mt8196-gpu= eb-mbox.yaml new file mode 100644 index 0000000000000000000000000000000000000000..ab5b780cb83a708a3897ca1a440= 131d97b56c3a6 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/mediatek,mt8196-gpueb-mbox.= yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/mediatek,mt8196-gpueb-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MFlexGraphics GPUEB Mailbox Controller + +maintainers: + - Nicolas Frattaroli + +properties: + compatible: + enum: + - mediatek,mt8196-gpueb-mbox + + reg: + items: + - description: mailbox data registers + - description: mailbox control registers + + reg-names: + items: + - const: data + - const: ctl + + clocks: + items: + - description: main clock of the GPUEB MCU + + interrupts: + items: + - description: fires when a new message is received + + "#mbox-cells": + const: 1 + description: + The number of the mailbox channel. + +required: + - compatible + - reg + - reg-names + - clocks + - interrupts + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + #include + #include + #include + + mailbox@4b09fd80 { + compatible =3D "mediatek,mt8196-gpueb-mbox"; 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Wed, 17 Sep 2025 05:23:31 -0700 (PDT) From: Nicolas Frattaroli Date: Wed, 17 Sep 2025 14:22:36 +0200 Subject: [PATCH v3 05/10] mailbox: add MediaTek GPUEB IPI mailbox Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-mt8196-gpufreq-v3-5-c4ede4b4399e@collabora.com> References: <20250917-mt8196-gpufreq-v3-0-c4ede4b4399e@collabora.com> In-Reply-To: <20250917-mt8196-gpufreq-v3-0-c4ede4b4399e@collabora.com> To: AngeloGioacchino Del Regno , Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Jassi Brar , Kees Cook , "Gustavo A. R. Silva" , Chia-I Wu , Chen-Yu Tsai Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, linux-hardening@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 The MT8196 SoC uses an embedded MCU to control frequencies and power of the GPU. This controller is referred to as "GPUEB". It communicates to the application processor, among other ways, through a mailbox. The mailbox exposes one interrupt, which appears to only be fired when a response is received, rather than a transaction is completed. For us, this means we unfortunately need to poll for txdone. The mailbox also requires the EB clock to be on when touching any of the mailbox registers. Add a simple driver for it based on the common mailbox framework. Signed-off-by: Nicolas Frattaroli Reviewed-by: AngeloGioacchino Del Regno --- drivers/mailbox/Kconfig | 10 ++ drivers/mailbox/Makefile | 2 + drivers/mailbox/mtk-gpueb-mailbox.c | 330 ++++++++++++++++++++++++++++++++= ++++ 3 files changed, 342 insertions(+) diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 02432d4a5ccd46a16156a09c7f277fb03e4013f5..2016defda1fabb5c0fcc8078f84= a52d4e4e00167 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -294,6 +294,16 @@ config MTK_CMDQ_MBOX critical time limitation, such as updating display configuration during the vblank. =20 +config MTK_GPUEB_MBOX + tristate "MediaTek GPUEB Mailbox Support" + depends on ARCH_MEDIATEK || COMPILE_TEST + help + The MediaTek GPUEB mailbox is used to communicate with the embedded + controller in charge of GPU frequency and power management on some + MediaTek SoCs, such as the MT8196. + Say Y or m here if you want to support the MT8196 SoC in your kernel + build. + config ZYNQMP_IPI_MBOX tristate "Xilinx ZynqMP IPI Mailbox" depends on ARCH_ZYNQMP && OF diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index 98a68f838486eed117d24296138bf59fda3f92e4..564d06e71313e6d1972e4a6036e= 1e78c8c7ec450 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -63,6 +63,8 @@ obj-$(CONFIG_MTK_ADSP_MBOX) +=3D mtk-adsp-mailbox.o =20 obj-$(CONFIG_MTK_CMDQ_MBOX) +=3D mtk-cmdq-mailbox.o =20 +obj-$(CONFIG_MTK_GPUEB_MBOX) +=3D mtk-gpueb-mailbox.o + obj-$(CONFIG_ZYNQMP_IPI_MBOX) +=3D zynqmp-ipi-mailbox.o =20 obj-$(CONFIG_SUN6I_MSGBOX) +=3D sun6i-msgbox.o diff --git a/drivers/mailbox/mtk-gpueb-mailbox.c b/drivers/mailbox/mtk-gpue= b-mailbox.c new file mode 100644 index 0000000000000000000000000000000000000000..b4a8dab5381f67da3783136cd15= 828f2df281dcf --- /dev/null +++ b/drivers/mailbox/mtk-gpueb-mailbox.c @@ -0,0 +1,330 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * MediaTek GPUEB mailbox driver for SoCs such as the MT8196 + * + * Copyright (C) 2025, Collabora Ltd. + * + * Developers harmed in the making of this driver: + * - Nicolas Frattaroli + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MBOX_CTL_TX_STS 0x0000 +#define MBOX_CTL_IRQ_SET 0x0004 +#define MBOX_CTL_IRQ_CLR 0x0074 +#define MBOX_CTL_RX_STS 0x0078 + +#define MBOX_FULL BIT(0) /* i.e. we've received data */ +#define MBOX_CLOGGED BIT(1) /* i.e. the channel is shutdown */ + +#define MBOX_MAX_RX_SIZE 32 /* in bytes */ + +struct mtk_gpueb_mbox { + struct device *dev; + struct clk *clk; + void __iomem *mbox_mmio; + void __iomem *mbox_ctl; + struct mbox_controller mbox; + struct mtk_gpueb_mbox_chan *ch; + int irq; + const struct mtk_gpueb_mbox_variant *v; +}; + +/** + * struct mtk_gpueb_mbox_chan - per-channel runtime data + * @ebm: pointer to the parent &struct mtk_gpueb_mbox mailbox + * @full_name: descriptive name of channel for IRQ subsystem + * @num: channel number, starting at 0 + * @rx_status: signifies whether channel reception is turned off, or full + * @c: pointer to the constant &struct mtk_gpueb_mbox_chan_desc channel da= ta + */ +struct mtk_gpueb_mbox_chan { + struct mtk_gpueb_mbox *ebm; + char *full_name; + u8 num; + atomic_t rx_status; + const struct mtk_gpueb_mbox_chan_desc *c; +}; + +/** + * struct mtk_gpueb_mbox_chan_desc - per-channel constant data + * @name: name of this channel + * @num: index of this channel, starting at 0 + * @tx_offset: byte offset measured from mmio base for outgoing data + * @tx_len: size, in bytes, of the outgoing data on this channel + * @rx_offset: bytes offset measured from mmio base for incoming data + * @rx_len: size, in bytes, of the incoming data on this channel + */ +struct mtk_gpueb_mbox_chan_desc { + const char *name; + const u8 num; + const u16 tx_offset; + const u8 tx_len; + const u16 rx_offset; + const u8 rx_len; +}; + +struct mtk_gpueb_mbox_variant { + const u8 num_channels; + const struct mtk_gpueb_mbox_chan_desc channels[] __counted_by(num_channel= s); +}; + +/** + * mtk_gpueb_mbox_read_rx - read RX buffer from MMIO into channel's RX buf= fer + * @buf: buffer to read into + * @chan: pointer to the channel to read + */ +static void mtk_gpueb_mbox_read_rx(void *buf, struct mtk_gpueb_mbox_chan *= chan) +{ + memcpy_fromio(buf, chan->ebm->mbox_mmio + chan->c->rx_offset, chan->c->rx= _len); +} + +static irqreturn_t mtk_gpueb_mbox_isr(int irq, void *data) +{ + struct mtk_gpueb_mbox_chan *ch =3D data; + u32 rx_sts; + + rx_sts =3D readl(ch->ebm->mbox_ctl + MBOX_CTL_RX_STS); + + if (rx_sts & BIT(ch->num)) { + if (!atomic_cmpxchg(&ch->rx_status, 0, MBOX_FULL | MBOX_CLOGGED)) + return IRQ_WAKE_THREAD; + } + + return IRQ_NONE; +} + +static irqreturn_t mtk_gpueb_mbox_thread(int irq, void *data) +{ + struct mtk_gpueb_mbox_chan *ch =3D data; + u8 buf[MBOX_MAX_RX_SIZE] =3D {}; + int status; + + status =3D atomic_cmpxchg(&ch->rx_status, + MBOX_FULL | MBOX_CLOGGED, MBOX_FULL); + if (status =3D=3D (MBOX_FULL | MBOX_CLOGGED)) { + mtk_gpueb_mbox_read_rx(buf, ch); + writel(BIT(ch->num), ch->ebm->mbox_ctl + MBOX_CTL_IRQ_CLR); + mbox_chan_received_data(&ch->ebm->mbox.chans[ch->num], buf); + atomic_set(&ch->rx_status, 0); + return IRQ_HANDLED; + } + + return IRQ_NONE; +} + +static int mtk_gpueb_mbox_send_data(struct mbox_chan *chan, void *data) +{ + struct mtk_gpueb_mbox_chan *ch =3D chan->con_priv; + int i; + u32 *values =3D data; + + if (atomic_read(&ch->rx_status)) + return -EBUSY; + + /* + * We don't want any fancy nonsense, just write the 32-bit values in + * order. memcpy_toio/__iowrite32_copy don't work here, because fancy. + */ + for (i =3D 0; i < ch->c->tx_len; i +=3D 4) + writel(values[i / 4], ch->ebm->mbox_mmio + ch->c->tx_offset + i); + + writel(BIT(ch->num), ch->ebm->mbox_ctl + MBOX_CTL_IRQ_SET); + + return 0; +} + +static int mtk_gpueb_mbox_startup(struct mbox_chan *chan) +{ + struct mtk_gpueb_mbox_chan *ch =3D chan->con_priv; + int ret; + + atomic_set(&ch->rx_status, 0); + + ret =3D clk_enable(ch->ebm->clk); + if (ret) { + dev_err(ch->ebm->dev, "Failed to enable EB clock: %pe\n", + ERR_PTR(ret)); + goto err_clog; + } + + writel(BIT(ch->num), ch->ebm->mbox_ctl + MBOX_CTL_IRQ_CLR); + + ret =3D devm_request_threaded_irq(ch->ebm->dev, ch->ebm->irq, mtk_gpueb_m= box_isr, + mtk_gpueb_mbox_thread, IRQF_SHARED | IRQF_ONESHOT, + ch->full_name, ch); + if (ret) { + dev_err(ch->ebm->dev, "Failed to request IRQ: %pe\n", + ERR_PTR(ret)); + goto err_unclk; + } + + return 0; + +err_unclk: + clk_disable(ch->ebm->clk); +err_clog: + atomic_set(&ch->rx_status, MBOX_CLOGGED); + + return ret; +} + +static void mtk_gpueb_mbox_shutdown(struct mbox_chan *chan) +{ + struct mtk_gpueb_mbox_chan *ch =3D chan->con_priv; + + atomic_set(&ch->rx_status, MBOX_CLOGGED); + + devm_free_irq(ch->ebm->dev, ch->ebm->irq, ch); + + clk_disable(ch->ebm->clk); +} + +static bool mtk_gpueb_mbox_last_tx_done(struct mbox_chan *chan) +{ + struct mtk_gpueb_mbox_chan *ch =3D chan->con_priv; + + return !(readl(ch->ebm->mbox_ctl + MBOX_CTL_TX_STS) & BIT(ch->num)); +} + +const struct mbox_chan_ops mtk_gpueb_mbox_ops =3D { + .send_data =3D mtk_gpueb_mbox_send_data, + .startup =3D mtk_gpueb_mbox_startup, + .shutdown =3D mtk_gpueb_mbox_shutdown, + .last_tx_done =3D mtk_gpueb_mbox_last_tx_done, +}; + +static struct mbox_chan * +mtk_gpueb_mbox_of_xlate(struct mbox_controller *mbox, + const struct of_phandle_args *sp) +{ + struct mtk_gpueb_mbox *ebm =3D dev_get_drvdata(mbox->dev); + + if (!sp->args_count) + return ERR_PTR(-EINVAL); + + if (sp->args[0] >=3D ebm->v->num_channels) + return ERR_PTR(-ECHRNG); + + return &mbox->chans[sp->args[0]]; +} + +static int mtk_gpueb_mbox_probe(struct platform_device *pdev) +{ + struct mtk_gpueb_mbox *ebm; + unsigned int i; + + ebm =3D devm_kzalloc(&pdev->dev, sizeof(*ebm), GFP_KERNEL); + if (!ebm) + return -ENOMEM; + + ebm->dev =3D &pdev->dev; + ebm->v =3D of_device_get_match_data(ebm->dev); + + ebm->irq =3D platform_get_irq(pdev, 0); + if (ebm->irq < 0) + return ebm->irq; + + ebm->clk =3D devm_clk_get_prepared(ebm->dev, NULL); + if (IS_ERR(ebm->clk)) + return dev_err_probe(ebm->dev, PTR_ERR(ebm->clk), + "Failed to get 'eb' clock\n"); + + ebm->mbox_mmio =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(ebm->mbox_mmio)) + return dev_err_probe(ebm->dev, PTR_ERR(ebm->mbox_mmio), + "Couldn't map mailbox data registers\n"); + + ebm->mbox_ctl =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(ebm->mbox_ctl)) + return dev_err_probe( + ebm->dev, PTR_ERR(ebm->mbox_ctl), + "Couldn't map mailbox control registers\n"); + + ebm->ch =3D devm_kmalloc_array(ebm->dev, ebm->v->num_channels, + sizeof(*ebm->ch), GFP_KERNEL); + if (!ebm->ch) + return -ENOMEM; + + ebm->mbox.chans =3D devm_kcalloc(ebm->dev, ebm->v->num_channels, + sizeof(struct mbox_chan), GFP_KERNEL); + if (!ebm->mbox.chans) + return -ENOMEM; + + for (i =3D 0; i < ebm->v->num_channels; i++) { + ebm->ch[i].c =3D &ebm->v->channels[i]; + if (ebm->ch[i].c->rx_len > MBOX_MAX_RX_SIZE) { + dev_err(ebm->dev, "Channel %s RX size (%d) too large\n", + ebm->ch[i].c->name, ebm->ch[i].c->rx_len); + return -EINVAL; + } + ebm->ch[i].full_name =3D devm_kasprintf(ebm->dev, GFP_KERNEL, "%s:%s", + dev_name(ebm->dev), ebm->ch[i].c->name); + if (!ebm->ch[i].full_name) + return -ENOMEM; + + ebm->ch[i].ebm =3D ebm; + ebm->ch[i].num =3D i; + spin_lock_init(&ebm->mbox.chans[i].lock); + ebm->mbox.chans[i].con_priv =3D &ebm->ch[i]; + atomic_set(&ebm->ch[i].rx_status, MBOX_CLOGGED); + } + + ebm->mbox.dev =3D ebm->dev; + ebm->mbox.num_chans =3D ebm->v->num_channels; + ebm->mbox.txdone_poll =3D true; + ebm->mbox.txpoll_period =3D 0; /* minimum hrtimer interval */ + ebm->mbox.of_xlate =3D mtk_gpueb_mbox_of_xlate; + ebm->mbox.ops =3D &mtk_gpueb_mbox_ops; + + dev_set_drvdata(ebm->dev, ebm); + + return devm_mbox_controller_register(ebm->dev, &ebm->mbox); +} + +static const struct mtk_gpueb_mbox_variant mtk_gpueb_mbox_mt8196 =3D { + .num_channels =3D 12, + .channels =3D { + { "fast-dvfs-event", 0, 0x0000, 16, 0x00e0, 16 }, + { "gpufreq", 1, 0x0010, 32, 0x00f0, 32 }, + { "sleep", 2, 0x0030, 12, 0x0110, 4 }, + { "timer", 3, 0x003c, 24, 0x0114, 4 }, + { "fhctl", 4, 0x0054, 36, 0x0118, 4 }, + { "ccf", 5, 0x0078, 16, 0x011c, 16 }, + { "gpumpu", 6, 0x0088, 24, 0x012c, 4 }, + { "fast-dvfs", 7, 0x00a0, 24, 0x0130, 24 }, + { "ipir-c-met", 8, 0x00b8, 4, 0x0148, 16 }, + { "ipis-c-met", 9, 0x00bc, 16, 0x0158, 4 }, + { "brisket", 10, 0x00cc, 16, 0x015c, 16 }, + { "ppb", 11, 0x00dc, 4, 0x016c, 4 }, + }, +}; + +static const struct of_device_id mtk_gpueb_mbox_of_ids[] =3D { + { .compatible =3D "mediatek,mt8196-gpueb-mbox", .data =3D &mtk_gpueb_mbox= _mt8196 }, + { /* Sentinel */ } +}; +MODULE_DEVICE_TABLE(of, mtk_gpueb_mbox_of_ids); + +static struct platform_driver mtk_gpueb_mbox_drv =3D { + .probe =3D mtk_gpueb_mbox_probe, + .driver =3D { + .name =3D "mtk-gpueb-mbox", + .of_match_table =3D mtk_gpueb_mbox_of_ids, + } +}; +module_platform_driver(mtk_gpueb_mbox_drv); + +MODULE_AUTHOR("Nicolas Frattaroli "); +MODULE_DESCRIPTION("MediaTek GPUEB mailbox driver"); +MODULE_LICENSE("GPL"); --=20 2.51.0 From nobody Thu Oct 2 10:55:24 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC0BC31A81E; Wed, 17 Sep 2025 12:24:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-mt8196-gpufreq-v3-6-c4ede4b4399e@collabora.com> References: <20250917-mt8196-gpufreq-v3-0-c4ede4b4399e@collabora.com> In-Reply-To: <20250917-mt8196-gpufreq-v3-0-c4ede4b4399e@collabora.com> To: AngeloGioacchino Del Regno , Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Jassi Brar , Kees Cook , "Gustavo A. R. Silva" , Chia-I Wu , Chen-Yu Tsai Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, linux-hardening@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 As it stands, panthor keeps a cached current frequency value for when it wants to retrieve it. This doesn't work well for when things might switch frequency without panthor's knowledge. Instead, implement the get_cur_freq operation, and expose it through a helper function to the rest of panthor. Reviewed-by: Steven Price Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nicolas Frattaroli --- drivers/gpu/drm/panthor/panthor_devfreq.c | 33 +++++++++++++++++++++++++++= ---- drivers/gpu/drm/panthor/panthor_devfreq.h | 2 ++ drivers/gpu/drm/panthor/panthor_device.h | 3 --- drivers/gpu/drm/panthor/panthor_drv.c | 4 +++- 4 files changed, 34 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/panthor/panthor_devfreq.c b/drivers/gpu/drm/pa= nthor/panthor_devfreq.c index 3686515d368db5bb329f4858d4a7247a4957cc24..8903f60c0a3f06313ac2008791c= 210ff32b6bd52 100644 --- a/drivers/gpu/drm/panthor/panthor_devfreq.c +++ b/drivers/gpu/drm/panthor/panthor_devfreq.c @@ -62,7 +62,6 @@ static void panthor_devfreq_update_utilization(struct pan= thor_devfreq *pdevfreq) static int panthor_devfreq_target(struct device *dev, unsigned long *freq, u32 flags) { - struct panthor_device *ptdev =3D dev_get_drvdata(dev); struct dev_pm_opp *opp; int err; =20 @@ -72,8 +71,6 @@ static int panthor_devfreq_target(struct device *dev, uns= igned long *freq, dev_pm_opp_put(opp); =20 err =3D dev_pm_opp_set_rate(dev, *freq); - if (!err) - ptdev->current_frequency =3D *freq; =20 return err; } @@ -115,11 +112,21 @@ static int panthor_devfreq_get_dev_status(struct devi= ce *dev, return 0; } =20 +static int panthor_devfreq_get_cur_freq(struct device *dev, unsigned long = *freq) +{ + struct panthor_device *ptdev =3D dev_get_drvdata(dev); + + *freq =3D clk_get_rate(ptdev->clks.core); + + return 0; +} + static struct devfreq_dev_profile panthor_devfreq_profile =3D { .timer =3D DEVFREQ_TIMER_DELAYED, .polling_ms =3D 50, /* ~3 frames */ .target =3D panthor_devfreq_target, .get_dev_status =3D panthor_devfreq_get_dev_status, + .get_cur_freq =3D panthor_devfreq_get_cur_freq, }; =20 int panthor_devfreq_init(struct panthor_device *ptdev) @@ -198,7 +205,6 @@ int panthor_devfreq_init(struct panthor_device *ptdev) return PTR_ERR(opp); =20 panthor_devfreq_profile.initial_freq =3D cur_freq; - ptdev->current_frequency =3D cur_freq; =20 /* * Set the recommend OPP this will enable and configure the regulator @@ -296,3 +302,22 @@ void panthor_devfreq_record_idle(struct panthor_device= *ptdev) =20 spin_unlock_irqrestore(&pdevfreq->lock, irqflags); } + +unsigned long panthor_devfreq_get_freq(struct panthor_device *ptdev) +{ + struct panthor_devfreq *pdevfreq =3D ptdev->devfreq; + unsigned long freq =3D 0; + int ret; + + if (!pdevfreq || !pdevfreq->devfreq) + return 0; + + if (pdevfreq->devfreq->profile->get_cur_freq) { + ret =3D pdevfreq->devfreq->profile->get_cur_freq(ptdev->base.dev, + &freq); + if (ret) + return 0; + } + + return freq; +} diff --git a/drivers/gpu/drm/panthor/panthor_devfreq.h b/drivers/gpu/drm/pa= nthor/panthor_devfreq.h index b7631de695f7d79456478c87e8af5dc47673cd1d..f8e29e02f66cb3281ed4bb4c75c= da9bd4df82b92 100644 --- a/drivers/gpu/drm/panthor/panthor_devfreq.h +++ b/drivers/gpu/drm/panthor/panthor_devfreq.h @@ -18,4 +18,6 @@ void panthor_devfreq_suspend(struct panthor_device *ptdev= ); void panthor_devfreq_record_busy(struct panthor_device *ptdev); void panthor_devfreq_record_idle(struct panthor_device *ptdev); =20 +unsigned long panthor_devfreq_get_freq(struct panthor_device *ptdev); + #endif /* __PANTHOR_DEVFREQ_H__ */ diff --git a/drivers/gpu/drm/panthor/panthor_device.h b/drivers/gpu/drm/pan= thor/panthor_device.h index 9f0649ecfc4fc697a21a8b2fc4dd89c8ecf298df..f32c1868bf6d782d99df9dbd0ba= bcea049c917e0 100644 --- a/drivers/gpu/drm/panthor/panthor_device.h +++ b/drivers/gpu/drm/panthor/panthor_device.h @@ -214,9 +214,6 @@ struct panthor_device { /** @profile_mask: User-set profiling flags for job accounting. */ u32 profile_mask; =20 - /** @current_frequency: Device clock frequency at present. Set by DVFS*/ - unsigned long current_frequency; - /** @fast_rate: Maximum device clock frequency. Set by DVFS */ unsigned long fast_rate; =20 diff --git a/drivers/gpu/drm/panthor/panthor_drv.c b/drivers/gpu/drm/pantho= r/panthor_drv.c index ea4a37b566a8b215f2b7a09c333a696f1dcdb58f..4d59d94c353c3ca76f4b98a411c= 8f8284efafd08 100644 --- a/drivers/gpu/drm/panthor/panthor_drv.c +++ b/drivers/gpu/drm/panthor/panthor_drv.c @@ -25,6 +25,7 @@ #include #include =20 +#include "panthor_devfreq.h" #include "panthor_device.h" #include "panthor_fw.h" #include "panthor_gem.h" @@ -1519,7 +1520,8 @@ static void panthor_gpu_show_fdinfo(struct panthor_de= vice *ptdev, drm_printf(p, "drm-cycles-panthor:\t%llu\n", pfile->stats.cycles); =20 drm_printf(p, "drm-maxfreq-panthor:\t%lu Hz\n", ptdev->fast_rate); - drm_printf(p, "drm-curfreq-panthor:\t%lu Hz\n", ptdev->current_frequency); + drm_printf(p, "drm-curfreq-panthor:\t%lu Hz\n", + panthor_devfreq_get_freq(ptdev)); } =20 static void panthor_show_internal_memory_stats(struct drm_printer *p, stru= ct drm_file *file) --=20 2.51.0 From nobody Thu Oct 2 10:55:24 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8712031A81E; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-mt8196-gpufreq-v3-7-c4ede4b4399e@collabora.com> References: <20250917-mt8196-gpufreq-v3-0-c4ede4b4399e@collabora.com> In-Reply-To: <20250917-mt8196-gpufreq-v3-0-c4ede4b4399e@collabora.com> To: AngeloGioacchino Del Regno , Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Jassi Brar , Kees Cook , "Gustavo A. R. Silva" , Chia-I Wu , Chen-Yu Tsai Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, linux-hardening@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 The only device-specific part of panthor's get_dev_status devfreq callback is getting the clock frequency. All the other logic surrounding what it does may be useful for other devfreq implementations however. Make it call into get_cur_freq instead of poking the common clock framework directly. Signed-off-by: Nicolas Frattaroli --- drivers/gpu/drm/panthor/panthor_devfreq.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/panthor/panthor_devfreq.c b/drivers/gpu/drm/pa= nthor/panthor_devfreq.c index 8903f60c0a3f06313ac2008791c210ff32b6bd52..118da7cbb3c809e4aabfef7d209= 14e61c2b62555 100644 --- a/drivers/gpu/drm/panthor/panthor_devfreq.c +++ b/drivers/gpu/drm/panthor/panthor_devfreq.c @@ -87,9 +87,13 @@ static int panthor_devfreq_get_dev_status(struct device = *dev, { struct panthor_device *ptdev =3D dev_get_drvdata(dev); struct panthor_devfreq *pdevfreq =3D ptdev->devfreq; + struct devfreq_dev_profile *p =3D pdevfreq->devfreq->profile; unsigned long irqflags; + int ret; =20 - status->current_frequency =3D clk_get_rate(ptdev->clks.core); + ret =3D p->get_cur_freq(dev, &status->current_frequency); + if (ret) + return ret; =20 spin_lock_irqsave(&pdevfreq->lock, irqflags); =20 --=20 2.51.0 From nobody Thu Oct 2 10:55:24 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B10F4337E9A; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-mt8196-gpufreq-v3-8-c4ede4b4399e@collabora.com> References: <20250917-mt8196-gpufreq-v3-0-c4ede4b4399e@collabora.com> In-Reply-To: <20250917-mt8196-gpufreq-v3-0-c4ede4b4399e@collabora.com> To: AngeloGioacchino Del Regno , Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Jassi Brar , Kees Cook , "Gustavo A. R. Silva" , Chia-I Wu , Chen-Yu Tsai Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, linux-hardening@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 On some devices, devfreq is not controlled directly by DT OPPs and the common clock framework, but through an external devfreq driver. To permit this type of usage, add the concept of devfreq providers. Devfreq providers for panthor register themselves with panthor as a provider. panthor then gets whatever device is pointed at on its performance-domains property, finds the registered devfreq provider for it, and uses its registered devfreq ops. It wraps those operations by passing the provider ops the provider's struct device, as opposed to the panthor device. Providers can choose to omit overloading some operations. In that case, panthor's own implementation is used. The only exception is the exit operation, which panthor does not use, and the wrapper only gets registered if a provider needs it. Should the probe order work out such that panthor probes before the devfreq provider is finished probing and registering itself, then we just defer the probe after adding a device link. Signed-off-by: Nicolas Frattaroli --- drivers/gpu/drm/panthor/panthor_devfreq.c | 190 ++++++++++++++++++++++++++= ---- drivers/gpu/drm/panthor/panthor_devfreq.h | 47 ++++++++ 2 files changed, 212 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/panthor/panthor_devfreq.c b/drivers/gpu/drm/pa= nthor/panthor_devfreq.c index 118da7cbb3c809e4aabfef7d20914e61c2b62555..1f10724e2f08df09b52fa1a27ff= e9cfd49994b09 100644 --- a/drivers/gpu/drm/panthor/panthor_devfreq.c +++ b/drivers/gpu/drm/panthor/panthor_devfreq.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include =20 @@ -34,6 +35,12 @@ struct panthor_devfreq { /** @last_busy_state: True if the GPU was busy last time we updated the s= tate. */ bool last_busy_state; =20 + /** + * @panthor_devfreq_provider: the used performance-domain controller + * through which devfreq callbacks are passed onto, or NULL if none. + */ + struct panthor_devfreq_provider *provider; + /** * @lock: Lock used to protect busy_time, idle_time, time_last_update and * last_busy_state. @@ -44,6 +51,19 @@ struct panthor_devfreq { spinlock_t lock; }; =20 +static LIST_HEAD(panthor_devfreq_providers); +static DEFINE_MUTEX(panthor_devfreq_providers_lock); + +int panthor_devfreq_register_provider(struct panthor_devfreq_provider *pro= v) +{ + guard(mutex)(&panthor_devfreq_providers_lock); + + list_add(&prov->node, &panthor_devfreq_providers); + + return 0; +} +EXPORT_SYMBOL(panthor_devfreq_register_provider); + static void panthor_devfreq_update_utilization(struct panthor_devfreq *pde= vfreq) { ktime_t now, last; @@ -59,12 +79,26 @@ static void panthor_devfreq_update_utilization(struct p= anthor_devfreq *pdevfreq) pdevfreq->time_last_update =3D now; } =20 +static void panthor_devfreq_exit(struct device *dev) +{ + struct panthor_device *ptdev =3D dev_get_drvdata(dev); + struct panthor_devfreq_provider *provider =3D ptdev->devfreq->provider; + + if (provider && provider->exit) + provider->exit(provider->dev); +} + static int panthor_devfreq_target(struct device *dev, unsigned long *freq, u32 flags) { + struct panthor_device *ptdev =3D dev_get_drvdata(dev); + struct panthor_devfreq_provider *provider =3D ptdev->devfreq->provider; struct dev_pm_opp *opp; int err; =20 + if (provider && provider->target) + return provider->target(provider->dev, freq, flags); + opp =3D devfreq_recommended_opp(dev, freq, flags); if (IS_ERR(opp)) return PTR_ERR(opp); @@ -87,6 +121,7 @@ static int panthor_devfreq_get_dev_status(struct device = *dev, { struct panthor_device *ptdev =3D dev_get_drvdata(dev); struct panthor_devfreq *pdevfreq =3D ptdev->devfreq; + struct panthor_devfreq_provider *provider =3D pdevfreq->provider; struct devfreq_dev_profile *p =3D pdevfreq->devfreq->profile; unsigned long irqflags; int ret; @@ -97,32 +132,42 @@ static int panthor_devfreq_get_dev_status(struct devic= e *dev, =20 spin_lock_irqsave(&pdevfreq->lock, irqflags); =20 - panthor_devfreq_update_utilization(pdevfreq); + if (provider && provider->get_dev_status) { + ret =3D provider->get_dev_status(provider->dev, status); + } else { + panthor_devfreq_update_utilization(pdevfreq); =20 - status->total_time =3D ktime_to_ns(ktime_add(pdevfreq->busy_time, - pdevfreq->idle_time)); + status->total_time =3D ktime_to_ns(ktime_add(pdevfreq->busy_time, + pdevfreq->idle_time)); =20 - status->busy_time =3D ktime_to_ns(pdevfreq->busy_time); + status->busy_time =3D ktime_to_ns(pdevfreq->busy_time); =20 - panthor_devfreq_reset(pdevfreq); + panthor_devfreq_reset(pdevfreq); + } =20 spin_unlock_irqrestore(&pdevfreq->lock, irqflags); =20 - drm_dbg(&ptdev->base, "busy %lu total %lu %lu %% freq %lu MHz\n", - status->busy_time, status->total_time, - status->busy_time / (status->total_time / 100), - status->current_frequency / 1000 / 1000); + if (!ret) + drm_dbg(&ptdev->base, "busy %lu total %lu %lu %% freq %lu MHz\n", + status->busy_time, status->total_time, + status->busy_time / (status->total_time / 100), + status->current_frequency / 1000 / 1000); =20 - return 0; + return ret; } =20 static int panthor_devfreq_get_cur_freq(struct device *dev, unsigned long = *freq) { struct panthor_device *ptdev =3D dev_get_drvdata(dev); + struct panthor_devfreq_provider *provider =3D ptdev->devfreq->provider; + int ret =3D 0; =20 - *freq =3D clk_get_rate(ptdev->clks.core); + if (provider && provider->get_cur_freq) + ret =3D provider->get_cur_freq(provider->dev, freq); + else + *freq =3D clk_get_rate(ptdev->clks.core); =20 - return 0; + return ret; } =20 static struct devfreq_dev_profile panthor_devfreq_profile =3D { @@ -133,7 +178,51 @@ static struct devfreq_dev_profile panthor_devfreq_prof= ile =3D { .get_cur_freq =3D panthor_devfreq_get_cur_freq, }; =20 -int panthor_devfreq_init(struct panthor_device *ptdev) +static int panthor_devfreq_use_provider(struct panthor_device *ptdev, + struct panthor_devfreq_provider *provider) +{ + struct devfreq_dev_profile *p =3D &panthor_devfreq_profile; + struct device *dev =3D ptdev->base.dev; + unsigned int i; + int ret =3D 0; + + ptdev->devfreq->provider =3D provider; + + if (provider->exit) + p->exit =3D panthor_devfreq_exit; + + for (i =3D 0; i < provider->num_opps; i++) { + ret =3D dev_pm_opp_add_dynamic(dev, provider->opp_table[i]); + if (ret) { + DRM_DEV_ERROR(dev, "Couldn't add OPP %u: %pe\n", i, ERR_PTR(ret)); + return ret; + } + } + + p->max_state =3D provider->num_opps; + + if (provider->num_opps) + ptdev->fast_rate =3D provider->opp_table[provider->num_opps - 1]->freq; + + return ret; +} + +static int panthor_devfreq_init_provider(struct panthor_device *ptdev, + struct device *provider_dev) +{ + struct panthor_devfreq_provider *prov; + + guard(mutex)(&panthor_devfreq_providers_lock); + + list_for_each_entry(prov, &panthor_devfreq_providers, node) { + if (prov->dev =3D=3D provider_dev) + return panthor_devfreq_use_provider(ptdev, prov); + } + + return -EPROBE_DEFER; +} + +static int panthor_devfreq_init_of(struct panthor_device *ptdev) { /* There's actually 2 regulators (mali and sram), but the OPP core only * supports one. @@ -142,20 +231,12 @@ int panthor_devfreq_init(struct panthor_device *ptdev) * the coupling logic deal with voltage updates. */ static const char * const reg_names[] =3D { "mali", NULL }; - struct thermal_cooling_device *cooling; struct device *dev =3D ptdev->base.dev; - struct panthor_devfreq *pdevfreq; struct dev_pm_opp *opp; unsigned long cur_freq; unsigned long freq =3D ULONG_MAX; int ret; =20 - pdevfreq =3D drmm_kzalloc(&ptdev->base, sizeof(*ptdev->devfreq), GFP_KERN= EL); - if (!pdevfreq) - return -ENOMEM; - - ptdev->devfreq =3D pdevfreq; - ret =3D devm_pm_opp_set_regulators(dev, reg_names); if (ret) { if (ret !=3D -EPROBE_DEFER) @@ -168,10 +249,6 @@ int panthor_devfreq_init(struct panthor_device *ptdev) if (ret) return ret; =20 - spin_lock_init(&pdevfreq->lock); - - panthor_devfreq_reset(pdevfreq); - cur_freq =3D clk_get_rate(ptdev->clks.core); =20 /* Regulator coupling only takes care of synchronizing/balancing voltage @@ -229,6 +306,61 @@ int panthor_devfreq_init(struct panthor_device *ptdev) =20 dev_pm_opp_put(opp); =20 + return 0; +} + +static int panthor_devfreq_init_platform(struct panthor_device *ptdev) +{ + struct device_node *pcnode; + struct platform_device *pdev; + struct device_link *link; + int ret; + + pcnode =3D of_parse_phandle(ptdev->base.dev->of_node, + "performance-domains", 0); + if (!pcnode) + return -EINVAL; + + pdev =3D of_find_device_by_node(pcnode); + of_node_put(pcnode); + if (!pdev) + return -ENODEV; + + link =3D device_link_add(ptdev->base.dev, &pdev->dev, + DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); + if (!link) { + dev_err(ptdev->base.dev, "failed to add device link\n"); + return -ENODEV; + } + + ret =3D panthor_devfreq_init_provider(ptdev, &pdev->dev); + if (ret) + return dev_err_probe(ptdev->base.dev, ret, + "failed to initialize devfreq provider\n"); + + DRM_DEV_INFO(ptdev->base.dev, "initialized devfreq provider %s\n", + dev_name(&pdev->dev)); + + return 0; +} + +int panthor_devfreq_init(struct panthor_device *ptdev) +{ + struct thermal_cooling_device *cooling; + struct device *dev =3D ptdev->base.dev; + struct panthor_devfreq *pdevfreq; + int ret; + + pdevfreq =3D drmm_kzalloc(&ptdev->base, sizeof(*ptdev->devfreq), GFP_KERN= EL); + if (!pdevfreq) + return -ENOMEM; + + ptdev->devfreq =3D pdevfreq; + + spin_lock_init(&pdevfreq->lock); + + panthor_devfreq_reset(pdevfreq); + /* * Setup default thresholds for the simple_ondemand governor. * The values are chosen based on experiments. @@ -236,6 +368,14 @@ int panthor_devfreq_init(struct panthor_device *ptdev) pdevfreq->gov_data.upthreshold =3D 45; pdevfreq->gov_data.downdifferential =3D 5; =20 + if (!of_property_present(dev->of_node, "performance-domains")) + ret =3D panthor_devfreq_init_of(ptdev); + else + ret =3D panthor_devfreq_init_platform(ptdev); + + if (ret) + return ret; + pdevfreq->devfreq =3D devm_devfreq_add_device(dev, &panthor_devfreq_profi= le, DEVFREQ_GOV_SIMPLE_ONDEMAND, &pdevfreq->gov_data); diff --git a/drivers/gpu/drm/panthor/panthor_devfreq.h b/drivers/gpu/drm/pa= nthor/panthor_devfreq.h index f8e29e02f66cb3281ed4bb4c75cda9bd4df82b92..777045d406242f46dea376bccb9= 99bfc11f92a7a 100644 --- a/drivers/gpu/drm/panthor/panthor_devfreq.h +++ b/drivers/gpu/drm/panthor/panthor_devfreq.h @@ -10,6 +10,51 @@ struct thermal_cooling_device; struct panthor_device; struct panthor_devfreq; =20 +struct panthor_devfreq_provider { + /** @dev: device pointer to the provider device */ + struct device *dev; + + /** + * @opp_table: table of unique OPPs, sorted from lowest frequency to + * highest. + */ + struct dev_pm_opp_data **opp_table; + + /** @num_opps: number of entries in @opp_table. */ + unsigned int num_opps; + + /** + * @target: &struct devfreq_dev_profile "target" callback to wrap, + * optional. Falls back to panthor internal implementation if absent. + * Passes @dev as the first parameter, not panthor's device. + */ + int (*target)(struct device *dev, unsigned long *freq, u32 flags); + + /** + * @get_dev_status: &struct devfreq_dev_profile "get_dev_status" callback + * to wrap, optional. Falls back to panthor internal implementation if + * absent. Passes @dev as the first parameter, not panthor's device. + */ + int (*get_dev_status)(struct device *dev, + struct devfreq_dev_status *stat); + + /** + * @get_cur_freq: &struct devfreq_dev_profile "get_dev_status" callback + * to wrap, optional. Falls back to panthor internal implementation if + * absent. Passes @dev as the first parameter, not panthor's device. + */ + int (*get_cur_freq)(struct device *dev, unsigned long *freq); + + /** + * @exit: &struct devfreq_dev_profile "exit" callback to wrap, optional. + * Falls back to not registering one an exit function at all if absent. + * Passes @dev as the first parameter, not panthor's device. + */ + void (*exit)(struct device *dev); + + struct list_head node; +}; + int panthor_devfreq_init(struct panthor_device *ptdev); =20 void panthor_devfreq_resume(struct panthor_device *ptdev); @@ -20,4 +65,6 @@ void panthor_devfreq_record_idle(struct panthor_device *p= tdev); =20 unsigned long panthor_devfreq_get_freq(struct panthor_device *ptdev); =20 +int panthor_devfreq_register_provider(struct panthor_devfreq_provider *pro= v); + #endif /* __PANTHOR_DEVFREQ_H__ */ --=20 2.51.0 From nobody Thu Oct 2 10:55:24 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E5070328973; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-mt8196-gpufreq-v3-9-c4ede4b4399e@collabora.com> References: <20250917-mt8196-gpufreq-v3-0-c4ede4b4399e@collabora.com> In-Reply-To: <20250917-mt8196-gpufreq-v3-0-c4ede4b4399e@collabora.com> To: AngeloGioacchino Del Regno , Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Jassi Brar , Kees Cook , "Gustavo A. R. Silva" , Chia-I Wu , Chen-Yu Tsai Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, linux-hardening@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 While panthor does not try to do anything untoward with the core clock outside of increasing its enable/disable count, the spirit of using DT to describe hardware, not what drivers need, informs us that on the MT8196, panthor should work without one, as the true owner of the clocks in this case is the performance-domain. Add a boolean to the soc_data struct that tells panthor whether on any given SoC, it can leave even the core clock NULL. Set it to true for the MT8196 soc_data instance. Signed-off-by: Nicolas Frattaroli Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/panthor/panthor_device.c | 3 +++ drivers/gpu/drm/panthor/panthor_device.h | 3 +++ drivers/gpu/drm/panthor/panthor_drv.c | 1 + 3 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/panthor/panthor_device.c b/drivers/gpu/drm/pan= thor/panthor_device.c index c7033d82cef55c940adc8434231cac6c5a20c288..581901a8e64fdb0946f20af5934= 89fefde1cc05f 100644 --- a/drivers/gpu/drm/panthor/panthor_device.c +++ b/drivers/gpu/drm/panthor/panthor_device.c @@ -43,6 +43,9 @@ static int panthor_gpu_coherency_init(struct panthor_devi= ce *ptdev) =20 static int panthor_clk_init(struct panthor_device *ptdev) { + if (ptdev->soc_data && ptdev->soc_data->no_clocks) + return 0; + ptdev->clks.core =3D devm_clk_get(ptdev->base.dev, NULL); if (IS_ERR(ptdev->clks.core)) return dev_err_probe(ptdev->base.dev, diff --git a/drivers/gpu/drm/panthor/panthor_device.h b/drivers/gpu/drm/pan= thor/panthor_device.h index f32c1868bf6d782d99df9dbd0babcea049c917e0..cc8485afdaf865edc89a36823ba= 75c588a040e0b 100644 --- a/drivers/gpu/drm/panthor/panthor_device.h +++ b/drivers/gpu/drm/panthor/panthor_device.h @@ -40,6 +40,9 @@ struct panthor_soc_data { =20 /** @asn_hash: ASN_HASH values when asn_hash_enable is true. */ u32 asn_hash[3]; + + /** @no_clocks: True if clock control is external, not by panthor. */ + bool no_clocks; }; =20 /** diff --git a/drivers/gpu/drm/panthor/panthor_drv.c b/drivers/gpu/drm/pantho= r/panthor_drv.c index 4d59d94c353c3ca76f4b98a411c8f8284efafd08..3583ec955a85fe6e383839ec2bd= e017e1c6a995c 100644 --- a/drivers/gpu/drm/panthor/panthor_drv.c +++ b/drivers/gpu/drm/panthor/panthor_drv.c @@ -1687,6 +1687,7 @@ ATTRIBUTE_GROUPS(panthor); static const struct panthor_soc_data soc_data_mediatek_mt8196 =3D { .asn_hash_enable =3D true, .asn_hash =3D { 0xb, 0xe, 0x0, }, + .no_clocks =3D true, }; =20 static const struct of_device_id dt_match[] =3D { --=20 2.51.0 From nobody Thu Oct 2 10:55:24 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E296C333163; Wed, 17 Sep 2025 12:24:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1758111850; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=gjnpJe7OvNQx8BVFibgbqd6R/nPyOkeSAAUQxJENU28=; b=CugyvuxuKr3liHU26ij5S5ZigHC671Xpz/93aDxDgcPoJg+h9vrZER+eeSvnyZ2e /+eeo3wyIb3tYdwFZnXjzHFY7+7SHvLB+nUpHd/kQpakRTMRkFDk13ECbg5DnDYRqE2 2sQcLSee+EBWlW5WZ9tIPfhV0gqo0J9YIK07gDIU= Received: by mx.zohomail.com with SMTPS id 1758111847514772.0305687016033; Wed, 17 Sep 2025 05:24:07 -0700 (PDT) From: Nicolas Frattaroli Date: Wed, 17 Sep 2025 14:22:41 +0200 Subject: [PATCH v3 10/10] drm/panthor: add support for MediaTek MFlexGraphics Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250917-mt8196-gpufreq-v3-10-c4ede4b4399e@collabora.com> References: <20250917-mt8196-gpufreq-v3-0-c4ede4b4399e@collabora.com> In-Reply-To: <20250917-mt8196-gpufreq-v3-0-c4ede4b4399e@collabora.com> To: AngeloGioacchino Del Regno , Boris Brezillon , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Jassi Brar , Kees Cook , "Gustavo A. R. Silva" , Chia-I Wu , Chen-Yu Tsai Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, linux-hardening@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 MediaTek uses some glue logic to control frequency and power on some of their GPUs. This is best exposed as a devfreq driver, as it saves us from having to hardcode OPPs into the device tree, and can be extended with additional devfreq-y logic like more clever governors that use the hardware's GPUEB MCU to set frame time targets and power limits. Add this driver to the panthor subdirectory. It needs to live here as it needs to call into panthor's devfreq layer to register itself as a provider. Signed-off-by: Nicolas Frattaroli --- drivers/gpu/drm/panthor/Kconfig | 13 + drivers/gpu/drm/panthor/Makefile | 2 + drivers/gpu/drm/panthor/mediatek_mfg.c | 946 +++++++++++++++++++++++++++++= ++++ 3 files changed, 961 insertions(+) diff --git a/drivers/gpu/drm/panthor/Kconfig b/drivers/gpu/drm/panthor/Kcon= fig index 55b40ad07f3b0779e0c434469ddc874ff74fde27..c4d2599c05df9e0e009b8e99b3d= 29c220269ca0d 100644 --- a/drivers/gpu/drm/panthor/Kconfig +++ b/drivers/gpu/drm/panthor/Kconfig @@ -21,3 +21,16 @@ config DRM_PANTHOR =20 Note that the Mali-G68 and Mali-G78, while Valhall architecture, will be supported with the panfrost driver as they are not CSF GPUs. + +config DRM_PANTHOR_MEDIATEK_MFG + tristate "MediaTek MFlexGraphics Extensions for Panthor" + depends on (DRM_PANTHOR && ARCH_MEDIATEK) || COMPILE_TEST + select DEVFREQ_GOV_SIMPLE_ONDEMAND + select PM_DEVFREQ + select MTK_GPUEB_MBOX + help + Support for power and clock control in Panthor for MediaTek + MFlexGraphics devices, such as the GPU on the MT8196 or MT6991 SoCs. + + These extensions are required for the GPU to work on these platforms, + as they control the glue logic that powers on the GPU. diff --git a/drivers/gpu/drm/panthor/Makefile b/drivers/gpu/drm/panthor/Mak= efile index 02db21748c125688d2ef20ed254b5ebd7ff642e4..e0ebfdfb20bd78e0003c860c86c= 040746248fb89 100644 --- a/drivers/gpu/drm/panthor/Makefile +++ b/drivers/gpu/drm/panthor/Makefile @@ -12,4 +12,6 @@ panthor-y :=3D \ panthor_mmu.o \ panthor_sched.o =20 +obj-$(CONFIG_DRM_PANTHOR_MEDIATEK_MFG) +=3D mediatek_mfg.o + obj-$(CONFIG_DRM_PANTHOR) +=3D panthor.o diff --git a/drivers/gpu/drm/panthor/mediatek_mfg.c b/drivers/gpu/drm/panth= or/mediatek_mfg.c new file mode 100644 index 0000000000000000000000000000000000000000..1b3220d721e91334522b4e158ac= 3e262dea19d49 --- /dev/null +++ b/drivers/gpu/drm/panthor/mediatek_mfg.c @@ -0,0 +1,946 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Driver for MediaTek MFlexGraphics Devices + * + * Copyright (C) 2025, Collabora Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "panthor_devfreq.h" + +#define GPR_LP_STATE 0x0028 +#define EB_ON_SUSPEND 0x0 +#define EB_ON_RESUME 0x1 +#define GPR_IPI_MAGIC 0x34 + +#define RPC_PWR_CON 0x0504 +#define PWR_ACK_M GENMASK(31, 30) +#define RPC_DUMMY_REG_2 0x0658 +#define RPC_GHPM_CFG0_CON 0x0800 +#define GHPM_ENABLE_M BIT(0) +#define GHPM_ON_SEQ_M BIT(2) +#define RPC_GHPM_RO0_CON 0x09A4 +#define GHPM_STATE_M GENMASK(7, 0) +#define GHPM_PWR_STATE_M BIT(16) + +#define GF_REG_MAGIC 0x0000 +#define GF_REG_GPU_OPP_IDX 0x0004 +#define GF_REG_STK_OPP_IDX 0x0008 +#define GF_REG_GPU_OPP_NUM 0x000c +#define GF_REG_STK_OPP_NUM 0x0010 +#define GF_REG_GPU_OPP_SNUM 0x0014 +#define GF_REG_STK_OPP_SNUM 0x0018 +#define GF_REG_POWER_COUNT 0x001c +#define GF_REG_BUCK_COUNT 0x0020 +#define GF_REG_MTCMOS_COUNT 0x0024 +#define GF_REG_CG_COUNT 0x0028 /* CG =3D Clock Gate? */ +#define GF_REG_ACTIVE_COUNT 0x002C +#define GF_REG_TEMP_RAW 0x0030 +#define GF_REG_TEMP_NORM_GPU 0x0034 +#define GF_REG_TEMP_HIGH_GPU 0x0038 +#define GF_REG_TEMP_NORM_STK 0x003C +#define GF_REG_TEMP_HIGH_STK 0x0040 +#define GF_REG_FREQ_CUR_GPU 0x0044 +#define GF_REG_FREQ_CUR_STK 0x0048 +#define GF_REG_FREQ_OUT_GPU 0x004C /* Guess: actual achieved freq */ +#define GF_REG_FREQ_OUT_STK 0x0050 /* Guess: actual achieved freq */ +#define GF_REG_FREQ_METER_GPU 0x0054 /* Seems unused, always 0 */ +#define GF_REG_FREQ_METER_STK 0x0058 /* Seems unused, always 0 */ +#define GF_REG_VOLT_CUR_GPU 0x005C /* in tens of microvolts */ +#define GF_REG_VOLT_CUR_STK 0x0060 /* in tens of microvolts */ +#define GF_REG_VOLT_CUR_GPU_SRAM 0x0064 +#define GF_REG_VOLT_CUR_STK_SRAM 0x0068 +#define GF_REG_VOLT_CUR_GPU_REG 0x006C /* Seems unused, always 0 */ +#define GF_REG_VOLT_CUR_STK_REG 0x0070 /* Seems unused, always 0 */ +#define GF_REG_VOLT_CUR_GPU_REG_SRAM 0x0074 +#define GF_REG_VOLT_CUR_STK_REG_SRAM 0x0078 +#define GF_REG_PWR_CUR_GPU 0x007C /* in milliwatts */ +#define GF_REG_PWR_CUR_STK 0x0080 /* in milliwatts */ +#define GF_REG_PWR_MAX_GPU 0x0084 /* in milliwatts */ +#define GF_REG_PWR_MAX_STK 0x0088 /* in milliwatts */ +#define GF_REG_PWR_MIN_GPU 0x008C /* in milliwatts */ +#define GF_REG_PWR_MIN_STK 0x0090 /* in milliwatts */ +#define GF_REG_LEAKAGE_RT_GPU 0x0094 /* Unknown */ +#define GF_REG_LEAKAGE_RT_STK 0x0098 /* Unknown */ +#define GF_REG_LEAKAGE_RT_SRAM 0x009C /* Unknown */ +#define GF_REG_LEAKAGE_HT_GPU 0x00A0 /* Unknown */ +#define GF_REG_LEAKAGE_HT_STK 0x00A4 /* Unknown */ +#define GF_REG_LEAKAGE_HT_SRAM 0x00A8 /* Unknown */ +#define GF_REG_VOLT_DAC_LOW_GPU 0x00AC /* Seems unused, always 0 */ +#define GF_REG_VOLT_DAC_LOW_STK 0x00B0 /* Seems unused, always 0 */ +#define GF_REG_OPP_CUR_CEIL 0x00B4 +#define GF_REG_OPP_CUR_FLOOR 0x00B8 +#define GF_REG_OPP_CUR_LIMITER_CEIL 0x00BC +#define GF_REG_OPP_CUR_LIMITER_FLOOR 0x00C0 +#define GF_REG_OPP_PRIORITY_CEIL 0x00C4 +#define GF_REG_OPP_PRIORITY_FLOOR 0x00C8 +#define GF_REG_PWR_CTL 0x00CC +#define GF_REG_ACTIVE_SLEEP_CTL 0x00D0 +#define GF_REG_DVFS_STATE 0x00D4 +#define GF_REG_SHADER_PRESENT 0x00D8 +#define GF_REG_ASENSOR_ENABLE 0x00DC +#define GF_REG_AGING_LOAD 0x00E0 +#define GF_REG_AGING_MARGIN 0x00E4 +#define GF_REG_AVS_ENABLE 0x00E8 +#define GF_REG_AVS_MARGIN 0x00EC +#define GF_REG_CHIP_TYPE 0x00F0 +#define GF_REG_SB_VERSION 0x00F4 +#define GF_REG_PTP_VERSION 0x00F8 +#define GF_REG_DBG_VERSION 0x00FC +#define GF_REG_KDBG_VERSION 0x0100 +#define GF_REG_GPM1_MODE 0x0104 +#define GF_REG_GPM3_MODE 0x0108 +#define GF_REG_DFD_MODE 0x010C +#define GF_REG_DUAL_BUCK 0x0110 +#define GF_REG_SEGMENT_ID 0x0114 +#define GF_REG_POWER_TIME_H 0x0118 +#define GF_REG_POWER_TIME_L 0x011C +#define GF_REG_PWR_STATUS 0x0120 +#define GF_REG_STRESS_TEST 0x0124 +#define GF_REG_TEST_MODE 0x0128 +#define GF_REG_IPS_MODE 0x012C +#define GF_REG_TEMP_COMP_MODE 0x0130 +#define GF_REG_HT_TEMP_COMP_MODE 0x0134 +#define GF_REG_PWR_TRACKER_MODE 0x0138 +#define GF_REG_OPP_TABLE_GPU 0x0314 +#define GF_REG_OPP_TABLE_STK 0x09A4 +#define GF_REG_OPP_TABLE_GPU_S 0x1034 +#define GF_REG_OPP_TABLE_STK_S 0x16c4 +#define GF_REG_LIMIT_TABLE 0x1d54 +#define GF_REG_GPM3_TABLE 0x223C + +#define MFG_MT8196_E2_ID 0x101 +#define GPUEB_SLEEP_MAGIC 0x55667788UL +#define GPUEB_SRAM_MAGIC 0xBABADADAUL + +#define GPUEB_TIMEOUT_US 10000UL +#define GPUEB_POLL_US 50 + +#define MAX_OPP_NUM 70 + +#define MBOX_MAX_RX_SIZE 32 /* in bytes */ + +/* + * This enum is part of the ABI of the GPUEB firmware. Don't change the + * numbering, as you would wreak havoc. + */ +enum mtk_mfg_ipi_cmd { + CMD_INIT_SHARED_MEM =3D 0, + CMD_GET_FREQ_BY_IDX =3D 1, + CMD_GET_POWER_BY_IDX =3D 2, + CMD_GET_OPPIDX_BY_FREQ =3D 3, + CMD_GET_LEAKAGE_POWER =3D 4, + CMD_SET_LIMIT =3D 5, + CMD_POWER_CONTROL =3D 6, + CMD_ACTIVE_SLEEP_CONTROL =3D 7, + CMD_COMMIT =3D 8, + CMD_DUAL_COMMIT =3D 9, + CMD_PDCA_CONFIG =3D 10, + CMD_UPDATE_DEBUG_OPP_INFO =3D 11, + CMD_SWITCH_LIMIT =3D 12, + CMD_FIX_TARGET_OPPIDX =3D 13, + CMD_FIX_DUAL_TARGET_OPPIDX =3D 14, + CMD_FIX_CUSTOM_FREQ_VOLT =3D 15, + CMD_FIX_DUAL_CUSTOM_FREQ_VOLT =3D 16, + CMD_SET_MFGSYS_CONFIG =3D 17, + CMD_MSSV_COMMIT =3D 18, + CMD_NUM =3D 19, +}; + +/* + * This struct is part of the ABI of the GPUEB firmware. Changing it, or + * reordering fields in it, will break things, so don't do it. Thank you. + */ +struct __packed mtk_mfg_ipi_msg { + __le32 magic; + __le32 cmd; + __le32 target; + /* + * Downstream relies on the compiler to implicitly add the following + * padding, as it declares the struct as non-packed. + */ + __le32 reserved; + union { + s32 __bitwise oppidx; + s32 __bitwise return_value; + __le32 freq; + __le32 volt; + __le32 power; + __le32 power_state; + __le32 mode; + __le32 value; + struct { + __le64 base; + __le32 size; + } shared_mem; + struct { + __le32 freq; + __le32 volt; + } custom; + struct { + __le32 limiter; + s32 __bitwise ceiling_info; + s32 __bitwise floor_info; + } set_limit; + struct { + __le32 target; + __le32 val; + } mfg_cfg; + struct { + __le32 target; + __le32 val; + } mssv; + struct { + s32 __bitwise gpu_oppidx; + s32 __bitwise stack_oppidx; + } dual_commit; + struct { + __le32 fgpu; + __le32 vgpu; + __le32 fstack; + __le32 vstack; + } dual_custom; + } u; +}; + +struct __packed mtk_mfg_ipi_sleep_msg { + __le32 event; + __le32 state; + __le32 magic; +}; + +/** + * struct mtk_mfg_opp_entry - OPP table entry from firmware + * @freq_khz: The operating point's frequency in kilohertz + * @voltage_core: The operating point's core voltage in tens of microvolts + * @voltage_sram: The operating point's SRAM voltage in tens of microvolts + * @posdiv: exponent of base 2 for PLL frequency divisor used for this OPP + * @voltage_margin: Number of tens of microvolts the voltage can be unders= hot + * @power_mw: estimate of power usage at this operating point, in milliwat= ts + * + * This struct is part of the ABI with the EB firmware. Do not change it. + */ +struct __packed mtk_mfg_opp_entry { + __le32 freq_khz; + __le32 voltage_core; + __le32 voltage_sram; + __le32 posdiv; + __le32 voltage_margin; + __le32 power_mw; +}; + +struct mtk_mfg_mbox { + struct mbox_client cl; + struct completion rx_done; + struct mtk_mfg *mfg; + struct mbox_chan *ch; + void *rx_data; +}; + +struct mtk_mfg { + struct platform_device *pdev; + struct clk *clk_eb; + struct clk_bulk_data *gpu_clks; + struct regulator_bulk_data *gpu_regs; + void __iomem *rpc; + void __iomem *gpr; + void __iomem *sram; + phys_addr_t sram_phys; + unsigned int sram_size; + unsigned int ghpm_en_reg; + u32 ipi_magic; + unsigned int num_opps; + unsigned int num_unique_gpu_opps; + struct dev_pm_opp_data *gpu_opps; + struct dev_pm_opp_data *stack_opps; + struct mtk_mfg_mbox *gf_mbox; + struct mtk_mfg_mbox *slp_mbox; + int last_opp; + const struct mtk_mfg_variant *variant; +}; + +struct mtk_mfg_variant { + const char *const *clk_names; + unsigned int num_clks; + const char *const *regulator_names; + unsigned int num_regulators; + int (*init)(struct mtk_mfg *mfg); +}; + +static inline void mtk_mfg_update_reg_bits(void __iomem *addr, u32 mask, u= 32 val) +{ + writel((readl(addr) & ~mask) | (val & mask), addr); +} + +static inline unsigned long mtk_mfg_read_gpu_freq(struct mtk_mfg *mfg) +{ + return readl(mfg->sram + GF_REG_FREQ_CUR_GPU) * 1000UL; +} + +static int mtk_mfg_eb_on(struct mtk_mfg *mfg) +{ + struct device *dev =3D &mfg->pdev->dev; + u32 val; + int ret; + + /* + * If MFG is already on from e.g. the bootloader, we should skip doing + * the power-on sequence, as it wouldn't work without powering it off + * first. + */ + if ((readl(mfg->rpc + RPC_PWR_CON) & PWR_ACK_M) =3D=3D PWR_ACK_M) + return 0; + + ret =3D readl_poll_timeout(mfg->rpc + RPC_GHPM_RO0_CON, val, + !(val & (GHPM_PWR_STATE_M | GHPM_STATE_M)), + GPUEB_POLL_US, GPUEB_TIMEOUT_US); + if (ret) { + dev_err(dev, "timed out waiting for EB to power on\n"); + return ret; + } + + mtk_mfg_update_reg_bits(mfg->rpc + mfg->ghpm_en_reg, GHPM_ENABLE_M, + GHPM_ENABLE_M); + + mtk_mfg_update_reg_bits(mfg->rpc + RPC_GHPM_CFG0_CON, GHPM_ON_SEQ_M, 0); + mtk_mfg_update_reg_bits(mfg->rpc + RPC_GHPM_CFG0_CON, GHPM_ON_SEQ_M, + GHPM_ON_SEQ_M); + + mtk_mfg_update_reg_bits(mfg->rpc + mfg->ghpm_en_reg, GHPM_ENABLE_M, 0); + + + ret =3D readl_poll_timeout(mfg->rpc + RPC_PWR_CON, val, + (val & PWR_ACK_M) =3D=3D PWR_ACK_M, + GPUEB_POLL_US, GPUEB_TIMEOUT_US); + if (ret) { + dev_err(dev, "timed out waiting for EB power ack, val =3D 0x%X\n", + val); + return ret; + } + + ret =3D readl_poll_timeout(mfg->gpr + GPR_LP_STATE, val, + (val =3D=3D EB_ON_RESUME), + GPUEB_POLL_US, GPUEB_TIMEOUT_US); + if (ret) { + dev_err(dev, "timed out waiting for EB to resume, status =3D 0x%X\n", va= l); + return ret; + } + + return 0; +} + +static int mtk_mfg_eb_off(struct mtk_mfg *mfg) +{ + struct device *dev =3D &mfg->pdev->dev; + struct mtk_mfg_ipi_sleep_msg msg =3D { + .event =3D 0, + .state =3D 0, + .magic =3D GPUEB_SLEEP_MAGIC + }; + u32 val; + int ret; + + ret =3D mbox_send_message(mfg->slp_mbox->ch, &msg); + if (ret < 0) { + dev_err(dev, "Cannot send sleep command: %pe\n", ERR_PTR(ret)); + return ret; + } + + ret =3D readl_poll_timeout(mfg->rpc + RPC_PWR_CON, val, + !(val & PWR_ACK_M), GPUEB_POLL_US, + GPUEB_TIMEOUT_US); + + if (ret) + dev_err(dev, "timed out waiting for EB to power off, val=3D0x%08X\n", + val); + + return ret; +} + +static int mtk_mfg_send_ipi(struct mtk_mfg *mfg, struct mtk_mfg_ipi_msg *m= sg) +{ + struct device *dev =3D &mfg->pdev->dev; + int ret; + + msg->magic =3D mfg->ipi_magic; + + ret =3D mbox_send_message(mfg->gf_mbox->ch, msg); + if (ret < 0) { + dev_err(dev, "Cannot send GPUFreq IPI command: %pe\n", ERR_PTR(ret)); + return ret; + } + + wait_for_completion(&mfg->gf_mbox->rx_done); + + msg =3D mfg->gf_mbox->rx_data; + + if (msg->u.return_value < 0) { + dev_err(dev, "IPI return: %d\n", msg->u.return_value); + return -EPROTO; + } + + return 0; +} + +static int mtk_mfg_init_shared_mem(struct mtk_mfg *mfg) +{ + struct device *dev =3D &mfg->pdev->dev; + struct mtk_mfg_ipi_msg msg =3D {}; + int ret; + + dev_dbg(dev, "clearing GPUEB sram, 0x%X bytes\n", mfg->sram_size); + memset_io(mfg->sram, 0, mfg->sram_size); + + msg.cmd =3D CMD_INIT_SHARED_MEM; + msg.u.shared_mem.base =3D mfg->sram_phys; + msg.u.shared_mem.size =3D mfg->sram_size; + + ret =3D mtk_mfg_send_ipi(mfg, &msg); + if (ret) + return ret; + + if (readl(mfg->sram) !=3D GPUEB_SRAM_MAGIC) { + dev_err(dev, "EB did not initialise SRAM correctly\n"); + return -EIO; + } + + return 0; +} + +static int mtk_mfg_power_control(struct mtk_mfg *mfg, bool enabled) +{ + struct mtk_mfg_ipi_msg msg =3D {}; + + msg.cmd =3D CMD_POWER_CONTROL; + msg.u.power_state =3D enabled ? 1 : 0; + + return mtk_mfg_send_ipi(mfg, &msg); +} + +static int mtk_mfg_set_oppidx(struct mtk_mfg *mfg, int opp_idx) +{ + struct mtk_mfg_ipi_msg msg =3D {}; + int ret; + + if (!mfg->gpu_opps || !mfg->stack_opps) + return 0; + + if (opp_idx >=3D mfg->num_opps) + return -EINVAL; + + if (mfg->last_opp =3D=3D opp_idx) + return 0; + + msg.cmd =3D CMD_FIX_TARGET_OPPIDX; + msg.u.oppidx =3D opp_idx; + + ret =3D mtk_mfg_send_ipi(mfg, &msg); + if (ret) + return ret; + + mfg->last_opp =3D opp_idx; + + return 0; +} + +static int mtk_mfg_read_opp_tables(struct mtk_mfg *mfg) +{ + struct device *dev =3D &mfg->pdev->dev; + struct mtk_mfg_opp_entry e =3D {}; + unsigned int i; + unsigned long long last_freq; + + mfg->num_opps =3D readl(mfg->sram + GF_REG_GPU_OPP_NUM); + if (mfg->num_opps !=3D readl(mfg->sram + GF_REG_STK_OPP_NUM)) { + dev_err(dev, "OPP count of GPU and Stack differ, %u vs. %u\n", + mfg->num_opps, readl(mfg->sram + GF_REG_STK_OPP_NUM)); + return -EINVAL; + } + + if (mfg->num_opps > MAX_OPP_NUM || mfg->num_opps =3D=3D 0) { + dev_err(dev, "OPP count (%u) out of range %u >=3D count > 0\n", + mfg->num_opps, MAX_OPP_NUM); + return -EINVAL; + } + + mfg->gpu_opps =3D devm_kcalloc(dev, mfg->num_opps, + sizeof(struct dev_pm_opp_data), GFP_KERNEL); + if (!mfg->gpu_opps) + return -ENOMEM; + + mfg->stack_opps =3D devm_kcalloc(dev, mfg->num_opps, + sizeof(struct dev_pm_opp_data), GFP_KERNEL); + if (!mfg->stack_opps) + return -ENOMEM; + + for (i =3D 0; i < mfg->num_opps; i++) { + memcpy_fromio(&e, mfg->sram + GF_REG_OPP_TABLE_GPU + i * sizeof(e), + sizeof(e)); + if (mem_is_zero(&e, sizeof(e))) { + dev_err(dev, "ran into an empty GPU OPP at index %u\n", + i); + return -EINVAL; + } + mfg->gpu_opps[i].freq =3D e.freq_khz * 1000ULL; + mfg->gpu_opps[i].u_volt =3D e.voltage_core * 10; + + if (!last_freq || mfg->gpu_opps[i].freq !=3D last_freq) + mfg->num_unique_gpu_opps++; + + last_freq =3D mfg->gpu_opps[i].freq; + } + + /* + * Unused at present; we currently use the same OPP index for both GPU + * core and GPU stack, and the way they contain duplicates seems to + * indicate that this is the way to go. + * + * Might still be useful if we want to expose finer-grained adjustments + * or better information about expected power draw. + */ + for (i =3D 0; i < mfg->num_opps; i++) { + memcpy_fromio(&e, mfg->sram + GF_REG_OPP_TABLE_STK + i * sizeof(e), + sizeof(e)); + if (mem_is_zero(&e, sizeof(e))) { + dev_err(dev, "ran into an empty GPU OPP at index %u\n", + i); + return -EINVAL; + } + mfg->stack_opps[i].freq =3D e.freq_khz * 1000ULL; + mfg->stack_opps[i].u_volt =3D e.voltage_core * 10; + } + + return 0; +} + +static inline bool mtk_mfg_opp_idx_match(struct mtk_mfg *mfg, int idx, + unsigned long rate) +{ + if ((idx =3D=3D mfg->num_opps - 1) && mfg->gpu_opps[idx].freq >=3D rate) + return true; + + if (mfg->gpu_opps[idx].freq >=3D rate && mfg->gpu_opps[idx + 1].freq < ra= te) + return true; + + return false; +} + +/** + * mtk_mfg_get_closest_opp_idx - find OPP index for desired GPU frequency + * @mfg: pointer to a &struct mtk_mfg driver instance + * @gpu_rate: desired rate of the GPU core in Hz + * + * Given a desired target frequency for the GPU core, find the index of a + * matching OPP, or the next higher OPP if no exact match is found, or the + * maximum OPP for frequencies exceeding the maximum OPP's frequency. + * + * For duplicate OPP entries, chooses the highest OPP index, as in, the one + * closest to the next lower frequency OPP. + * + * Returns -EINVAL on error, or the OPP index on success. + */ +static int mtk_mfg_get_closest_opp_idx(struct mtk_mfg *mfg, unsigned long = gpu_rate) +{ + int r =3D mfg->num_opps - 1; + int l =3D 0; + int m; + + if (!mfg->gpu_opps) + return -EINVAL; + + if (mfg->gpu_opps[0].freq <=3D gpu_rate) + return 0; + + while (l <=3D r) { + m =3D l + (r - l) / 2; + if (mtk_mfg_opp_idx_match(mfg, m, gpu_rate)) + return m; + if (mfg->gpu_opps[m].freq >=3D gpu_rate) /* >=3D for dupes */ + l =3D m + 1; + else + r =3D m - 1; + } + + return -EINVAL; +} + +static int mtk_mfg_devfreq_target(struct device *dev, unsigned long *freq, + u32 flags) +{ + struct mtk_mfg *mfg =3D dev_get_drvdata(dev); + int ret, opp; + + opp =3D mtk_mfg_get_closest_opp_idx(mfg, *freq); + if (opp < 0) { + dev_err(dev, "Couldn't get closest OPP: %pe\n", ERR_PTR(opp)); + return opp; + } + + ret =3D pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + ret =3D mtk_mfg_set_oppidx(mfg, opp); + if (!ret) + *freq =3D mtk_mfg_read_gpu_freq(mfg); + else + dev_err(dev, "Couldn't set OPP: %pe\n", ERR_PTR(ret)); + + pm_runtime_put(dev); + + return ret; +} + +static int mtk_mfg_devfreq_get_cur_freq(struct device *dev, unsigned long = *freq) +{ + struct mtk_mfg *mfg =3D dev_get_drvdata(dev); + int ret; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + *freq =3D mtk_mfg_read_gpu_freq(mfg); + + pm_runtime_put(dev); + + return 0; +} + +static const char *const mtk_mfg_mt8196_clk_names[] =3D { + "core", + "stack0", + "stack1", +}; + +static const char *const mtk_mfg_mt8196_regulators[] =3D { + "core", + "stack", + "sram", +}; + +static int mtk_mfg_mt8196_init(struct mtk_mfg *mfg) +{ + void __iomem *e2_base; + + e2_base =3D devm_platform_ioremap_resource_byname(mfg->pdev, "hw-revision= "); + if (IS_ERR(e2_base)) + return dev_err_probe(&mfg->pdev->dev, PTR_ERR(e2_base), + "Couldn't get hw-revision register\n"); + + if (readl(e2_base) =3D=3D MFG_MT8196_E2_ID) + mfg->ghpm_en_reg =3D RPC_DUMMY_REG_2; + else + mfg->ghpm_en_reg =3D RPC_GHPM_CFG0_CON; + + return 0; +}; + +static const struct mtk_mfg_variant mtk_mfg_mt8196_variant =3D { + .clk_names =3D mtk_mfg_mt8196_clk_names, + .num_clks =3D ARRAY_SIZE(mtk_mfg_mt8196_clk_names), + .regulator_names =3D mtk_mfg_mt8196_regulators, + .num_regulators =3D ARRAY_SIZE(mtk_mfg_mt8196_regulators), + .init =3D mtk_mfg_mt8196_init, +}; + +static void mtk_mfg_mbox_rx_callback(struct mbox_client *cl, void *mssg) +{ + struct mtk_mfg_mbox *mb =3D container_of(cl, struct mtk_mfg_mbox, cl); + + if (mb->rx_data) + mb->rx_data =3D memcpy(mb->rx_data, mssg, MBOX_MAX_RX_SIZE); + complete(&mb->rx_done); +} + +static int mtk_mfg_init_mbox(struct mtk_mfg *mfg) +{ + struct device *dev =3D &mfg->pdev->dev; + struct mtk_mfg_mbox *gf; + struct mtk_mfg_mbox *slp; + + gf =3D devm_kzalloc(dev, sizeof(*gf), GFP_KERNEL); + if (!gf) + return -ENOMEM; + + slp =3D devm_kzalloc(dev, sizeof(*slp), GFP_KERNEL); + if (!slp) + return -ENOMEM; + + gf->mfg =3D mfg; + init_completion(&gf->rx_done); + gf->cl.dev =3D dev; + gf->cl.rx_callback =3D mtk_mfg_mbox_rx_callback; + gf->cl.tx_tout =3D GPUEB_TIMEOUT_US / USEC_PER_MSEC; + gf->rx_data =3D devm_kzalloc(dev, MBOX_MAX_RX_SIZE, GFP_KERNEL); + if (!gf->rx_data) + return -ENOMEM; + gf->ch =3D mbox_request_channel_byname(&gf->cl, "gpufreq"); + if (IS_ERR(gf->ch)) + return PTR_ERR(gf->ch); + + mfg->gf_mbox =3D gf; + + slp->mfg =3D mfg; + init_completion(&slp->rx_done); + slp->cl.dev =3D dev; + slp->cl.tx_tout =3D GPUEB_TIMEOUT_US / USEC_PER_MSEC; + slp->cl.tx_block =3D true; + slp->ch =3D mbox_request_channel_byname(&slp->cl, "sleep"); + if (IS_ERR(slp->ch)) + return PTR_ERR(slp->ch); + + mfg->slp_mbox =3D slp; + + return 0; +} + +static const struct of_device_id mtk_mfg_of_match[] =3D { + { .compatible =3D "mediatek,mt8196-gpufreq", .data =3D &mtk_mfg_mt8196_va= riant }, + {} +}; +MODULE_DEVICE_TABLE(of, mtk_mfg_of_match); + +static int mtk_mfg_probe(struct platform_device *pdev) +{ + struct device_node *shmem __free(device_node); + struct panthor_devfreq_provider *prov; + struct mtk_mfg *mfg; + struct device *dev =3D &pdev->dev; + const struct mtk_mfg_variant *data =3D of_device_get_match_data(dev); + struct resource res; + int ret, i, j; + + mfg =3D devm_kzalloc(dev, sizeof(*mfg), GFP_KERNEL); + if (!mfg) + return -ENOMEM; + + prov =3D devm_kzalloc(dev, sizeof(*prov), GFP_KERNEL); + if (!prov) + return -ENOMEM; + + prov->dev =3D dev; + prov->get_cur_freq =3D mtk_mfg_devfreq_get_cur_freq; + prov->target =3D mtk_mfg_devfreq_target; + + mfg->pdev =3D pdev; + mfg->variant =3D data; + + dev_set_drvdata(dev, mfg); + + mfg->gpr =3D devm_platform_ioremap_resource_byname(pdev, "gpr"); + if (IS_ERR(mfg->gpr)) + return dev_err_probe(dev, PTR_ERR(mfg->gpr), + "Could not retrieve GPR MMIO registers\n"); + + mfg->rpc =3D devm_platform_ioremap_resource_byname(pdev, "rpc"); + if (IS_ERR(mfg->rpc)) + return dev_err_probe(dev, PTR_ERR(mfg->rpc), + "Could not retrieve RPC MMIO registers\n"); + + mfg->clk_eb =3D devm_clk_get(dev, "eb"); + if (IS_ERR(mfg->clk_eb)) + return dev_err_probe(dev, PTR_ERR(mfg->clk_eb), + "Could not get 'eb' clock\n"); + + mfg->gpu_clks =3D devm_kcalloc(dev, data->num_clks, sizeof(*mfg->gpu_clks= ), + GFP_KERNEL); + if (!mfg->gpu_clks) + return -ENOMEM; + + for (i =3D 0; i < data->num_clks; i++) + mfg->gpu_clks[i].id =3D data->clk_names[i]; + + ret =3D devm_clk_bulk_get(dev, data->num_clks, mfg->gpu_clks); + if (ret) + return dev_err_probe(dev, ret, "couldn't get GPU clocks\n"); + + mfg->gpu_regs =3D devm_kcalloc(dev, data->num_regulators, + sizeof(*mfg->gpu_regs), GFP_KERNEL); + if (!mfg->gpu_regs) + return -ENOMEM; + + for (i =3D 0; i < data->num_regulators; i++) + mfg->gpu_regs[i].supply =3D data->regulator_names[i]; + + ret =3D devm_regulator_bulk_get(dev, data->num_regulators, mfg->gpu_regs); + if (ret) + return dev_err_probe(dev, ret, "couldn't get GPU regulators\n"); + + shmem =3D of_parse_phandle(dev->of_node, "shmem", 0); + if (!shmem) + return dev_err_probe(dev, -ENODEV, "Could not get 'shmem'\n"); + + ret =3D of_address_to_resource(shmem, 0, &res); + if (ret) + return dev_err_probe(dev, ret, + "failed to get GPUEB shared memory\n"); + + mfg->sram =3D devm_ioremap(dev, res.start, resource_size(&res)); + if (!mfg->sram) + return dev_err_probe(dev, -EADDRNOTAVAIL, + "failed to ioremap GPUEB sram\n"); + mfg->sram_size =3D resource_size(&res); + mfg->sram_phys =3D res.start; + + if (data->init) { + ret =3D data->init(mfg); + if (ret) + return dev_err_probe(dev, ret, "Variant init failed\n"); + } + + ret =3D clk_prepare_enable(mfg->clk_eb); + if (ret) + return dev_err_probe(dev, ret, "failed to turn on EB clock\n"); + mfg->ipi_magic =3D readl(mfg->gpr + GPR_IPI_MAGIC); + /* Downstream does this, don't know why. */ + writel(0x0, mfg->gpr + GPR_IPI_MAGIC); + + ret =3D mtk_mfg_init_mbox(mfg); + if (ret) { + ret =3D dev_err_probe(dev, ret, "Couldn't initialise mailbox\n"); + goto out; + } + + clk_disable_unprepare(mfg->clk_eb); + + mfg->last_opp =3D -1; + + devm_pm_runtime_enable(dev); + + ret =3D pm_runtime_resume_and_get(dev); + if (ret) + return dev_err_probe(dev, ret, "Failed to power on MFG\n"); + + ret =3D mtk_mfg_init_shared_mem(mfg); + if (ret) { + dev_err(dev, "Couldn't initialize EB SRAM: %pe\n", ERR_PTR(ret)); + goto out; + } + + ret =3D mtk_mfg_read_opp_tables(mfg); + if (ret) { + dev_err(dev, "Error reading OPP tables from EB: %pe\n", + ERR_PTR(ret)); + goto out; + } + + /* gpu_opps may contain duplicates and is sorted the other way */ + prov->opp_table =3D devm_kmalloc_array(dev, mfg->num_unique_gpu_opps, + sizeof(*prov->opp_table), GFP_KERNEL); + if (!prov->opp_table) { + ret =3D -ENOMEM; + goto out; + } + + prov->num_opps =3D mfg->num_unique_gpu_opps; + + j =3D 0; + for (i =3D mfg->num_opps - 1; i >=3D 0 && j < mfg->num_unique_gpu_opps; i= --) + if ((j =3D=3D 0) || (mfg->gpu_opps[i].freq !=3D prov->opp_table[j - 1]->= freq)) + prov->opp_table[j++] =3D &mfg->gpu_opps[i]; + + ret =3D panthor_devfreq_register_provider(prov); + +out: + pm_runtime_put(dev); + return ret; +} + +static int mtk_mfg_suspend(struct device *dev) +{ + struct mtk_mfg *mfg =3D dev_get_drvdata(dev); + int ret; + + ret =3D mtk_mfg_power_control(mfg, false); + if (ret) { + dev_err(dev, "power_control failed: %pe\n", ERR_PTR(ret)); + return ret; + } + ret =3D mtk_mfg_eb_off(mfg); + if (ret) { + dev_err(dev, "eb_off failed: %pe\n", ERR_PTR(ret)); + return ret; + } + clk_bulk_disable_unprepare(mfg->variant->num_clks, mfg->gpu_clks); + clk_disable_unprepare(mfg->clk_eb); + ret =3D regulator_bulk_disable(mfg->variant->num_regulators, mfg->gpu_reg= s); + + return ret; +} + +static int mtk_mfg_resume(struct device *dev) +{ + struct mtk_mfg *mfg =3D dev_get_drvdata(dev); + int ret; + + ret =3D regulator_bulk_enable(mfg->variant->num_regulators, + mfg->gpu_regs); + if (ret) + return ret; + + ret =3D clk_prepare_enable(mfg->clk_eb); + if (ret) + goto err_disable_regulators; + + ret =3D clk_bulk_prepare_enable(mfg->variant->num_clks, mfg->gpu_clks); + if (ret) + goto err_disable_eb_clk; + + ret =3D mtk_mfg_eb_on(mfg); + if (ret) + goto err_disable_clks; + + ret =3D mtk_mfg_power_control(mfg, true); + if (ret) + goto err_eb_off; + + return 0; + +err_eb_off: + mtk_mfg_eb_off(mfg); +err_disable_clks: + clk_bulk_disable_unprepare(mfg->variant->num_clks, mfg->gpu_clks); +err_disable_eb_clk: + clk_disable_unprepare(mfg->clk_eb); +err_disable_regulators: + regulator_bulk_disable(mfg->variant->num_regulators, mfg->gpu_regs); + + return ret; +} + + +static DEFINE_RUNTIME_DEV_PM_OPS(mtk_mfg_pm_ops, + mtk_mfg_suspend, + mtk_mfg_resume, + NULL); + +static struct platform_driver mtk_mfg_driver =3D { + .driver =3D { + .name =3D "panthor-mtk-mfg", + .of_match_table =3D mtk_mfg_of_match, + .pm =3D pm_ptr(&mtk_mfg_pm_ops), + }, + .probe =3D mtk_mfg_probe, +}; +module_platform_driver(mtk_mfg_driver); + +MODULE_SOFTDEP("pre: panthor"); +MODULE_AUTHOR("Nicolas Frattaroli "); +MODULE_DESCRIPTION("MediaTek MFlexGraphics Extension for Panthor"); +MODULE_LICENSE("GPL"); --=20 2.51.0