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Signed-off-by: Mikko Perttunen --- Changes in v2: - Pass register value as unsigned long to use with for_each_set_bit - Add unaligned register handling for Tegra186/194 - Link to v1: https://lore.kernel.org/r/20250707-host1x-syncpt-irq-perf-v1-= 1-16d53e516895@nvidia.com --- drivers/gpu/host1x/dev.c | 9 +++++++ drivers/gpu/host1x/dev.h | 3 +++ drivers/gpu/host1x/hw/intr_hw.c | 56 ++++++++++++++++++++++++++++++++++---= ---- 3 files changed, 59 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c index 1f93e5e276c0835eac2f713ffcd60a9db8db2c21..80380b6138276877be9709048c1= 5da85d079f977 100644 --- a/drivers/gpu/host1x/dev.c +++ b/drivers/gpu/host1x/dev.c @@ -71,6 +71,15 @@ u32 host1x_sync_readl(struct host1x *host1x, u32 r) return readl(sync_regs + r); } =20 +#ifdef CONFIG_64BIT +u64 host1x_sync_readq(struct host1x *host1x, u32 r) +{ + void __iomem *sync_regs =3D host1x->regs + host1x->info->sync_offset; + + return readq(sync_regs + r); +} +#endif + void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r) { writel(v, ch->regs + r); diff --git a/drivers/gpu/host1x/dev.h b/drivers/gpu/host1x/dev.h index d3855a1c6b472a9bd289c753d79906463e6bcdb4..ef44618ed88a128bae9ab712bf4= 9f8abc0f3b778 100644 --- a/drivers/gpu/host1x/dev.h +++ b/drivers/gpu/host1x/dev.h @@ -179,6 +179,9 @@ void host1x_hypervisor_writel(struct host1x *host1x, u3= 2 v, u32 r); u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r); void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r); u32 host1x_sync_readl(struct host1x *host1x, u32 r); +#ifdef CONFIG_64BIT +u64 host1x_sync_readq(struct host1x *host1x, u32 r); +#endif void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r); u32 host1x_ch_readl(struct host1x_channel *ch, u32 r); =20 diff --git a/drivers/gpu/host1x/hw/intr_hw.c b/drivers/gpu/host1x/hw/intr_h= w.c index 415f8d7e42021b791550ca719adafa088cd34101..aad4435256ba4257f19a20c02bf= a552229b62c55 100644 --- a/drivers/gpu/host1x/hw/intr_hw.c +++ b/drivers/gpu/host1x/hw/intr_hw.c @@ -11,26 +11,64 @@ #include "../intr.h" #include "../dev.h" =20 +static void process_32_syncpts(struct host1x *host, unsigned long val, u32= reg_offset) +{ + unsigned int id; + + if (!val) + return; + + host1x_sync_writel(host, val, HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(reg_o= ffset)); + host1x_sync_writel(host, val, HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(r= eg_offset)); + + for_each_set_bit(id, &val, 32) + host1x_intr_handle_interrupt(host, reg_offset * 32 + id); +} + static irqreturn_t syncpt_thresh_isr(int irq, void *dev_id) { struct host1x_intr_irq_data *irq_data =3D dev_id; struct host1x *host =3D irq_data->host; unsigned long reg; - unsigned int i, id; + unsigned int i; =20 +#if !defined(CONFIG_64BIT) for (i =3D irq_data->offset; i < DIV_ROUND_UP(host->info->nb_pts, 32); i +=3D host->num_syncpt_irqs) { reg =3D host1x_sync_readl(host, HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(i)); =20 - host1x_sync_writel(host, reg, - HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(i)); - host1x_sync_writel(host, reg, + process_32_syncpts(host, reg, i); + } +#elif HOST1X_HW =3D=3D 6 || HOST1X_HW =3D=3D 7 + /* + * Tegra186 and Tegra194 have the first INT_STATUS register not 64-bit al= igned, + * and only have one interrupt line. + */ + reg =3D host1x_sync_readl(host, HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS= (0)); + process_32_syncpts(host, reg, 0); + + for (i =3D 1; i < (host->info->nb_pts / 32) - 1; i +=3D 2) { + reg =3D host1x_sync_readq(host, HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(i)); =20 - for_each_set_bit(id, ®, 32) - host1x_intr_handle_interrupt(host, i * 32 + id); + process_32_syncpts(host, lower_32_bits(reg), i); + process_32_syncpts(host, upper_32_bits(reg), i+1); + } + + reg =3D host1x_sync_readl(host, HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS= (i)); + process_32_syncpts(host, reg, i); +#else + /* All 64-bit capable SoCs have number of syncpoints divisible by 64 */ + for (i =3D irq_data->offset; i < DIV_ROUND_UP(host->info->nb_pts, 64); + i +=3D host->num_syncpt_irqs) { + reg =3D host1x_sync_readq(host, + HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(i*2)); + + process_32_syncpts(host, lower_32_bits(reg), i*2+0); + process_32_syncpts(host, upper_32_bits(reg), i*2+1); } +#endif =20 return IRQ_HANDLED; } @@ -68,12 +106,12 @@ host1x_intr_init_host_sync(struct host1x *host, u32 cp= m) =20 /* * Program threshold interrupt destination among 8 lines per VM, - * per syncpoint. For each group of 32 syncpoints (corresponding to one - * interrupt status register), direct to one interrupt line, going + * per syncpoint. For each group of 64 syncpoints (corresponding to two + * interrupt status registers), direct to one interrupt line, going * around in a round robin fashion. */ for (id =3D 0; id < host->info->nb_pts; id++) { - u32 reg_offset =3D id / 32; + u32 reg_offset =3D id / 64; u32 irq_index =3D reg_offset % host->num_syncpt_irqs; =20 host1x_sync_writel(host, irq_index, HOST1X_SYNC_SYNCPT_INTR_DEST(id)); --- base-commit: 33bcf93b9a6b028758105680f8b538a31bc563cf change-id: 20250707-host1x-syncpt-irq-perf-a10b1d9313df