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[86.139.30.37]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3ecdc2deb20sm932154f8f.47.2025.09.16.08.03.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Sep 2025 08:03:02 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Greg Kroah-Hartman , Mathias Nyman , Geert Uytterhoeven , Magnus Damm , Philipp Zabel Cc: Biju Das , Krzysztof Kozlowski , Wesley Cheng , linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v3 6/9] usb: host: xhci-rcar: Add Renesas RZ/G3E USB3 Host driver support Date: Tue, 16 Sep 2025 16:02:42 +0100 Message-ID: <20250916150255.4231-7-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250916150255.4231-1-biju.das.jz@bp.renesas.com> References: <20250916150255.4231-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The USB3.2 Gen2 Host controller (a.k.a USB3HOST), IP found on the RZ/G3E SoC is similar to R-Car XHCI, but it doesn't require any firmware. Signed-off-by: Biju Das --- v2->v3: * No change. v1->v2: * No change. --- drivers/usb/host/Kconfig | 2 +- drivers/usb/host/xhci-rcar.c | 55 ++++++++++++++++++++++++++++++ drivers/usb/host/xhci-rzg3e-regs.h | 12 +++++++ 3 files changed, 68 insertions(+), 1 deletion(-) create mode 100644 drivers/usb/host/xhci-rzg3e-regs.h diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 109100cc77a3..c4f17ce5c77b 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -93,7 +93,7 @@ config USB_XHCI_RCAR default ARCH_RENESAS help Say 'Y' to enable the support for the xHCI host controller - found in Renesas R-Car ARM SoCs. + found in Renesas R-Car and RZ/G3E alike ARM SoCs. =20 config USB_XHCI_RZV2M bool "xHCI support for Renesas RZ/V2M SoC" diff --git a/drivers/usb/host/xhci-rcar.c b/drivers/usb/host/xhci-rcar.c index 6d4662def87f..8a993ee21c87 100644 --- a/drivers/usb/host/xhci-rcar.c +++ b/drivers/usb/host/xhci-rcar.c @@ -11,10 +11,12 @@ #include #include #include +#include =20 #include "xhci.h" #include "xhci-plat.h" #include "xhci-rcar-regs.h" +#include "xhci-rzg3e-regs.h" #include "xhci-rzv2m.h" =20 #define XHCI_RCAR_FIRMWARE_NAME_V1 "r8a779x_usb3_v1.dlmem" @@ -67,6 +69,48 @@ static void xhci_rcar_start(struct usb_hcd *hcd) } } =20 +static void xhci_rzg3e_start(struct usb_hcd *hcd) +{ + u32 int_en; + + if (hcd->regs) { + /* Update the controller initial setting */ + writel(0x03130200, hcd->regs + RZG3E_USB3_HOST_U3P0PIPESC(0)); + writel(0x00160200, hcd->regs + RZG3E_USB3_HOST_U3P0PIPESC(1)); + writel(0x03150000, hcd->regs + RZG3E_USB3_HOST_U3P0PIPESC(2)); + writel(0x03130200, hcd->regs + RZG3E_USB3_HOST_U3P0PIPESC(3)); + writel(0x00180000, hcd->regs + RZG3E_USB3_HOST_U3P0PIPESC(4)); + + /* Interrupt Enable */ + int_en =3D readl(hcd->regs + RZG3E_USB3_HOST_INTEN); + int_en |=3D RZG3E_USB3_HOST_INTEN_ENA; + writel(int_en, hcd->regs + RZG3E_USB3_HOST_INTEN); + } +} + +static int xhci_rzg3e_resume(struct usb_hcd *hcd) +{ + struct xhci_hcd *xhci =3D hcd_to_xhci(hcd); + + return reset_control_deassert(xhci->reset); +} + +static int xhci_rzg3e_post_resume(struct usb_hcd *hcd) +{ + xhci_rzg3e_start(hcd); + + return 0; +} + +static int xhci_rzg3e_suspend(struct usb_hcd *hcd) +{ + struct xhci_hcd *xhci =3D hcd_to_xhci(hcd); + + reset_control_assert(xhci->reset); + + return 0; +} + static int xhci_rcar_download_firmware(struct usb_hcd *hcd) { struct device *dev =3D hcd->self.controller; @@ -190,6 +234,14 @@ static const struct xhci_plat_priv xhci_plat_renesas_r= zv2m =3D { .plat_start =3D xhci_rzv2m_start, }; =20 +static const struct xhci_plat_priv xhci_plat_renesas_rzg3e =3D { + .quirks =3D XHCI_NO_64BIT_SUPPORT | XHCI_RESET_ON_RESUME | XHCI_SUSPEND_R= ESUME_CLKS, + .plat_start =3D xhci_rzg3e_start, + .suspend_quirk =3D xhci_rzg3e_suspend, + .resume_quirk =3D xhci_rzg3e_resume, + .post_resume_quirk =3D xhci_rzg3e_post_resume, +}; + static const struct of_device_id usb_xhci_of_match[] =3D { { .compatible =3D "renesas,xhci-r8a7790", @@ -206,6 +258,9 @@ static const struct of_device_id usb_xhci_of_match[] = =3D { }, { .compatible =3D "renesas,xhci-r8a7796", .data =3D &xhci_plat_renesas_rcar_gen3, + }, { + .compatible =3D "renesas,r9a09g047-xhci", + .data =3D &xhci_plat_renesas_rzg3e, }, { .compatible =3D "renesas,rcar-gen2-xhci", .data =3D &xhci_plat_renesas_rcar_gen2, diff --git a/drivers/usb/host/xhci-rzg3e-regs.h b/drivers/usb/host/xhci-rzg= 3e-regs.h new file mode 100644 index 000000000000..7a244a47b882 --- /dev/null +++ b/drivers/usb/host/xhci-rzg3e-regs.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __XHCI_RZG3E_H +#define __XHCI_RZG3E_H + +#define RZG3E_USB3_HOST_INTEN 0x1044 /* Interrupt Enable */ +#define RZG3E_USB3_HOST_U3P0PIPESC(x) (0x10c0 + (x) * 4) /* PIPE Status an= d Control Register */ + +#define RZG3E_USB3_HOST_INTEN_XHC BIT(0) +#define RZG3E_USB3_HOST_INTEN_HSE BIT(2) +#define RZG3E_USB3_HOST_INTEN_ENA (RZG3E_USB3_HOST_INTEN_XHC | RZG3E_USB3_= HOST_INTEN_HSE) + +#endif /* __XHCI_RZG3E_H */ --=20 2.43.0