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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Sep 2025 10:43:28.0629 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4fcdfb5e-0294-494f-0795-08ddf50ddf0c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989E7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6383 Content-Type: text/plain; charset="utf-8" AMD MDB PCIe endpoint support. For AMD specific support added the following - AMD supported PCIe Device IDs and Vendor ID (Xilinx). - AMD MDB specific driver data - AMD MDB specific VSEC capability to retrieve the device DDR base address. Signed-off-by: Devendra K Verma --- Changes in v2: Reverted the devmem_phys_off type to u64. Renamed the function appropriately to suit the functionality for setting the LL & data region offsets. Changes in v1: Removed the pci device id from pci_ids.h file. Added the vendor id macro as per the suggested method. Changed the type of the newly added devmem_phys_off variable. Added to logic to assign offsets for LL and data region blocks in case more number of channels are enabled than given in amd_mdb_data struct. --- drivers/dma/dw-edma/dw-edma-pcie.c | 147 +++++++++++++++++++++++++++++++++= +++- 1 file changed, 145 insertions(+), 2 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-ed= ma-pcie.c index 3371e0a7..50f8002 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -17,12 +17,19 @@ =20 #include "dw-edma-core.h" =20 +/* Synopsys */ #define DW_PCIE_VSEC_DMA_ID 0x6 #define DW_PCIE_VSEC_DMA_BAR GENMASK(10, 8) #define DW_PCIE_VSEC_DMA_MAP GENMASK(2, 0) #define DW_PCIE_VSEC_DMA_WR_CH GENMASK(9, 0) #define DW_PCIE_VSEC_DMA_RD_CH GENMASK(25, 16) =20 +/* AMD MDB specific defines */ +#define DW_PCIE_XILINX_MDB_VSEC_DMA_ID 0x6 +#define DW_PCIE_XILINX_MDB_VSEC_ID 0x20 +#define PCI_DEVICE_ID_AMD_MDB_B054 0xb054 +#define DW_PCIE_AMD_MDB_INVALID_ADDR (~0ULL) + #define DW_BLOCK(a, b, c) \ { \ .bar =3D a, \ @@ -50,6 +57,7 @@ struct dw_edma_pcie_data { u8 irqs; u16 wr_ch_cnt; u16 rd_ch_cnt; + u64 devmem_phys_off; }; =20 static const struct dw_edma_pcie_data snps_edda_data =3D { @@ -90,6 +98,91 @@ struct dw_edma_pcie_data { .rd_ch_cnt =3D 2, }; =20 +static const struct dw_edma_pcie_data amd_mdb_data =3D { + /* MDB registers location */ + .rg.bar =3D BAR_0, + .rg.off =3D 0x00001000, /* 4 Kbytes */ + .rg.sz =3D 0x00002000, /* 8 Kbytes */ + /* MDB memory linked list location */ + .ll_wr =3D { + /* Channel 0 - BAR 2, offset 0 Mbytes, size 2 Kbytes */ + DW_BLOCK(BAR_2, 0x00000000, 0x00000800) + /* Channel 1 - BAR 2, offset 2 Mbytes, size 2 Kbytes */ + DW_BLOCK(BAR_2, 0x00200000, 0x00000800) + }, + .ll_rd =3D { + /* Channel 0 - BAR 2, offset 4 Mbytes, size 2 Kbytes */ + DW_BLOCK(BAR_2, 0x00400000, 0x00000800) + /* Channel 1 - BAR 2, offset 6 Mbytes, size 2 Kbytes */ + DW_BLOCK(BAR_2, 0x00600000, 0x00000800) + }, + /* MDB memory data location */ + .dt_wr =3D { + /* Channel 0 - BAR 2, offset 8 Mbytes, size 2 Kbytes */ + DW_BLOCK(BAR_2, 0x00800000, 0x00000800) + /* Channel 1 - BAR 2, offset 9 Mbytes, size 2 Kbytes */ + DW_BLOCK(BAR_2, 0x00900000, 0x00000800) + }, + .dt_rd =3D { + /* Channel 0 - BAR 2, offset 10 Mbytes, size 2 Kbytes */ + DW_BLOCK(BAR_2, 0x00a00000, 0x00000800) + /* Channel 1 - BAR 2, offset 11 Mbytes, size 2 Kbytes */ + DW_BLOCK(BAR_2, 0x00b00000, 0x00000800) + }, + /* Other */ + .mf =3D EDMA_MF_HDMA_NATIVE, + .irqs =3D 1, + .wr_ch_cnt =3D 2, + .rd_ch_cnt =3D 2, +}; + +static void dw_edma_set_chan_region_offset(struct dw_edma_pcie_data *pdata, + enum pci_barno bar, off_t start_off, + off_t off_gap, size_t size) +{ + u16 i; + off_t off; + u16 wr_ch =3D pdata->wr_ch_cnt; + u16 rd_ch =3D pdata->rd_ch_cnt; + + if (wr_ch <=3D 2 || rd_ch <=3D 2) + return; + + off =3D start_off; + + /* Write channel LL region */ + for (i =3D 0; i < wr_ch; i++) { + pdata->ll_wr[i].bar =3D bar; + pdata->ll_wr[i].off =3D off; + pdata->ll_wr[i].sz =3D size; + off +=3D off_gap + size; + } + + /* Read channel LL region */ + for (i =3D 0; i < rd_ch; i++) { + pdata->ll_rd[i].bar =3D bar; + pdata->ll_rd[i].off =3D off; + pdata->ll_rd[i].sz =3D size; + off +=3D off_gap + size; + } + + /* Write channel data region */ + for (i =3D 0; i < wr_ch; i++) { + pdata->dt_wr[i].bar =3D bar; + pdata->dt_wr[i].off =3D off; + pdata->dt_wr[i].sz =3D size; + off +=3D off_gap + size; + } + + /* Read channel data region */ + for (i =3D 0; i < rd_ch; i++) { + pdata->dt_rd[i].bar =3D bar; + pdata->dt_rd[i].off =3D off; + pdata->dt_rd[i].sz =3D size; + off +=3D off_gap + size; + } +} + static int dw_edma_pcie_irq_vector(struct device *dev, unsigned int nr) { return pci_irq_vector(to_pci_dev(dev), nr); @@ -120,9 +213,22 @@ static void dw_edma_pcie_get_vsec_dma_data(struct pci_= dev *pdev, u32 val, map; u16 vsec; u64 off; + u16 vendor =3D pdev->vendor; + int cap; =20 - vsec =3D pci_find_vsec_capability(pdev, PCI_VENDOR_ID_SYNOPSYS, - DW_PCIE_VSEC_DMA_ID); + /* + * Synopsys and AMD (Xilinx) use the same VSEC ID for the purpose + * of map, channel counts, etc. + */ + if (vendor !=3D PCI_VENDOR_ID_SYNOPSYS || + vendor !=3D PCI_VENDOR_ID_XILINX) + return; + + cap =3D DW_PCIE_VSEC_DMA_ID; + if (vendor =3D=3D PCI_VENDOR_ID_XILINX) + cap =3D DW_PCIE_XILINX_MDB_VSEC_ID; + + vsec =3D pci_find_vsec_capability(pdev, vendor, cap); if (!vsec) return; =20 @@ -155,6 +261,24 @@ static void dw_edma_pcie_get_vsec_dma_data(struct pci_= dev *pdev, off <<=3D 32; off |=3D val; pdata->rg.off =3D off; + + /* AMD specific VSEC capability */ + vsec =3D pci_find_vsec_capability(pdev, vendor, + DW_PCIE_XILINX_MDB_VSEC_ID); + if (!vsec) + return; + + pci_read_config_dword(pdev, vsec + PCI_VNDR_HEADER, &val); + if (PCI_VNDR_HEADER_ID(val) !=3D 0x20 || + PCI_VNDR_HEADER_REV(val) !=3D 0x1) + return; + + pci_read_config_dword(pdev, vsec + 0xc, &val); + off =3D val; + pci_read_config_dword(pdev, vsec + 0x8, &val); + off <<=3D 32; + off |=3D val; + pdata->devmem_phys_off =3D off; } =20 static int dw_edma_pcie_probe(struct pci_dev *pdev, @@ -179,6 +303,7 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, } =20 memcpy(vsec_data, pdata, sizeof(struct dw_edma_pcie_data)); + vsec_data->devmem_phys_off =3D DW_PCIE_AMD_MDB_INVALID_ADDR; =20 /* * Tries to find if exists a PCIe Vendor-Specific Extended Capability @@ -186,6 +311,22 @@ static int dw_edma_pcie_probe(struct pci_dev *pdev, */ dw_edma_pcie_get_vsec_dma_data(pdev, vsec_data); =20 + if (pdev->vendor =3D=3D PCI_VENDOR_ID_XILINX) { + /* + * There is no valid address found for the LL memory + * space on the device side. + */ + if (vsec_data->devmem_phys_off =3D=3D DW_PCIE_AMD_MDB_INVALID_ADDR) + return -EINVAL; + + /* + * Configure the channel LL and data blocks if number of + * channels enabled in VSEC capability are more than the + * channels configured in amd_mdb_data. + */ + dw_edma_set_chan_region_offset(vsec_data, BAR_2, 0, 0x200000, 0x800); + } + /* Mapping PCI BAR regions */ mask =3D BIT(vsec_data->rg.bar); for (i =3D 0; i < vsec_data->wr_ch_cnt; i++) { @@ -367,6 +508,8 @@ static void dw_edma_pcie_remove(struct pci_dev *pdev) =20 static const struct pci_device_id dw_edma_pcie_id_table[] =3D { { PCI_DEVICE_DATA(SYNOPSYS, EDDA, &snps_edda_data) }, + { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_AMD_MDB_B054), + (kernel_ulong_t)&amd_mdb_data }, { } }; MODULE_DEVICE_TABLE(pci, dw_edma_pcie_id_table); --=20 1.8.3.1