From nobody Thu Oct 2 14:26:18 2025 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 751712EC0A7 for ; Tue, 16 Sep 2025 10:04:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758017107; cv=none; b=IGzA/Rkg7rlhrJFJyUaHVeK5GSUC3QpYvY+Wj27AQZtOcDF7XXNVwYmPWTm+8RMwruIeNcxNaQMATSdJB8muR5ZVWxVd4fF1AhkMxCYfRGvZofNzuwJdAtES5Dlt3ggStlS8hr+sOzbELsHK3U/9udoftGWbNyxgIWvMB3z+7lg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758017107; c=relaxed/simple; bh=dGCs+/xCdCk59ZK1jDd5wfKYdT5wxUGoVifwoS8BGac=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tgkOSZaQ1s+JJzQvKV8WZFUbBl59wxyCESnjM6ZH154bf2Q7pciFA6nZ2ghO7SopNIPVP1FFrAaxvDXhXDrWZLRYU08ZWNtsxdAzrK+zbZZ5O5LXX7/MaUyRpEq4tO7L8FtZU/XzsHJENe7TDn/zND4mtE17kqoMCjYevY4wd0c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 58GA4SgF067801 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 16 Sep 2025 18:04:28 +0800 (+08) (envelope-from randolph@andestech.com) Received: from atctrx.andestech.com (10.0.15.173) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Tue, 16 Sep 2025 18:04:28 +0800 From: Randolph Lin To: CC: , , , , , , , , , , , , , , , , , , , , , , Randolph Lin Subject: [PATCH v2 4/5] PCI: andes: Add Andes QiLai SoC PCIe host driver support Date: Tue, 16 Sep 2025 18:04:16 +0800 Message-ID: <20250916100417.3036847-5-randolph@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250916100417.3036847-1-randolph@andestech.com> References: <20250916100417.3036847-1-randolph@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 58GA4SgF067801 Content-Type: text/plain; charset="utf-8" Add driver support for DesignWare based PCIe controller in Andes QiLai SoC. The driver only supports the Root Complex mode. Signed-off-by: Randolph Lin --- drivers/pci/controller/dwc/Kconfig | 16 ++ drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-andes-qilai.c | 214 ++++++++++++++++++ 3 files changed, 231 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie-andes-qilai.c diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dw= c/Kconfig index ff6b6d9e18ec..6dc7af3dcea9 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -49,6 +49,22 @@ config PCIE_AMD_MDB DesignWare IP and therefore the driver re-uses the DesignWare core functions to implement the driver. =20 +config PCIE_ANDES_QILAI + bool "ANDES QiLai PCIe controller" + depends on OF && (RISCV || COMPILE_TEST) + depends on PCI_MSI + depends on ARCH_ANDES + select PCIE_DW_HOST + help + Say Y here to enable PCIe controller support on Andes QiLai SoCs, + which operate in Root Complex mode. The Andes QiLai SoCs PCIe + controller is based on DesignWare IP (5.97a version) and therefore + the driver re-uses the DesignWare core functions to implement the + driver. The Andes QiLai SoC has three Root Complexes (RCs): one + operates on PCIe 4.0 with 4 lanes at 0x80000000, while the other + two operate on PCIe 4.0 with 2 lanes at 0xA0000000 and 0xC0000000, + respectively. + config PCI_MESON tristate "Amlogic Meson PCIe controller" default m if ARCH_MESON diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/d= wc/Makefile index 6919d27798d1..de9583cbd675 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_PCIE_DW_HOST) +=3D pcie-designware-host.o obj-$(CONFIG_PCIE_DW_EP) +=3D pcie-designware-ep.o obj-$(CONFIG_PCIE_DW_PLAT) +=3D pcie-designware-plat.o obj-$(CONFIG_PCIE_AMD_MDB) +=3D pcie-amd-mdb.o +obj-$(CONFIG_PCIE_ANDES_QILAI) +=3D pcie-andes-qilai.o obj-$(CONFIG_PCIE_BT1) +=3D pcie-bt1.o obj-$(CONFIG_PCI_DRA7XX) +=3D pci-dra7xx.o obj-$(CONFIG_PCI_EXYNOS) +=3D pci-exynos.o diff --git a/drivers/pci/controller/dwc/pcie-andes-qilai.c b/drivers/pci/co= ntroller/dwc/pcie-andes-qilai.c new file mode 100644 index 000000000000..c7f5dffa3e20 --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-andes-qilai.c @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for the PCIe Controller in QiLai from Andes + * + * Copyright (C) 2025 Andes Technology Corporation + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-designware.h" + +#define PCIE_INTR_CONTROL1 0x15c +#define PCIE_MSI_CTRL_INT_EN BIT(28) + +#define PCIE_LOGIC_COHERENCY_CONTROL3 0x8e8 + +/* + * Refer to Table A4-5 (Memory type encoding) in the + * AMBA AXI and ACE Protocol Specification. + * The selected value corresponds to the Memory type field: + * "Write-back, Read and Write-allocate". + */ +#define IOCP_ARCACHE 0b1111 +#define IOCP_AWCACHE 0b1111 + +#define PCIE_CFG_MSTR_ARCACHE_MODE GENMASK(6, 3) +#define PCIE_CFG_MSTR_AWCACHE_MODE GENMASK(14, 11) +#define PCIE_CFG_MSTR_ARCACHE_VALUE GENMASK(22, 19) +#define PCIE_CFG_MSTR_AWCACHE_VALUE GENMASK(30, 27) + +#define PCIE_GEN_CONTROL2 0x54 +#define PCIE_CFG_LTSSM_EN BIT(0) + +#define PCIE_REGS_PCIE_SII_PM_STATE 0xc0 +#define SMLH_LINK_UP BIT(6) +#define RDLH_LINK_UP BIT(7) +#define PCIE_REGS_PCIE_SII_LINK_UP (SMLH_LINK_UP | RDLH_LINK_UP) + +struct qilai_pcie { + struct dw_pcie pci; + struct platform_device *pdev; + void __iomem *apb_base; +}; + +#define to_qilai_pcie(_pci) container_of(_pci, struct qilai_pcie, pci) + +static +bool qilai_pcie_outbound_atu_addr_valid(struct dw_pcie *pci, + const struct dw_pcie_ob_atu_cfg *atu, + u64 *limit_addr) +{ + u64 parent_bus_addr =3D atu->parent_bus_addr; + + *limit_addr =3D parent_bus_addr + atu->size - 1; + + /* + * Addresses below 4 GB are not 1:1 mapped; therefore, range checks + * only need to ensure addresses below 4 GB match pci->region_limit. + */ + if (lower_32_bits(*limit_addr & ~pci->region_limit) !=3D + lower_32_bits(parent_bus_addr & ~pci->region_limit) || + !IS_ALIGNED(parent_bus_addr, pci->region_align) || + !IS_ALIGNED(atu->pci_addr, pci->region_align) || !atu->size) + return false; + + return true; +} + +static bool qilai_pcie_link_up(struct dw_pcie *pci) +{ + struct qilai_pcie *pcie =3D to_qilai_pcie(pci); + u32 val; + + /* Read smlh & rdlh link up by checking debug port */ + val =3D readl(pcie->apb_base + PCIE_REGS_PCIE_SII_PM_STATE); + + return (val & PCIE_REGS_PCIE_SII_LINK_UP) =3D=3D PCIE_REGS_PCIE_SII_LINK_= UP; +} + +static int qilai_pcie_start_link(struct dw_pcie *pci) +{ + struct qilai_pcie *pcie =3D to_qilai_pcie(pci); + u32 val; + + val =3D readl(pcie->apb_base + PCIE_GEN_CONTROL2); + val |=3D PCIE_CFG_LTSSM_EN; + writel(val, pcie->apb_base + PCIE_GEN_CONTROL2); + + return 0; +} + +static const struct dw_pcie_ops qilai_pcie_ops =3D { + .outbound_atu_addr_valid =3D qilai_pcie_outbound_atu_addr_valid, + .link_up =3D qilai_pcie_link_up, + .start_link =3D qilai_pcie_start_link, +}; + +/* + * Setup the Qilai PCIe IOCP (IO Coherence Port) Read/Write Behaviors to t= he + * Write-Back, Read and Write Allocate mode. + * The IOCP HW target is SoC last-level cache (L2 Cache), which serves as = the + * system cache. + * The IOCP HW helps maintain cache monitoring, ensuring that the device c= an + * snoop data from/to the cache. + */ +static void qilai_pcie_iocp_cache_setup(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + u32 val; + + dw_pcie_dbi_ro_wr_en(pci); + + dw_pcie_read(pci->dbi_base + PCIE_LOGIC_COHERENCY_CONTROL3, + sizeof(val), &val); + FIELD_MODIFY(PCIE_CFG_MSTR_ARCACHE_MODE, &val, IOCP_ARCACHE); + FIELD_MODIFY(PCIE_CFG_MSTR_AWCACHE_MODE, &val, IOCP_AWCACHE); + FIELD_MODIFY(PCIE_CFG_MSTR_ARCACHE_VALUE, &val, IOCP_ARCACHE); + FIELD_MODIFY(PCIE_CFG_MSTR_AWCACHE_VALUE, &val, IOCP_AWCACHE); + dw_pcie_write(pci->dbi_base + PCIE_LOGIC_COHERENCY_CONTROL3, + sizeof(val), val); + + dw_pcie_dbi_ro_wr_dis(pci); +} + +static void qilai_pcie_enable_msi(struct qilai_pcie *pcie) +{ + u32 val; + + val =3D readl(pcie->apb_base + PCIE_INTR_CONTROL1); + val |=3D PCIE_MSI_CTRL_INT_EN; + writel(val, pcie->apb_base + PCIE_INTR_CONTROL1); +} + +static int qilai_pcie_host_init(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct qilai_pcie *pcie =3D to_qilai_pcie(pci); + + qilai_pcie_enable_msi(pcie); + + return 0; +} + +static const struct dw_pcie_host_ops qilai_pcie_host_ops =3D { + .init =3D qilai_pcie_host_init, +}; + +static int qilai_pcie_probe(struct platform_device *pdev) +{ + struct qilai_pcie *pcie; + struct dw_pcie *pci; + struct device *dev; + int ret; + + pcie =3D devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL); + if (!pcie) + return -ENOMEM; + + pcie->pdev =3D pdev; + platform_set_drvdata(pdev, pcie); + + pci =3D &pcie->pci; + dev =3D &pcie->pdev->dev; + pcie->pci.dev =3D dev; + pcie->pci.ops =3D &qilai_pcie_ops; + pcie->pci.pp.ops =3D &qilai_pcie_host_ops; + pci->use_parent_dt_ranges =3D true; + + dw_pcie_cap_set(&pcie->pci, REQ_RES); + + pcie->apb_base =3D devm_platform_ioremap_resource_byname(pdev, "apb"); + if (IS_ERR(pcie->apb_base)) { + dev_err_probe(dev, ret, "Failed to Get APB registers.\n"); + return PTR_ERR(pcie->apb_base); + } + + ret =3D dw_pcie_host_init(&pcie->pci.pp); + if (ret) { + dev_err_probe(dev, ret, "Failed to initialize PCIe host\n"); + return ret; + } + + qilai_pcie_iocp_cache_setup(&pcie->pci.pp); + + return 0; +} + +static const struct of_device_id qilai_pcie_of_match[] =3D { + { .compatible =3D "andestech,qilai-pcie" }, + {}, +}; +MODULE_DEVICE_TABLE(of, qilai_pcie_of_match); + +static struct platform_driver qilai_pcie_driver =3D { + .probe =3D qilai_pcie_probe, + .driver =3D { + .name =3D "qilai-pcie", + .of_match_table =3D qilai_pcie_of_match, + /* only test passed at PROBE_DEFAULT_STRATEGY */ + .probe_type =3D PROBE_DEFAULT_STRATEGY, + }, +}; + +builtin_platform_driver(qilai_pcie_driver); + +MODULE_AUTHOR("Randolph Lin "); +MODULE_DESCRIPTION("Andes Qilai PCIe driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1