From nobody Thu Oct 2 14:26:18 2025 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6EC12C3257 for ; Tue, 16 Sep 2025 10:04:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758017088; cv=none; b=cF9j4Av8CQIMiP3ps3N3pLT9z9pODnf/Yr/ZkAZhtRi2Mow2A5JoHOIiI8UjKiGOfU9jVV4hU1f1ccbPCtYhC+6wfz1Zx8D5ecAlSekkbTtqdkFaX3lQjoVOgYyzgWgF7pnlnnMarhbgnsmDb6UPxcXvuEpO31Ohv1Zb9NAa3V4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758017088; c=relaxed/simple; bh=jHU400IsoN/UwulISHshcn2dTNANoVVkVRVZpGK+3sU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=rVea/lZeb2Suicntn0INYZND59kWs6NMS09rUEoQNbFbtE0SXs4LRkfyUKvKNpvLiysX+akR8y2St/8d0NcGngo1mayG4Fpn75qqm52xpCDzGepcvpYVhkMa0t//FRGOeyewwvOMuZm8FJq3cHTZunNfMFhEMrvUMsgvIiavfZo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 58GA4QXx067800 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 16 Sep 2025 18:04:26 +0800 (+08) (envelope-from randolph@andestech.com) Received: from atctrx.andestech.com (10.0.15.173) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Tue, 16 Sep 2025 18:04:26 +0800 From: Randolph Lin To: CC: , , , , , , , , , , , , , , , , , , , , , , Randolph Lin Subject: [PATCH v2 3/5] riscv: dts: andes: Add PCIe node into the QiLai SoC Date: Tue, 16 Sep 2025 18:04:15 +0800 Message-ID: <20250916100417.3036847-4-randolph@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250916100417.3036847-1-randolph@andestech.com> References: <20250916100417.3036847-1-randolph@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 58GA4QXx067800 Content-Type: text/plain; charset="utf-8" Add the Andes QiLai PCIe node, which includes 3 Root Complexes. Signed-off-by: Randolph Lin --- arch/riscv/boot/dts/andes/qilai.dtsi | 109 +++++++++++++++++++++++++++ 1 file changed, 109 insertions(+) diff --git a/arch/riscv/boot/dts/andes/qilai.dtsi b/arch/riscv/boot/dts/and= es/qilai.dtsi index de3de32f8c39..d475b5fe2356 100644 --- a/arch/riscv/boot/dts/andes/qilai.dtsi +++ b/arch/riscv/boot/dts/andes/qilai.dtsi @@ -182,5 +182,114 @@ uart0: serial@30300000 { reg-io-width =3D <4>; no-loopback-test; }; + + bus@80000000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-ranges =3D <0x44 0x00000000 0x04 0x00000000 0x04 0x00000000>; + ranges =3D <0x00 0x80000000 0x00 0x80000000 0x00 0x20000000>, + <0x00 0x04000000 0x00 0x04000000 0x00 0x00001000>, + <0x00 0x00000000 0x20 0x00000000 0x20 0x00000000>; + + pci@80000000 { + compatible =3D "andestech,qilai-pcie"; + device_type =3D "pci"; + reg =3D <0x00 0x80000000 0x00 0x20000000>, /* DBI registers */ + <0x00 0x04000000 0x00 0x00001000>, /* APB registers */ + <0x00 0x00000000 0x00 0x00010000>; /* Configuration registers */ + reg-names =3D "dbi", "apb", "config"; + + bus-range =3D <0x0 0xff>; + num-viewport =3D <4>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x02000000 0x00 0x10000000 0x00 0x10000000 0x00 0xf0000000= >, + <0x43000000 0x01 0x00000000 0x01 0x00000000 0x1f 0x00000000>; + + #interrupt-cells =3D <1>; + interrupts =3D <0xf 0x4>; + interrupt-names =3D "msi"; + interrupt-parent =3D <&plic>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 1 &plic 0xf 0x4>, + <0 0 0 2 &plic 0xf 0x4>, + <0 0 0 3 &plic 0xf 0x4>, + <0 0 0 4 &plic 0xf 0x4>; + }; + }; + + bus@a0000000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-ranges =3D <0x44 0x00000000 0x04 0x00000000 0x04 0x00000000>; + ranges =3D <0x00 0xa0000000 0x00 0xa0000000 0x00 0x20000000>, + <0x00 0x04001000 0x00 0x04001000 0x00 0x00001000>, + <0x00 0x00000000 0x10 0x00000000 0x08 0x00000000>; + + pci@a0000000 { + compatible =3D "andestech,qilai-pcie"; + device_type =3D "pci"; + reg =3D <0x00 0xa0000000 0x00 0x20000000>, /* DBI registers */ + <0x00 0x04001000 0x00 0x00001000>, /* APB registers */ + <0x00 0x00000000 0x00 0x00010000>; /* Configuration registers */ + reg-names =3D "dbi", "apb", "config"; + + bus-range =3D <0x0 0xff>; + num-viewport =3D <4>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x02000000 0x00 0x10000000 0x00 0x10000000 0x0 0xf0000000>, + <0x43000000 0x01 0x00000000 0x01 0x00000000 0x7 0x00000000>; + + #interrupt-cells =3D <1>; + interrupts =3D <0xe 0x4>; + interrupt-names =3D "msi"; + interrupt-parent =3D <&plic>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 1 &plic 0xe 0x4>, + <0 0 0 2 &plic 0xe 0x4>, + <0 0 0 3 &plic 0xe 0x4>, + <0 0 0 4 &plic 0xe 0x4>; + }; + }; + + bus@c0000000 { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-ranges =3D <0x44 0x00000000 0x04 0x00000000 0x04 0x00000000>; + ranges =3D <0x00 0xc0000000 0x00 0xc0000000 0x00 0x20000000>, + <0x00 0x04002000 0x00 0x04002000 0x00 0x00001000>, + <0x00 0x00000000 0x18 0x00000000 0x08 0x00000000>; + + pci@c0000000 { + compatible =3D "andestech,qilai-pcie"; + device_type =3D "pci"; + reg =3D <0x00 0xc0000000 0x00 0x20000000>, /* DBI registers */ + <0x00 0x04002000 0x00 0x00001000>, /* APB registers */ + <0x00 0x00000000 0x00 0x00010000>; /* Configuration registers */ + reg-names =3D "dbi", "apb", "config"; + + bus-range =3D <0x0 0xff>; + num-viewport =3D <4>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x02000000 0x00 0x10000000 0x00 0x10000000 0x0 0xf0000000>, + <0x43000000 0x01 0x00000000 0x01 0x00000000 0x7 0x00000000>; + + #interrupt-cells =3D <1>; + interrupts =3D <0xd 0x4>; + interrupt-names =3D "msi"; + interrupt-parent =3D <&plic>; + interrupt-map-mask =3D <0 0 0 0>; + interrupt-map =3D <0 0 0 1 &plic 0xd 0x4>, + <0 0 0 2 &plic 0xd 0x4>, + <0 0 0 3 &plic 0xd 0x4>, + <0 0 0 4 &plic 0xd 0x4>; + }; + }; + }; }; --=20 2.34.1