From nobody Thu Oct 2 15:35:37 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52B4829B8FE; Tue, 16 Sep 2025 08:45:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758012312; cv=none; b=e/8qt6PsBWwigTjxhra92Ivw+fPC5nXXRi4jX5fzDBq60LwfTu/LE2v6MbdMmtasXFlkIIJ6SER623KDpwKnVxN12wwJOxoTG+e6VdFjXCDXfiZPcfvUhmR2inL4cZTx6v1srKPKRBgYLVUdnN++LSX1kHVTAQIbLQlsrGnidds= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758012312; c=relaxed/simple; bh=v51zz4Jv1mbYpBxEB5zBU7XOsgjUAXrR8IuArlSYLn8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fM45q2JzeKkU+JBzbKpRoj3OyY2i7+C2OU8kpN4xC+hbf1k6RQl5Oye8Pj/kGmyZdzNDUr4CeItN8SJayzz8SW/Ufr2OdFBMt1H2vMOgPfkPrAM1+Y3tBajSEtkz0cP53pLhr1nDqb1SjZvbWyAHiM8DYlrcaIDHrTqjMT2W0dg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=O7aQB+My; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="O7aQB+My" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1758012303; bh=v51zz4Jv1mbYpBxEB5zBU7XOsgjUAXrR8IuArlSYLn8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=O7aQB+My51APmWdeJ8JYiLlp1O8g2Smg9q9rYH2kM0kckDCZQulpyYkoYE4Nl17h4 wV5BVbSH0pE2liWPrvChDI/MTFtTCl0yGHZMYQSwUGGwixQB+ttHjYiVSN/k55N88/ JyYO73q8fk7SGhDRm+Mr8IzkmowKygCaq09SGceEbULSaoyZOxKfReF3R6fJYxi+A4 TyIwSVmkW6haaLhRsuwIY3h0D/ndYGBsZmILnTGzmDvixVwv0OYrW9gTY26rX4zIs+ rAZWDNd9gwJQvXnBRUr5yX4j74HkV9YXPa5JCTi/SH2xSuquNEBW+AQlSA651OZPFt 1lf82ObEEWp2g== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 9059B17E139F; Tue, 16 Sep 2025 10:45:02 +0200 (CEST) From: AngeloGioacchino Del Regno To: sboyd@kernel.org Cc: jic23@kernel.org, dlechner@baylibre.com, nuno.sa@analog.com, andy@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org, srini@kernel.org, vkoul@kernel.org, kishon@kernel.org, sre@kernel.org, krzysztof.kozlowski@linaro.org, u.kleine-koenig@baylibre.com, angelogioacchino.delregno@collabora.com, linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-pm@vger.kernel.org, kernel@collabora.com, wenst@chromium.org, casey.connolly@linaro.org, Neil Armstrong Subject: [PATCH v4 5/7] misc: qcom-coincell: Migrate to devm_spmi_subdevice_alloc_and_add() Date: Tue, 16 Sep 2025 10:44:43 +0200 Message-ID: <20250916084445.96621-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250916084445.96621-1-angelogioacchino.delregno@collabora.com> References: <20250916084445.96621-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some Qualcomm PMICs integrate a charger for coincells, usually powering an RTC when external (or main battery) power is missing. Instead of using the parent SPMI device (the main PMIC) as a kind of syscon in this driver, register a new SPMI sub-device and initialize its own regmap with this sub-device's specific base address, retrieved from the devicetree. This allows to stop manually adding the register base address to every R/W call in this driver, as this can be, and is now, handled by the regmap API instead. Acked-by: Greg Kroah-Hartman Link: https://lore.kernel.org/r/20250722101317.76729-6-angelogioacchino.del= regno@collabora.com Tested-by: Neil Armstrong # on SM8650-QRD Link: https://lore.kernel.org/r/20250730112645.542179-6-angelogioacchino.de= lregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- drivers/misc/Kconfig | 1 + drivers/misc/qcom-coincell.c | 38 +++++++++++++++++++++++++----------- 2 files changed, 28 insertions(+), 11 deletions(-) diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index b9c11f67315f..6bc14ae52ecb 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -291,6 +291,7 @@ config HP_ILO config QCOM_COINCELL tristate "Qualcomm coincell charger support" depends on MFD_SPMI_PMIC || COMPILE_TEST + select REGMAP_SPMI help This driver supports the coincell block found inside of Qualcomm PMICs. The coincell charger provides a means to diff --git a/drivers/misc/qcom-coincell.c b/drivers/misc/qcom-coincell.c index 3c57f7429147..49e38442b289 100644 --- a/drivers/misc/qcom-coincell.c +++ b/drivers/misc/qcom-coincell.c @@ -9,11 +9,11 @@ #include #include #include +#include =20 struct qcom_coincell { struct device *dev; struct regmap *regmap; - u32 base_addr; }; =20 #define QCOM_COINCELL_REG_RSET 0x44 @@ -35,7 +35,7 @@ static int qcom_coincell_chgr_config(struct qcom_coincell= *chgr, int rset, /* if disabling, just do that and skip other operations */ if (!enable) return regmap_write(chgr->regmap, - chgr->base_addr + QCOM_COINCELL_REG_ENABLE, 0); + QCOM_COINCELL_REG_ENABLE, 0); =20 /* find index for current-limiting resistor */ for (i =3D 0; i < ARRAY_SIZE(qcom_rset_map); i++) @@ -58,7 +58,7 @@ static int qcom_coincell_chgr_config(struct qcom_coincell= *chgr, int rset, } =20 rc =3D regmap_write(chgr->regmap, - chgr->base_addr + QCOM_COINCELL_REG_RSET, i); + QCOM_COINCELL_REG_RSET, i); if (rc) { /* * This is mainly to flag a bad base_addr (reg) from dts. @@ -71,19 +71,28 @@ static int qcom_coincell_chgr_config(struct qcom_coince= ll *chgr, int rset, } =20 rc =3D regmap_write(chgr->regmap, - chgr->base_addr + QCOM_COINCELL_REG_VSET, j); + QCOM_COINCELL_REG_VSET, j); if (rc) return rc; =20 /* set 'enable' register */ return regmap_write(chgr->regmap, - chgr->base_addr + QCOM_COINCELL_REG_ENABLE, + QCOM_COINCELL_REG_ENABLE, QCOM_COINCELL_ENABLE); } =20 static int qcom_coincell_probe(struct platform_device *pdev) { - struct device_node *node =3D pdev->dev.of_node; + struct regmap_config qcom_coincell_regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 8, + .max_register =3D 0x100, + .fast_io =3D true, + }; + struct device *dev =3D &pdev->dev; + struct device_node *node =3D dev->of_node; + struct spmi_subdevice *sub_sdev; + struct spmi_device *sparent; struct qcom_coincell chgr; u32 rset =3D 0; u32 vset =3D 0; @@ -92,16 +101,22 @@ static int qcom_coincell_probe(struct platform_device = *pdev) =20 chgr.dev =3D &pdev->dev; =20 - chgr.regmap =3D dev_get_regmap(pdev->dev.parent, NULL); + rc =3D of_property_read_u32(node, "reg", &qcom_coincell_regmap_config.reg= _base); + if (rc) + return rc; + + sparent =3D to_spmi_device(dev->parent); + sub_sdev =3D devm_spmi_subdevice_alloc_and_add(dev, sparent); + if (IS_ERR(sub_sdev)) + return PTR_ERR(sub_sdev); + + chgr.regmap =3D devm_regmap_init_spmi_ext(&sub_sdev->sdev, + &qcom_coincell_regmap_config); if (!chgr.regmap) { dev_err(chgr.dev, "Unable to get regmap\n"); return -EINVAL; } =20 - rc =3D of_property_read_u32(node, "reg", &chgr.base_addr); - if (rc) - return rc; - enable =3D !of_property_read_bool(node, "qcom,charger-disable"); =20 if (enable) { @@ -142,3 +157,4 @@ module_platform_driver(qcom_coincell_driver); =20 MODULE_DESCRIPTION("Qualcomm PMIC coincell charger driver"); MODULE_LICENSE("GPL v2"); +MODULE_IMPORT_NS("SPMI"); --=20 2.51.0