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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Sep 2025 05:18:50.6933 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 840e06b3-c22e-4de3-2793-08ddf4e085a0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E61.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9171 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Group MC error related registers into a struct as they could have soc specific values. Signed-off-by: Ketan Patil --- drivers/memory/tegra/mc.c | 45 +++++++++++++++++++++++---------- drivers/memory/tegra/mc.h | 14 ---------- drivers/memory/tegra/tegra114.c | 3 ++- drivers/memory/tegra/tegra124.c | 4 ++- drivers/memory/tegra/tegra186.c | 1 + drivers/memory/tegra/tegra194.c | 3 ++- drivers/memory/tegra/tegra20.c | 3 ++- drivers/memory/tegra/tegra210.c | 3 ++- drivers/memory/tegra/tegra234.c | 3 ++- drivers/memory/tegra/tegra30.c | 3 ++- include/soc/tegra/mc.h | 21 ++++++++++++++- 11 files changed, 67 insertions(+), 36 deletions(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 6edb210287dc..6c1578b25a61 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -56,6 +56,23 @@ static const struct of_device_id tegra_mc_of_match[] =3D= { }; MODULE_DEVICE_TABLE(of, tegra_mc_of_match); =20 +const struct tegra_mc_regs tegra20_mc_regs =3D { + .mc_cfg_channel_enable =3D 0xdf8, + .mc_err_status =3D 0x08, + .mc_err_add =3D 0x0c, + .mc_err_add_hi =3D 0x11fc, + .mc_err_vpr_status =3D 0x654, + .mc_err_vpr_add =3D 0x658, + .mc_err_sec_status =3D 0x67c, + .mc_err_sec_add =3D 0x680, + .mc_err_mts_status =3D 0x9b0, + .mc_err_mts_add =3D 0x9b4, + .mc_err_gen_co_status =3D 0xc00, + .mc_err_gen_co_add =3D 0xc04, + .mc_err_route_status =3D 0x9c0, + .mc_err_route_add =3D 0x9c4, +}; + static void tegra_mc_devm_action_put_device(void *data) { struct tegra_mc *mc =3D data; @@ -600,37 +617,37 @@ irqreturn_t tegra30_mc_handle_irq(int irq, void *data) =20 switch (intmask) { case MC_INT_DECERR_VPR: - status_reg =3D MC_ERR_VPR_STATUS; - addr_reg =3D MC_ERR_VPR_ADR; + status_reg =3D mc->soc->mc_regs->mc_err_vpr_status; + addr_reg =3D mc->soc->mc_regs->mc_err_vpr_add; break; =20 case MC_INT_SECERR_SEC: - status_reg =3D MC_ERR_SEC_STATUS; - addr_reg =3D MC_ERR_SEC_ADR; + status_reg =3D mc->soc->mc_regs->mc_err_sec_status; + addr_reg =3D mc->soc->mc_regs->mc_err_sec_add; break; =20 case MC_INT_DECERR_MTS: - status_reg =3D MC_ERR_MTS_STATUS; - addr_reg =3D MC_ERR_MTS_ADR; + status_reg =3D mc->soc->mc_regs->mc_err_mts_status; + addr_reg =3D mc->soc->mc_regs->mc_err_mts_add; break; =20 case MC_INT_DECERR_GENERALIZED_CARVEOUT: - status_reg =3D MC_ERR_GENERALIZED_CARVEOUT_STATUS; - addr_reg =3D MC_ERR_GENERALIZED_CARVEOUT_ADR; + status_reg =3D mc->soc->mc_regs->mc_err_gen_co_status; + addr_reg =3D mc->soc->mc_regs->mc_err_gen_co_add; break; =20 case MC_INT_DECERR_ROUTE_SANITY: - status_reg =3D MC_ERR_ROUTE_SANITY_STATUS; - addr_reg =3D MC_ERR_ROUTE_SANITY_ADR; + status_reg =3D mc->soc->mc_regs->mc_err_route_status; + addr_reg =3D mc->soc->mc_regs->mc_err_route_add; break; =20 default: - status_reg =3D MC_ERR_STATUS; - addr_reg =3D MC_ERR_ADR; + status_reg =3D mc->soc->mc_regs->mc_err_status; + addr_reg =3D mc->soc->mc_regs->mc_err_add; =20 #ifdef CONFIG_PHYS_ADDR_T_64BIT if (mc->soc->has_addr_hi_reg) - addr_hi_reg =3D MC_ERR_ADR_HI; + addr_hi_reg =3D mc->soc->mc_regs->mc_err_add_hi; #endif break; } @@ -883,7 +900,7 @@ static void tegra_mc_num_channel_enabled(struct tegra_m= c *mc) unsigned int i; u32 value; =20 - value =3D mc_ch_readl(mc, 0, MC_EMEM_ADR_CFG_CHANNEL_ENABLE); + value =3D mc_ch_readl(mc, 0, mc->soc->mc_regs->mc_cfg_channel_enable); if (value <=3D 0) { mc->num_channels =3D mc->soc->num_channels; return; diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index 1d97cf4d3a94..a7f20850741f 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -14,8 +14,6 @@ =20 #define MC_INTSTATUS 0x00 #define MC_INTMASK 0x04 -#define MC_ERR_STATUS 0x08 -#define MC_ERR_ADR 0x0c #define MC_GART_ERROR_REQ 0x30 #define MC_EMEM_ADR_CFG 0x54 #define MC_DECERR_EMEM_OTHERS_STATUS 0x58 @@ -43,19 +41,7 @@ #define MC_EMEM_ARB_OVERRIDE 0xe8 #define MC_TIMING_CONTROL_DBG 0xf8 #define MC_TIMING_CONTROL 0xfc -#define MC_ERR_VPR_STATUS 0x654 -#define MC_ERR_VPR_ADR 0x658 -#define MC_ERR_SEC_STATUS 0x67c -#define MC_ERR_SEC_ADR 0x680 -#define MC_ERR_MTS_STATUS 0x9b0 -#define MC_ERR_MTS_ADR 0x9b4 -#define MC_ERR_ROUTE_SANITY_STATUS 0x9c0 -#define MC_ERR_ROUTE_SANITY_ADR 0x9c4 -#define MC_ERR_GENERALIZED_CARVEOUT_STATUS 0xc00 -#define MC_ERR_GENERALIZED_CARVEOUT_ADR 0xc04 -#define MC_EMEM_ADR_CFG_CHANNEL_ENABLE 0xdf8 #define MC_GLOBAL_INTSTATUS 0xf24 -#define MC_ERR_ADR_HI 0x11fc =20 #define MC_INT_DECERR_ROUTE_SANITY BIT(20) #define MC_INT_DECERR_GENERALIZED_CARVEOUT BIT(17) diff --git a/drivers/memory/tegra/tegra114.c b/drivers/memory/tegra/tegra11= 4.c index 41350570c815..cc66620da60b 100644 --- a/drivers/memory/tegra/tegra114.c +++ b/drivers/memory/tegra/tegra114.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2014-2025 NVIDIA CORPORATION. All rights reserved. */ =20 #include @@ -1114,4 +1114,5 @@ const struct tegra_mc_soc tegra114_mc_soc =3D { .resets =3D tegra114_mc_resets, .num_resets =3D ARRAY_SIZE(tegra114_mc_resets), .ops =3D &tegra30_mc_ops, + .mc_regs =3D &tegra20_mc_regs, }; diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra12= 4.c index 9d7393e19f12..886dc68fea65 100644 --- a/drivers/memory/tegra/tegra124.c +++ b/drivers/memory/tegra/tegra124.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2014-2025 NVIDIA CORPORATION. All rights reserved. */ =20 #include @@ -1275,6 +1275,7 @@ const struct tegra_mc_soc tegra124_mc_soc =3D { .num_resets =3D ARRAY_SIZE(tegra124_mc_resets), .icc_ops =3D &tegra124_mc_icc_ops, .ops =3D &tegra30_mc_ops, + .mc_regs =3D &tegra20_mc_regs, }; #endif /* CONFIG_ARCH_TEGRA_124_SOC */ =20 @@ -1307,5 +1308,6 @@ const struct tegra_mc_soc tegra132_mc_soc =3D { .num_resets =3D ARRAY_SIZE(tegra124_mc_resets), .icc_ops =3D &tegra124_mc_icc_ops, .ops =3D &tegra30_mc_ops, + .mc_regs =3D &tegra20_mc_regs, }; #endif /* CONFIG_ARCH_TEGRA_132_SOC */ diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra18= 6.c index aee11457bf8e..a30158d92412 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -914,5 +914,6 @@ const struct tegra_mc_soc tegra186_mc_soc =3D { .ops =3D &tegra186_mc_ops, .ch_intmask =3D 0x0000000f, .global_intstatus_channel_shift =3D 0, + .mc_regs =3D &tegra20_mc_regs, }; #endif diff --git a/drivers/memory/tegra/tegra194.c b/drivers/memory/tegra/tegra19= 4.c index 26035ac3a1eb..fade258c0ea7 100644 --- a/drivers/memory/tegra/tegra194.c +++ b/drivers/memory/tegra/tegra194.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2017-2021 NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2017-2025 NVIDIA CORPORATION. All rights reserved. */ =20 #include @@ -1358,4 +1358,5 @@ const struct tegra_mc_soc tegra194_mc_soc =3D { .icc_ops =3D &tegra_mc_icc_ops, .ch_intmask =3D 0x00000f00, .global_intstatus_channel_shift =3D 8, + .mc_regs =3D &tegra20_mc_regs, }; diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra20.c index a3022e715dee..46e97bb10163 100644 --- a/drivers/memory/tegra/tegra20.c +++ b/drivers/memory/tegra/tegra20.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2012-2025 NVIDIA CORPORATION. All rights reserved. */ =20 #include @@ -778,4 +778,5 @@ const struct tegra_mc_soc tegra20_mc_soc =3D { .num_resets =3D ARRAY_SIZE(tegra20_mc_resets), .icc_ops =3D &tegra20_mc_icc_ops, .ops =3D &tegra20_mc_ops, + .mc_regs =3D &tegra20_mc_regs, }; diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra21= 0.c index cfa61dd88557..994b1e0e7f37 100644 --- a/drivers/memory/tegra/tegra210.c +++ b/drivers/memory/tegra/tegra210.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2015 NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2015-2025 NVIDIA CORPORATION. All rights reserved. */ =20 #include @@ -1287,4 +1287,5 @@ const struct tegra_mc_soc tegra210_mc_soc =3D { .resets =3D tegra210_mc_resets, .num_resets =3D ARRAY_SIZE(tegra210_mc_resets), .ops =3D &tegra30_mc_ops, + .mc_regs =3D &tegra20_mc_regs, }; diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra23= 4.c index 5f57cea48b62..23276f622aab 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2022-2023, NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2022-2025, NVIDIA CORPORATION. All rights reserved. */ =20 #include @@ -1152,4 +1152,5 @@ const struct tegra_mc_soc tegra234_mc_soc =3D { * supported. */ .num_carveouts =3D 32, + .mc_regs =3D &tegra20_mc_regs, }; diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c index d3e685c8431f..f22febcbee59 100644 --- a/drivers/memory/tegra/tegra30.c +++ b/drivers/memory/tegra/tegra30.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved. + * Copyright (C) 2014-2025 NVIDIA CORPORATION. All rights reserved. */ =20 #include @@ -1400,4 +1400,5 @@ const struct tegra_mc_soc tegra30_mc_soc =3D { .num_resets =3D ARRAY_SIZE(tegra30_mc_resets), .icc_ops =3D &tegra30_mc_icc_ops, .ops =3D &tegra30_mc_ops, + .mc_regs =3D &tegra20_mc_regs, }; diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 6ee4c59db620..d11dfefbe551 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (C) 2014 NVIDIA Corporation + * Copyright (C) 2014-2025 NVIDIA Corporation */ =20 #ifndef __SOC_TEGRA_MC_H__ @@ -168,6 +168,23 @@ struct tegra_mc_ops { int (*probe_device)(struct tegra_mc *mc, struct device *dev); }; =20 +struct tegra_mc_regs { + unsigned int mc_cfg_channel_enable; + unsigned int mc_err_status; + unsigned int mc_err_add; + unsigned int mc_err_add_hi; + unsigned int mc_err_vpr_status; + unsigned int mc_err_vpr_add; + unsigned int mc_err_sec_status; + unsigned int mc_err_sec_add; + unsigned int mc_err_mts_status; + unsigned int mc_err_mts_add; + unsigned int mc_err_gen_co_status; + unsigned int mc_err_gen_co_add; + unsigned int mc_err_route_status; + unsigned int mc_err_route_add; +}; + struct tegra_mc_soc { const struct tegra_mc_client *clients; unsigned int num_clients; @@ -196,6 +213,7 @@ struct tegra_mc_soc { =20 const struct tegra_mc_icc_ops *icc_ops; const struct tegra_mc_ops *ops; + const struct tegra_mc_regs *mc_regs; }; =20 struct tegra_mc { @@ -256,4 +274,5 @@ tegra_mc_get_carveout_info(struct tegra_mc *mc, unsigne= d int id, } #endif =20 +extern const struct tegra_mc_regs tegra20_mc_regs; #endif /* __SOC_TEGRA_MC_H__ */ --=20 2.17.1