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([2.196.40.230]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45f32640f49sm530985e9.9.2025.09.15.12.53.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Sep 2025 12:53:52 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Frank Li , linux-amarula@amarulasolutions.com, Michael Trimarchi , Dario Binacchi , Dmitry Torokhov , Fabio Estevam , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org Subject: [PATCH v3 1/6] Input: imx6ul_tsc - fix typo in register name Date: Mon, 15 Sep 2025 21:53:03 +0200 Message-ID: <20250915195335.1710780-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250915195335.1710780-1-dario.binacchi@amarulasolutions.com> References: <20250915195335.1710780-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Michael Trimarchi Replace 'SETING' with 'SETTING'. Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi Reviewed-by: Frank Li --- (no changes since v2) Changes in v2: - Add Reviewed-by tag of Frank Li. drivers/input/touchscreen/imx6ul_tsc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/input/touchscreen/imx6ul_tsc.c b/drivers/input/touchsc= reen/imx6ul_tsc.c index 6ac8fa84ed9f..c2c6e50efc54 100644 --- a/drivers/input/touchscreen/imx6ul_tsc.c +++ b/drivers/input/touchscreen/imx6ul_tsc.c @@ -55,7 +55,7 @@ #define ADC_TIMEOUT msecs_to_jiffies(100) =20 /* TSC registers */ -#define REG_TSC_BASIC_SETING 0x00 +#define REG_TSC_BASIC_SETTING 0x00 #define REG_TSC_PRE_CHARGE_TIME 0x10 #define REG_TSC_FLOW_CONTROL 0x20 #define REG_TSC_MEASURE_VALUE 0x30 @@ -192,7 +192,7 @@ static void imx6ul_tsc_set(struct imx6ul_tsc *tsc) =20 basic_setting |=3D tsc->measure_delay_time << 8; basic_setting |=3D DETECT_4_WIRE_MODE | AUTO_MEASURE; - writel(basic_setting, tsc->tsc_regs + REG_TSC_BASIC_SETING); + writel(basic_setting, tsc->tsc_regs + REG_TSC_BASIC_SETTING); =20 writel(DE_GLITCH_2, tsc->tsc_regs + REG_TSC_DEBUG_MODE2); =20 --=20 2.43.0 From nobody Thu Oct 2 14:27:55 2025 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD155289E0F for ; Mon, 15 Sep 2025 19:53:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757966038; cv=none; b=h/MDkBrC318DQCTi94WzLJqYtSAjktGMOnL9WHvX3YoTVucwplR3Y1GYibPtIM5gf3zBzyVq1IlNkzN+IMSms1/e4jb5S4wxrfLIPS54+NgESp83DG3WJtrYr8O+eBSi+J59XmVoT7BJr99tNjeDXsa+7c4RsUoNPamoSs0VQSc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757966038; c=relaxed/simple; bh=SWFqSXFx87fpKeGP6WN4l1K7YHQdzfNtqBr/fu+vOFA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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([2.196.40.230]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45f32640f49sm530985e9.9.2025.09.15.12.53.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Sep 2025 12:53:53 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Frank Li , linux-amarula@amarulasolutions.com, Dario Binacchi , Dmitry Torokhov , Fabio Estevam , Michael Trimarchi , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org Subject: [PATCH v3 2/6] Input: imx6ul_tsc - use BIT, FIELD_{GET,PREP} and GENMASK macros Date: Mon, 15 Sep 2025 21:53:04 +0200 Message-ID: <20250915195335.1710780-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250915195335.1710780-1-dario.binacchi@amarulasolutions.com> References: <20250915195335.1710780-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace opencoded masking and shifting, with BIT(), GENMASK(), FIELD_GET() and FIELD_PREP() macros. Signed-off-by: Dario Binacchi Reviewed-by: Frank Li --- (no changes since v2) Changes in v2: - Add Reviewed-by tag of Frank Li. - Move the patch right after the one fixing the typo according to Frank Li's suggestions. drivers/input/touchscreen/imx6ul_tsc.c | 96 +++++++++++++++----------- 1 file changed, 54 insertions(+), 42 deletions(-) diff --git a/drivers/input/touchscreen/imx6ul_tsc.c b/drivers/input/touchsc= reen/imx6ul_tsc.c index c2c6e50efc54..e2c59cc7c82c 100644 --- a/drivers/input/touchscreen/imx6ul_tsc.c +++ b/drivers/input/touchscreen/imx6ul_tsc.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -20,25 +21,23 @@ #include =20 /* ADC configuration registers field define */ -#define ADC_AIEN (0x1 << 7) +#define ADC_AIEN BIT(7) +#define ADC_ADCH_MASK GENMASK(4, 0) #define ADC_CONV_DISABLE 0x1F -#define ADC_AVGE (0x1 << 5) -#define ADC_CAL (0x1 << 7) -#define ADC_CALF 0x2 -#define ADC_12BIT_MODE (0x2 << 2) -#define ADC_CONV_MODE_MASK (0x3 << 2) +#define ADC_AVGE BIT(5) +#define ADC_CAL BIT(7) +#define ADC_CALF BIT(1) +#define ADC_CONV_MODE_MASK GENMASK(3, 2) +#define ADC_12BIT_MODE 0x2 #define ADC_IPG_CLK 0x00 -#define ADC_INPUT_CLK_MASK 0x3 -#define ADC_CLK_DIV_8 (0x03 << 5) -#define ADC_CLK_DIV_MASK (0x3 << 5) -#define ADC_SHORT_SAMPLE_MODE (0x0 << 4) -#define ADC_SAMPLE_MODE_MASK (0x1 << 4) -#define ADC_HARDWARE_TRIGGER (0x1 << 13) -#define ADC_AVGS_SHIFT 14 -#define ADC_AVGS_MASK (0x3 << 14) +#define ADC_INPUT_CLK_MASK GENMASK(1, 0) +#define ADC_CLK_DIV_8 0x03 +#define ADC_CLK_DIV_MASK GENMASK(6, 5) +#define ADC_SAMPLE_MODE BIT(4) +#define ADC_HARDWARE_TRIGGER BIT(13) +#define ADC_AVGS_MASK GENMASK(15, 14) #define SELECT_CHANNEL_4 0x04 #define SELECT_CHANNEL_1 0x01 -#define DISABLE_CONVERSION_INT (0x0 << 7) =20 /* ADC registers */ #define REG_ADC_HC0 0x00 @@ -65,19 +64,26 @@ #define REG_TSC_DEBUG_MODE 0x70 #define REG_TSC_DEBUG_MODE2 0x80 =20 +/* TSC_MEASURE_VALUE register field define */ +#define X_VALUE_MASK GENMASK(27, 16) +#define Y_VALUE_MASK GENMASK(11, 0) + /* TSC configuration registers field define */ -#define DETECT_4_WIRE_MODE (0x0 << 4) -#define AUTO_MEASURE 0x1 -#define MEASURE_SIGNAL 0x1 -#define DETECT_SIGNAL (0x1 << 4) -#define VALID_SIGNAL (0x1 << 8) -#define MEASURE_INT_EN 0x1 -#define MEASURE_SIG_EN 0x1 -#define VALID_SIG_EN (0x1 << 8) -#define DE_GLITCH_2 (0x2 << 29) -#define START_SENSE (0x1 << 12) -#define TSC_DISABLE (0x1 << 16) +#define MEASURE_DELAY_TIME_MASK GENMASK(31, 8) +#define DETECT_5_WIRE_MODE BIT(4) +#define AUTO_MEASURE BIT(0) +#define MEASURE_SIGNAL BIT(0) +#define DETECT_SIGNAL BIT(4) +#define VALID_SIGNAL BIT(8) +#define MEASURE_INT_EN BIT(0) +#define MEASURE_SIG_EN BIT(0) +#define VALID_SIG_EN BIT(8) +#define DE_GLITCH_MASK GENMASK(30, 29) +#define DE_GLITCH_2 0x02 +#define START_SENSE BIT(12) +#define TSC_DISABLE BIT(16) #define DETECT_MODE 0x2 +#define STATE_MACHINE_MASK GENMASK(22, 20) =20 struct imx6ul_tsc { struct device *dev; @@ -112,19 +118,20 @@ static int imx6ul_adc_init(struct imx6ul_tsc *tsc) =20 adc_cfg =3D readl(tsc->adc_regs + REG_ADC_CFG); adc_cfg &=3D ~(ADC_CONV_MODE_MASK | ADC_INPUT_CLK_MASK); - adc_cfg |=3D ADC_12BIT_MODE | ADC_IPG_CLK; - adc_cfg &=3D ~(ADC_CLK_DIV_MASK | ADC_SAMPLE_MODE_MASK); - adc_cfg |=3D ADC_CLK_DIV_8 | ADC_SHORT_SAMPLE_MODE; + adc_cfg |=3D FIELD_PREP(ADC_CONV_MODE_MASK, ADC_12BIT_MODE) | + FIELD_PREP(ADC_INPUT_CLK_MASK, ADC_IPG_CLK); + adc_cfg &=3D ~(ADC_CLK_DIV_MASK | ADC_SAMPLE_MODE); + adc_cfg |=3D FIELD_PREP(ADC_CLK_DIV_MASK, ADC_CLK_DIV_8); if (tsc->average_enable) { adc_cfg &=3D ~ADC_AVGS_MASK; - adc_cfg |=3D (tsc->average_select) << ADC_AVGS_SHIFT; + adc_cfg |=3D FIELD_PREP(ADC_AVGS_MASK, tsc->average_select); } adc_cfg &=3D ~ADC_HARDWARE_TRIGGER; writel(adc_cfg, tsc->adc_regs + REG_ADC_CFG); =20 /* enable calibration interrupt */ adc_hc |=3D ADC_AIEN; - adc_hc |=3D ADC_CONV_DISABLE; + adc_hc |=3D FIELD_PREP(ADC_ADCH_MASK, ADC_CONV_DISABLE); writel(adc_hc, tsc->adc_regs + REG_ADC_HC0); =20 /* start ADC calibration */ @@ -164,19 +171,21 @@ static void imx6ul_tsc_channel_config(struct imx6ul_t= sc *tsc) { u32 adc_hc0, adc_hc1, adc_hc2, adc_hc3, adc_hc4; =20 - adc_hc0 =3D DISABLE_CONVERSION_INT; + adc_hc0 =3D FIELD_PREP(ADC_AIEN, 0); writel(adc_hc0, tsc->adc_regs + REG_ADC_HC0); =20 - adc_hc1 =3D DISABLE_CONVERSION_INT | SELECT_CHANNEL_4; + adc_hc1 =3D FIELD_PREP(ADC_AIEN, 0) | + FIELD_PREP(ADC_ADCH_MASK, SELECT_CHANNEL_4); writel(adc_hc1, tsc->adc_regs + REG_ADC_HC1); =20 - adc_hc2 =3D DISABLE_CONVERSION_INT; + adc_hc2 =3D FIELD_PREP(ADC_AIEN, 0); writel(adc_hc2, tsc->adc_regs + REG_ADC_HC2); =20 - adc_hc3 =3D DISABLE_CONVERSION_INT | SELECT_CHANNEL_1; + adc_hc3 =3D FIELD_PREP(ADC_AIEN, 0) | + FIELD_PREP(ADC_ADCH_MASK, SELECT_CHANNEL_1); writel(adc_hc3, tsc->adc_regs + REG_ADC_HC3); =20 - adc_hc4 =3D DISABLE_CONVERSION_INT; + adc_hc4 =3D FIELD_PREP(ADC_AIEN, 0); writel(adc_hc4, tsc->adc_regs + REG_ADC_HC4); } =20 @@ -188,13 +197,16 @@ static void imx6ul_tsc_channel_config(struct imx6ul_t= sc *tsc) static void imx6ul_tsc_set(struct imx6ul_tsc *tsc) { u32 basic_setting =3D 0; + u32 debug_mode2; u32 start; =20 - basic_setting |=3D tsc->measure_delay_time << 8; - basic_setting |=3D DETECT_4_WIRE_MODE | AUTO_MEASURE; + basic_setting |=3D FIELD_PREP(MEASURE_DELAY_TIME_MASK, + tsc->measure_delay_time); + basic_setting |=3D AUTO_MEASURE; writel(basic_setting, tsc->tsc_regs + REG_TSC_BASIC_SETTING); =20 - writel(DE_GLITCH_2, tsc->tsc_regs + REG_TSC_DEBUG_MODE2); + debug_mode2 =3D FIELD_PREP(DE_GLITCH_MASK, DE_GLITCH_2); + writel(debug_mode2, tsc->tsc_regs + REG_TSC_DEBUG_MODE2); =20 writel(tsc->pre_charge_time, tsc->tsc_regs + REG_TSC_PRE_CHARGE_TIME); writel(MEASURE_INT_EN, tsc->tsc_regs + REG_TSC_INT_EN); @@ -250,7 +262,7 @@ static bool tsc_wait_detect_mode(struct imx6ul_tsc *tsc) =20 usleep_range(200, 400); debug_mode2 =3D readl(tsc->tsc_regs + REG_TSC_DEBUG_MODE2); - state_machine =3D (debug_mode2 >> 20) & 0x7; + state_machine =3D FIELD_GET(STATE_MACHINE_MASK, debug_mode2); } while (state_machine !=3D DETECT_MODE); =20 usleep_range(200, 400); @@ -278,8 +290,8 @@ static irqreturn_t tsc_irq_fn(int irq, void *dev_id) =20 if (status & MEASURE_SIGNAL) { value =3D readl(tsc->tsc_regs + REG_TSC_MEASURE_VALUE); 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([2.196.40.230]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45f32640f49sm530985e9.9.2025.09.15.12.53.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Sep 2025 12:53:54 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Frank Li , linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Dmitry Torokhov , Javier Carrasco , Jeff LaBundy , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-input@vger.kernel.org Subject: [PATCH v3 3/6] dt-bindings: touchscreen: add touchscreen-glitch-threshold-ns property Date: Mon, 15 Sep 2025 21:53:05 +0200 Message-ID: <20250915195335.1710780-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250915195335.1710780-1-dario.binacchi@amarulasolutions.com> References: <20250915195335.1710780-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for glitch threshold configuration. A detected signal is valid only if it lasts longer than the set threshold; otherwise, it is regarded as a glitch. Signed-off-by: Dario Binacchi --- (no changes since v2) Changes in v2: - Added in v2. .../devicetree/bindings/input/touchscreen/touchscreen.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/input/touchscreen/touchscree= n.yaml b/Documentation/devicetree/bindings/input/touchscreen/touchscreen.ya= ml index 3e3572aa483a..a60b4d08620d 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/touchscreen.yaml +++ b/Documentation/devicetree/bindings/input/touchscreen/touchscreen.yaml @@ -206,6 +206,10 @@ properties: =20 unevaluatedProperties: false =20 + touchscreen-glitch-threshold-ns: + description: Minimum duration in nanoseconds a signal must remain stab= le + to be considered valid. + dependencies: touchscreen-size-x: [ touchscreen-size-y ] touchscreen-size-y: [ touchscreen-size-x ] --=20 2.43.0 From nobody Thu Oct 2 14:27:55 2025 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A8F9328CF5E for ; Mon, 15 Sep 2025 19:53:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757966040; cv=none; b=fCpWRHV8vZ4ahLZKbMfRWZdxHsVNasDNLOUGbYQ+dzifNUMFDps6UUUjh+IsH60pHT6s2BqL+rTbWaIlBSTuZzxhuSv2ccT29IvnhTXnbyYStZq7QAq80cSb5J+f2WhWv2i7ekFM8LUOMVOUodHVtDDvHD5HamSTXfe2dmygZYc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757966040; c=relaxed/simple; bh=jH9/bubhcWhRpYTPmVEynThTP5AYOEziuVsPlmZV1kU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZtnzjcfUpuR4FJaLXyIx4oZ6HTGsdWHmRIaQ2AUqtKucmRRBXgxmdHfosO9EKaoSRcazhHZWFGH6gZEQLoR8MATYvfXod8+KV4UhCYZ6ee1cNkcQKqDNNkNxXQuJ/TskLSbrc1Fl4+BgmD1mfuEoCN9sjKdHjVq0MWcS/H2UeLY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=RFtNbGWU; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="RFtNbGWU" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-45f2fa8a1adso9238245e9.1 for ; Mon, 15 Sep 2025 12:53:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1757966037; x=1758570837; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JYpBInbhYba1I5IFzkBXif3pXoZfr9uL09LB08J1+iU=; b=RFtNbGWUsyQeOfrVcRCSlKAFl+Ipz6TYVd7rh8UOCcEnvnpICMOdS+Ejd/bnfPDK4L BrRHDYMVQWkldkgrn7DMVRgkGClx6S5yuM/EB03BWSJ4sfMEPKN9KW72otV/a3+SVL26 RVazHba3veFmYefqg8e20jjlRr8q9BDL1BShg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757966037; x=1758570837; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JYpBInbhYba1I5IFzkBXif3pXoZfr9uL09LB08J1+iU=; b=R5B2E66h4w6Gja/3ErhN/ck6rE+OkicP/34tqUVSIBWEdPuRdTTga/i73deRtJ9AVo SRCXpU766JbAi9l56Zhbzmkvip/GIqs56E7DXFFgZqFJJ/W1eaBeq780zCvQ8G3CwZ5k w31VK2QI3jhJbmDZ6WMy+MG6h+1YYkChg6zafi5oviGMoQAK755syC2BUn9vOP97lwtk /tclkGfKiYUp+UmsJMrE3snEOV/kE0/a0hYKV2E3M8RjrnKdvtkZT3kflsfd6O/xvLwQ RwpG2h0T0kNfItfjzQHeHZvr0BDfSMATrV5u8FHChOwVhdSQliCUGu8yL2SqoDNvFZOG iLKg== X-Gm-Message-State: AOJu0YxDHDL9Ba7Y3bmcdN4fgO+j9OhyIpUl9JvR5MkneuKJD/qUi2Wh VW9euQqGQj0KLINcPLmSZ4YV2tftJRh2TOQNnk+p7pyZTJkdALidm7wru9m0MA0aCqAZgo5yDh8 Ljl/Y X-Gm-Gg: ASbGnctSyuInz8+shYBeZCcAnG4gZGdA8epYUbyM+gp3oipNMhU8wEF/M76iJnECIST cldy7xM+Dzap8GnH/Q/+9eSCd1h0T5aji1IuEiTgKlAr5an8CGH7Rs3Pd44F00i8irPuRGIf5fp ZS54bsYHilC5hROCIdSXiTnN8mypHZMQP3oHkK2fI/pFtTSltGQlQRN+V5OmEjePd3XiZgf7pGs pnhxSMQl3rtn4COpUXvS3w+qom5ooiem81J2sMWmhWYDXZ0V8RCy1gdg39fe5QxuiBC6L/PSLIP antLXdmVQUdNd+5MaZJC5C7kgJg2PCV1Za6a+DAMvPlNxnlaGUmld1rJ/xnQU0ZUGnMg3ue4rfN 5KQEeEnY/OUhBhhgSsJY7WBR9qWuL5AXA1GRQ1Tnp0H07bTrh3TTnctFWORHlzMA= X-Google-Smtp-Source: AGHT+IGia0IZ0pDiz5Yw5I2pPYwxxrez1ql7kM6HUI8y8toQ7q5lIloMT59fhRpk+Z7OXMtwBgr0pQ== X-Received: by 2002:a05:600c:c8d:b0:458:b8b0:6338 with SMTP id 5b1f17b1804b1-45f24060698mr116466355e9.6.1757966036748; Mon, 15 Sep 2025 12:53:56 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.40.230]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45f32640f49sm530985e9.9.2025.09.15.12.53.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Sep 2025 12:53:56 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Frank Li , linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Dmitry Torokhov , Fabio Estevam , Haibo Chen , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org Subject: [PATCH v3 4/6] dt-bindings: touchscreen: fsl,imx6ul-tsc: support glitch thresold Date: Mon, 15 Sep 2025 21:53:06 +0200 Message-ID: <20250915195335.1710780-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250915195335.1710780-1-dario.binacchi@amarulasolutions.com> References: <20250915195335.1710780-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support the touchscreen-glitch-threshold-ns property. Unlike the generic description in touchscreen.yaml, this controller maps the provided value to one of four discrete thresholds internally. Signed-off-by: Dario Binacchi --- Changes in v3: - Remove the final part of the description that refers to implementation details. .../bindings/input/touchscreen/fsl,imx6ul-tsc.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/input/touchscreen/fsl,imx6ul= -tsc.yaml b/Documentation/devicetree/bindings/input/touchscreen/fsl,imx6ul-= tsc.yaml index 678756ad0f92..6214d8be5a99 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/fsl,imx6ul-tsc.ya= ml +++ b/Documentation/devicetree/bindings/input/touchscreen/fsl,imx6ul-tsc.ya= ml @@ -62,6 +62,18 @@ properties: description: Number of data samples which are averaged for each read. enum: [ 1, 4, 8, 16, 32 ] =20 + touchscreen-glitch-threshold-ns: + description: | + Unlike the generic property defined in touchscreen.yaml, this + controller does not allow arbitrary values. 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([2.196.40.230]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45f32640f49sm530985e9.9.2025.09.15.12.53.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Sep 2025 12:53:57 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Frank Li , linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 5/6] ARM: dts: imx6ull-engicam-microgea-bmm: set touchscreen glitch threshold Date: Mon, 15 Sep 2025 21:53:07 +0200 Message-ID: <20250915195335.1710780-6-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250915195335.1710780-1-dario.binacchi@amarulasolutions.com> References: <20250915195335.1710780-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable This way the detected signal is valid only if it lasts longer than 62 =C2=B5s, otherwise it is not sampled. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dts b/a= rch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dts index 279d46c22cd7..f12084d8f2a0 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dts @@ -154,6 +154,7 @@ &tsc { pinctrl-0 =3D <&pinctrl_tsc>; measure-delay-time =3D <0x9ffff>; pre-charge-time =3D <0xfff>; + touchscreen-glitch-threshold-ns =3D <62000>; xnur-gpios =3D <&gpio1 3 GPIO_ACTIVE_LOW>; status =3D "okay"; }; --=20 2.43.0 From nobody Thu Oct 2 14:27:55 2025 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71660296BB6 for ; Mon, 15 Sep 2025 19:54:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757966043; cv=none; b=MGXg3fmfis/+rdwsH/q4L58TPVZINWgnORRTjvZmKM1Mvc+H9zb/kXjJjmi1vvhsUEEfLPKZA8fGroEQjX+CHuFLykVSX2ADE5X5ave8rkKulJqVij/BLgio22Nei1CfXFjC+xD/3461kIGHY4XQM5gcOiixOrGOyWJjJO/y0FU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757966043; c=relaxed/simple; bh=PWtJQS5FRtbC8eI744kro5v4M7mGct2HyyMhtJCrfWU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qISKSRbtTpjHIcoFtiBu/178kev7xrzRKMWENkznQdWl9ulQWuRzxO2wdsGL4SS4T2K84rPGAjlNb+5sj1VUkGcP/1Fgn45SCT15dqn4oepcS7khTaB5GTDWLFQsZI+iQkjZYw6SaNAq+S1Bj2AXvlEr8WdeYxpXxqr7wLVc+D8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=V5OjWZA2; arc=none smtp.client-ip=209.85.128.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="V5OjWZA2" Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-45df0cde41bso35025445e9.3 for ; Mon, 15 Sep 2025 12:54:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1757966040; x=1758570840; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GqadXdSW1D0YdX9y/VYCHcP9OLLjsnrvbDdXfqIeuyU=; b=V5OjWZA2EfnAjk6lKiE+LI4av9Me0F8ymleG3geNbxfU0QeO0usKIM2Zy8l0UTedw0 rFz7L1y84WFQK4nuMEqLnOspYDKXubwBaINLonkTykMQqT31TN9zF95U33y7c3p/b/7a DB4EWDUU4z43UDGpgGsqlA+M8XAtQpCOIe3RQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757966040; x=1758570840; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GqadXdSW1D0YdX9y/VYCHcP9OLLjsnrvbDdXfqIeuyU=; b=DxqbK/IaPOpZNiS06a4G52ufIkaBRQNOsNfzkLymKSBHRh61+VWxj2KWZT7IFpck+u 4TN/eHugf3uDNuDCAfuqFXP/Rbsna4bD8jh4XHOIkK9mcFgtS4I9hkyEoxbb6UQTzbjX /uik1X2jdN3M9eDDIyDj8opJQzYKQzZr0TZ6LPgMM/PWKRHNaLJ87soXDRufV7v+yMNA +FoIP4lwplHt/Lb/Ut6+WspKZUsyOEg72+OuJ0nG1C0CIjU146AVXfDMS+XS1xR7Yw/u rbbM1YQS7rKQa5sLzELzGaCFA2JMD+EwXRj/R7eqfPCSa2ZBAZdYmvKOj5t0GjmY7D02 XSrA== X-Gm-Message-State: AOJu0YyaRhjY2EPZnp5FKRiuoEES2PCTOK58Ekae1GDdr27vsIniiAKm PRJr8mvxvZmqGcLv9Ot+qWdReRztuX+XASobkt013GOMwJMo1VdxTXHdfCacPNX7+tqhnPloq/3 ZXwlU X-Gm-Gg: ASbGnctZU26hyJ5NDNvpIYUD34RBxrvseYM6Rsg7/Keuw9Y6beLxxgvszWp9hUyxWMZ hHgBoFzGHpqHh47IcE4QKLp28Gq4Dy4am8EgoGWn3QpsiKGy/FUh1xIAgQnD/D8Ij7ctbmLGAbN KBMkPDvrWCEbOYPxpMoCCGuUh6mE3iFnw0YIIlq4ecdkbmhwBqfErJ+7parR/QbUs/bgqQdWye/ psXRSbcI0+9CR6GI5j7TSpvyDtK0nOPXs6LAv7gC03dESTYqFjozA34ltxc2p5jrSy3qLj4za9b CnnnmQy9Lsk6HZrAZJCKUSCfq6BID0IO9/sXvAjgSj01OggC70xNBT8btUN4n4ba/a6P48BwFsv 36CLlU12BpZKg/yJwup2VVWm3ED6h/6hItLG0p8Yq27eGt+8qx/wWK+AgBFnj1pI= X-Google-Smtp-Source: AGHT+IFX174NiBczGaK/x3CIfQpHj6Pi6AzSfzk1fSmasGkNMFC1MAnI/pPMBLk/mLUpvLPRyiHwCA== X-Received: by 2002:a05:600c:4453:b0:459:dde3:1a55 with SMTP id 5b1f17b1804b1-45f211f2fbemr160469475e9.24.1757966039580; Mon, 15 Sep 2025 12:53:59 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.. ([2.196.40.230]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45f32640f49sm530985e9.9.2025.09.15.12.53.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Sep 2025 12:53:59 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Frank Li , linux-amarula@amarulasolutions.com, Dario Binacchi , Dmitry Torokhov , Fabio Estevam , Michael Trimarchi , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org Subject: [PATCH v3 6/6] Input: imx6ul_tsc - set glitch threshold by DTS property Date: Mon, 15 Sep 2025 21:53:08 +0200 Message-ID: <20250915195335.1710780-7-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250915195335.1710780-1-dario.binacchi@amarulasolutions.com> References: <20250915195335.1710780-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Set the glitch threshold previously hardcoded in the driver. The change is backward compatible. Signed-off-by: Dario Binacchi --- Changes in v3: - Remove the final part of the description that refers to implementation details in fsl,imx6ul-tsc.yaml. Changes in v2: - Replace patch ("dt-bindings: input: touchscreen: fsl,imx6ul-tsc: add fsl,glitch-threshold") with ("dt-bindings: touchscreen: add touchscreen-glitch-threshold-ns property"), making the previous property general by moving it to touchscreen.yaml. - Rework "Input: imx6ul_tsc - set glitch threshold by DTS property" patch to match changes made to the DTS property. - Move "Input: imx6ul_tsc - use BIT, FIELD_{GET,PREP} and GENMASK macros" patch right after the patch fixing the typo. - Rework to match changes made to the DTS property. drivers/input/touchscreen/imx6ul_tsc.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/input/touchscreen/imx6ul_tsc.c b/drivers/input/touchsc= reen/imx6ul_tsc.c index e2c59cc7c82c..0d753aa05fbf 100644 --- a/drivers/input/touchscreen/imx6ul_tsc.c +++ b/drivers/input/touchscreen/imx6ul_tsc.c @@ -79,7 +79,7 @@ #define MEASURE_SIG_EN BIT(0) #define VALID_SIG_EN BIT(8) #define DE_GLITCH_MASK GENMASK(30, 29) -#define DE_GLITCH_2 0x02 +#define DE_GLITCH_DEF 0x02 #define START_SENSE BIT(12) #define TSC_DISABLE BIT(16) #define DETECT_MODE 0x2 @@ -98,6 +98,7 @@ struct imx6ul_tsc { u32 pre_charge_time; bool average_enable; u32 average_select; + u32 de_glitch; =20 struct completion completion; }; @@ -205,7 +206,7 @@ static void imx6ul_tsc_set(struct imx6ul_tsc *tsc) basic_setting |=3D AUTO_MEASURE; writel(basic_setting, tsc->tsc_regs + REG_TSC_BASIC_SETTING); =20 - debug_mode2 =3D FIELD_PREP(DE_GLITCH_MASK, DE_GLITCH_2); + debug_mode2 =3D FIELD_PREP(DE_GLITCH_MASK, tsc->de_glitch); writel(debug_mode2, tsc->tsc_regs + REG_TSC_DEBUG_MODE2); =20 writel(tsc->pre_charge_time, tsc->tsc_regs + REG_TSC_PRE_CHARGE_TIME); @@ -391,6 +392,7 @@ static int imx6ul_tsc_probe(struct platform_device *pde= v) int tsc_irq; int adc_irq; u32 average_samples; + u32 de_glitch; =20 tsc =3D devm_kzalloc(&pdev->dev, sizeof(*tsc), GFP_KERNEL); if (!tsc) @@ -513,6 +515,26 @@ static int imx6ul_tsc_probe(struct platform_device *pd= ev) return -EINVAL; } =20 + err =3D of_property_read_u32(np, "touchscreen-glitch-threshold-ns", + &de_glitch); + if (err) { + tsc->de_glitch =3D DE_GLITCH_DEF; + } else { + u64 cycles; + unsigned long rate =3D clk_get_rate(tsc->tsc_clk); + + cycles =3D DIV64_U64_ROUND_UP((u64)de_glitch * rate, NSEC_PER_SEC); + + if (cycles <=3D 0x3ff) + tsc->de_glitch =3D 3; + else if (cycles <=3D 0x7ff) + tsc->de_glitch =3D 2; + else if (cycles <=3D 0xfff) + tsc->de_glitch =3D 1; + else + tsc->de_glitch =3D 0; + } + err =3D input_register_device(tsc->input); if (err) { dev_err(&pdev->dev, --=20 2.43.0