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[86.139.30.37]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e8f4d644adsm9521728f8f.52.2025.09.15.09.36.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Sep 2025 09:36:40 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Biju Das , linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v3 1/2] pwm: rzg2l-gpt: Reinitialize cache value Date: Mon, 15 Sep 2025 17:36:30 +0100 Message-ID: <20250915163637.3572-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250915163637.3572-1-biju.das.jz@bp.renesas.com> References: <20250915163637.3572-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Reinitialize the cache value to 0 during disable(). Fixes: 061f087f5d0b ("pwm: Add support for RZ/G2L GPT") Signed-off-by: Biju Das --- v3: * New patch. --- drivers/pwm/pwm-rzg2l-gpt.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index 360c8bf3b190..b2452e50d618 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -190,8 +190,10 @@ static void rzg2l_gpt_disable(struct rzg2l_gpt_chip *r= zg2l_gpt, /* Stop count, Output low on GTIOCx pin when counting stops */ rzg2l_gpt->channel_enable_count[ch]--; =20 - if (!rzg2l_gpt->channel_enable_count[ch]) + if (!rzg2l_gpt->channel_enable_count[ch]) { rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), RZG2L_GTCR_CST, 0); + rzg2l_gpt->period_ticks[ch] =3D 0; + } =20 /* Disable pin output */ rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTIOR(ch), RZG2L_GTIOR_OxE(sub_ch), 0); --=20 2.43.0 From nobody Thu Oct 2 14:26:16 2025 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA8C9279359 for ; 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[86.139.30.37]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e8f4d644adsm9521728f8f.52.2025.09.15.09.36.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Sep 2025 09:36:40 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: Biju Das , linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH v3 2/2] pwm: rzg2l-gpt: Implementation of the waveform callbacks Date: Mon, 15 Sep 2025 17:36:31 +0100 Message-ID: <20250915163637.3572-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250915163637.3572-1-biju.das.jz@bp.renesas.com> References: <20250915163637.3572-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Convert the rzg2l-gpt driver to use the new callbacks for hardware programming. Signed-off-by: Biju Das --- v2->v3: * Created separate patch for fix for reinitialization of the cache variable in disable(). * .round_waveform_tohw() do not fail if the requested period is too small but use the smallest possible value. * Added lock in rzg2l_gpt_read_waveform(). * wfhw is reinitialized in rzg2l_gpt_read_waveform if channel is disabled * Optimizated rzg2l_gpt_is_ch_enabled() to avoid redundant reads to=20 RZG2L_GTCR(ch). * .write_waveform() returns error incase of invalid period for second channel. v1->v2: * Dropped modifing hardware from .round_waveform_tohw() callback. --- drivers/pwm/pwm-rzg2l-gpt.c | 193 ++++++++++++++++++++++-------------- 1 file changed, 118 insertions(+), 75 deletions(-) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index b2452e50d618..392bd129574b 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -86,6 +86,13 @@ struct rzg2l_gpt_chip { u32 channel_enable_count[RZG2L_MAX_HW_CHANNELS]; }; =20 +/* This represents a hardware configuration for one channel */ +struct rzg2l_gpt_waveform { + u32 gtpr; + u32 gtccr; + u8 prescale; +}; + static inline struct rzg2l_gpt_chip *to_rzg2l_gpt_chip(struct pwm_chip *ch= ip) { return pwmchip_get_drvdata(chip); @@ -148,7 +155,7 @@ static void rzg2l_gpt_free(struct pwm_chip *chip, struc= t pwm_device *pwm) rzg2l_gpt->channel_request_count[ch]--; } =20 -static bool rzg2l_gpt_is_ch_enabled(struct rzg2l_gpt_chip *rzg2l_gpt, u8 h= wpwm) +static bool rzg2l_gpt_is_ch_enabled(struct rzg2l_gpt_chip *rzg2l_gpt, u8 h= wpwm, u32 *gtcr) { u8 ch =3D RZG2L_GET_CH(hwpwm); u32 val; @@ -157,6 +164,9 @@ static bool rzg2l_gpt_is_ch_enabled(struct rzg2l_gpt_ch= ip *rzg2l_gpt, u8 hwpwm) if (!(val & RZG2L_GTCR_CST)) return false; =20 + if (gtcr) + *gtcr =3D val; + val =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTIOR(ch)); =20 return val & RZG2L_GTIOR_OxE(rzg2l_gpt_subchannel(hwpwm)); @@ -217,54 +227,38 @@ static u64 rzg2l_gpt_calculate_period_or_duty(struct = rzg2l_gpt_chip *rzg2l_gpt, return DIV64_U64_ROUND_UP(tmp, rzg2l_gpt->rate_khz); } =20 -static int rzg2l_gpt_get_state(struct pwm_chip *chip, struct pwm_device *p= wm, - struct pwm_state *state) -{ - struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); - - state->enabled =3D rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm); - if (state->enabled) { - u32 sub_ch =3D rzg2l_gpt_subchannel(pwm->hwpwm); - u32 ch =3D RZG2L_GET_CH(pwm->hwpwm); - u8 prescale; - u32 val; - - val =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCR(ch)); - prescale =3D FIELD_GET(RZG2L_GTCR_TPCS, val); - - val =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTPR(ch)); - state->period =3D rzg2l_gpt_calculate_period_or_duty(rzg2l_gpt, val, pre= scale); - - val =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch)); - state->duty_cycle =3D rzg2l_gpt_calculate_period_or_duty(rzg2l_gpt, val,= prescale); - if (state->duty_cycle > state->period) - state->duty_cycle =3D state->period; - } - - state->polarity =3D PWM_POLARITY_NORMAL; - - return 0; -} - static u32 rzg2l_gpt_calculate_pv_or_dc(u64 period_or_duty_cycle, u8 presc= ale) { return min_t(u64, DIV_ROUND_DOWN_ULL(period_or_duty_cycle, 1 << (2 * pres= cale)), U32_MAX); } =20 -/* Caller holds the lock while calling rzg2l_gpt_config() */ -static int rzg2l_gpt_config(struct pwm_chip *chip, struct pwm_device *pwm, - const struct pwm_state *state) +static int rzg2l_gpt_round_waveform_tohw(struct pwm_chip *chip, + struct pwm_device *pwm, + const struct pwm_waveform *wf, + void *_wfhw) + { struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); - u8 sub_ch =3D rzg2l_gpt_subchannel(pwm->hwpwm); + struct rzg2l_gpt_waveform *wfhw =3D _wfhw; + bool is_small_second_period =3D false; u8 ch =3D RZG2L_GET_CH(pwm->hwpwm); u64 period_ticks, duty_ticks; unsigned long pv, dc; - u8 prescale; + + guard(mutex)(&rzg2l_gpt->lock); + if (wf->period_length_ns =3D=3D 0) { + *wfhw =3D (struct rzg2l_gpt_waveform){ + .gtpr =3D 0, + .gtccr =3D 0, + .prescale =3D 0, + }; + + return 0; + } =20 /* Limit period/duty cycle to max value supported by the HW */ - period_ticks =3D mul_u64_u64_div_u64(state->period, rzg2l_gpt->rate_khz, = USEC_PER_SEC); + period_ticks =3D mul_u64_u64_div_u64(wf->period_length_ns, rzg2l_gpt->rat= e_khz, USEC_PER_SEC); if (period_ticks > RZG2L_MAX_TICKS) period_ticks =3D RZG2L_MAX_TICKS; /* @@ -274,18 +268,22 @@ static int rzg2l_gpt_config(struct pwm_chip *chip, st= ruct pwm_device *pwm, */ if (rzg2l_gpt->channel_request_count[ch] > 1) { if (period_ticks < rzg2l_gpt->period_ticks[ch]) - return -EBUSY; - else - period_ticks =3D rzg2l_gpt->period_ticks[ch]; + is_small_second_period =3D true; + + period_ticks =3D rzg2l_gpt->period_ticks[ch]; } =20 - prescale =3D rzg2l_gpt_calculate_prescale(rzg2l_gpt, period_ticks); - pv =3D rzg2l_gpt_calculate_pv_or_dc(period_ticks, prescale); + wfhw->prescale =3D rzg2l_gpt_calculate_prescale(rzg2l_gpt, period_ticks); + pv =3D rzg2l_gpt_calculate_pv_or_dc(period_ticks, wfhw->prescale); + wfhw->gtpr =3D pv; + if (is_small_second_period) + return 1; =20 - duty_ticks =3D mul_u64_u64_div_u64(state->duty_cycle, rzg2l_gpt->rate_khz= , USEC_PER_SEC); + duty_ticks =3D mul_u64_u64_div_u64(wf->duty_length_ns, rzg2l_gpt->rate_kh= z, USEC_PER_SEC); if (duty_ticks > period_ticks) duty_ticks =3D period_ticks; - dc =3D rzg2l_gpt_calculate_pv_or_dc(duty_ticks, prescale); + dc =3D rzg2l_gpt_calculate_pv_or_dc(duty_ticks, wfhw->prescale); + wfhw->gtccr =3D dc; =20 /* * GPT counter is shared by multiple channels, we cache the period ticks @@ -294,6 +292,61 @@ static int rzg2l_gpt_config(struct pwm_chip *chip, str= uct pwm_device *pwm, */ rzg2l_gpt->period_ticks[ch] =3D period_ticks; =20 + return 0; +} + +static int rzg2l_gpt_round_waveform_fromhw(struct pwm_chip *chip, + struct pwm_device *pwm, + const void *_wfhw, + struct pwm_waveform *wf) +{ + struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); + const struct rzg2l_gpt_waveform *wfhw =3D _wfhw; + + wf->period_length_ns =3D rzg2l_gpt_calculate_period_or_duty(rzg2l_gpt, wf= hw->gtpr, + wfhw->prescale); + wf->duty_length_ns =3D rzg2l_gpt_calculate_period_or_duty(rzg2l_gpt, wfhw= ->gtccr, + wfhw->prescale); + wf->duty_offset_ns =3D 0; + + return 0; +} + +static int rzg2l_gpt_read_waveform(struct pwm_chip *chip, + struct pwm_device *pwm, + void *_wfhw) +{ + struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); + struct rzg2l_gpt_waveform *wfhw =3D _wfhw; + u32 sub_ch =3D rzg2l_gpt_subchannel(pwm->hwpwm); + u32 ch =3D RZG2L_GET_CH(pwm->hwpwm); + u32 gtcr; + + guard(mutex)(&rzg2l_gpt->lock); + if (rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm, >cr)) { + wfhw->prescale =3D FIELD_GET(RZG2L_GTCR_TPCS, gtcr); + wfhw->gtpr =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTPR(ch)); + wfhw->gtccr =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch)); + if (wfhw->gtccr > wfhw->gtpr) + wfhw->gtccr =3D wfhw->gtpr; + } else { + *wfhw =3D (struct rzg2l_gpt_waveform) { }; + } + + return 0; +} + +static int rzg2l_gpt_write_waveform(struct pwm_chip *chip, + struct pwm_device *pwm, + const void *_wfhw) +{ + struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); + const struct rzg2l_gpt_waveform *wfhw =3D _wfhw; + u8 sub_ch =3D rzg2l_gpt_subchannel(pwm->hwpwm); + u8 ch =3D RZG2L_GET_CH(pwm->hwpwm); + u32 gptr; + + guard(mutex)(&rzg2l_gpt->lock); /* * Counter must be stopped before modifying mode, prescaler, timer * counter and buffer enable registers. These registers are shared @@ -312,14 +365,20 @@ static int rzg2l_gpt_config(struct pwm_chip *chip, st= ruct pwm_device *pwm, =20 /* Select count clock */ rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), RZG2L_GTCR_TPCS, - FIELD_PREP(RZG2L_GTCR_TPCS, prescale)); + FIELD_PREP(RZG2L_GTCR_TPCS, wfhw->prescale)); =20 /* Set period */ - rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTPR(ch), pv); + rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTPR(ch), wfhw->gtpr); + } else { + if (wfhw->gtpr) { + gptr =3D rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTPR(ch)); + if (wfhw->gtpr < gptr) + return -EBUSY; + } } =20 /* Set duty cycle */ - rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch), dc); + rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch), wfhw->gtccr); =20 if (rzg2l_gpt->channel_enable_count[ch] <=3D 1) { /* Set initial value for counter */ @@ -328,44 +387,28 @@ static int rzg2l_gpt_config(struct pwm_chip *chip, st= ruct pwm_device *pwm, /* Set no buffer operation */ rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTBER(ch), 0); =20 - /* Restart the counter after updating the registers */ - rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), - RZG2L_GTCR_CST, RZG2L_GTCR_CST); - } - - return 0; -} - -static int rzg2l_gpt_apply(struct pwm_chip *chip, struct pwm_device *pwm, - const struct pwm_state *state) -{ - struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); - bool enabled =3D pwm->state.enabled; - int ret; - - if (state->polarity !=3D PWM_POLARITY_NORMAL) - return -EINVAL; - - guard(mutex)(&rzg2l_gpt->lock); - if (!state->enabled) { - if (enabled) - rzg2l_gpt_disable(rzg2l_gpt, pwm); - - return 0; + if (wfhw->gtpr) + /* Restart the counter after updating the registers */ + rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), + RZG2L_GTCR_CST, RZG2L_GTCR_CST); } =20 - ret =3D rzg2l_gpt_config(chip, pwm, state); - if (!ret && !enabled) + if (wfhw->gtpr && !rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm, NULL)) rzg2l_gpt_enable(rzg2l_gpt, pwm); + else if (!wfhw->gtpr && rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm, NU= LL)) + rzg2l_gpt_disable(rzg2l_gpt, pwm); =20 - return ret; + return 0; } =20 static const struct pwm_ops rzg2l_gpt_ops =3D { .request =3D rzg2l_gpt_request, .free =3D rzg2l_gpt_free, - .get_state =3D rzg2l_gpt_get_state, - .apply =3D rzg2l_gpt_apply, + .sizeof_wfhw =3D sizeof(struct rzg2l_gpt_waveform), + .round_waveform_tohw =3D rzg2l_gpt_round_waveform_tohw, + .round_waveform_fromhw =3D rzg2l_gpt_round_waveform_fromhw, + .read_waveform =3D rzg2l_gpt_read_waveform, + .write_waveform =3D rzg2l_gpt_write_waveform, }; =20 static int rzg2l_gpt_probe(struct platform_device *pdev) --=20 2.43.0