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Mon, 15 Sep 2025 09:28:57 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGGcqLg89RzAzIylVbUAdhxQnrbuII6q9BMD4UeHPPpyAnAih60GUdiWlXGIqVqjdTWEN3ljw== X-Received: by 2002:a05:600c:1d22:b0:45f:2bc1:22d0 with SMTP id 5b1f17b1804b1-45f2c422f88mr52741475e9.33.1757953737422; Mon, 15 Sep 2025 09:28:57 -0700 (PDT) Received: from holism.lzampier.com ([2a06:5900:814a:ab00:c1c7:2e09:633d:e94e]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e7cde81491sm12840179f8f.42.2025.09.15.09.28.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Sep 2025 09:28:56 -0700 (PDT) From: Lucas Zampieri To: linux-kernel@vger.kernel.org Cc: Lucas Zampieri , Paul Walmsley , Samuel Holland , stable@vger.kernel.org, linux-riscv@lists.infradead.org, Thomas Gleixner , Jia Wang Subject: [PATCH] irqchip/sifive-plic: avoid interrupt ID 0 handling during suspend/resume Date: Mon, 15 Sep 2025 17:28:46 +0100 Message-ID: <20250915162847.103445-1-lzampier@redhat.com> X-Mailer: git-send-email 2.51.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To: linux-kernel@vger.kernel.org Cc: Paul Walmsley Cc: Samuel Holland Cc: stable@vger.kernel.org Cc: linux-riscv@lists.infradead.org Cc: Thomas Gleixner According to the PLIC specification[1], global interrupt sources are assigned small unsigned integer identifiers beginning at the value 1. An interrupt ID of 0 is reserved to mean "no interrupt". The current plic_irq_resume() and plic_irq_suspend() functions incorrectly starts the loop from index 0, which could access the reserved interrupt ID 0 register space. This fix changes the loop to start from index 1, skipping the reserved interrupt ID 0 as per the PLIC specification. This prevents potential undefined behavior when accessing the reserved register space during suspend/resume cycles. Fixes: e80f0b6a2cf3 ("irqchip/irq-sifive-plic: Add syscore callbacks for hi= bernation") Co-developed-by: Jia Wang Signed-off-by: Jia Wang Signed-off-by: Lucas Zampieri [1] https://github.com/riscv/riscv-plic-spec/releases/tag/1.0.0 --- drivers/irqchip/irq-sifive-plic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive= -plic.c index bf69a4802b71..1c2b4d2575ac 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -252,7 +252,7 @@ static int plic_irq_suspend(void) =20 priv =3D per_cpu_ptr(&plic_handlers, smp_processor_id())->priv; =20 - for (i =3D 0; i < priv->nr_irqs; i++) { + for (i =3D 1; i < priv->nr_irqs; i++) { __assign_bit(i, priv->prio_save, readl(priv->regs + PRIORITY_BASE + i * PRIORITY_PER_ID)); } @@ -283,7 +283,7 @@ static void plic_irq_resume(void) =20 priv =3D per_cpu_ptr(&plic_handlers, smp_processor_id())->priv; =20 - for (i =3D 0; i < priv->nr_irqs; i++) { + for (i =3D 1; i < priv->nr_irqs; i++) { index =3D BIT_WORD(i); writel((priv->prio_save[index] & BIT_MASK(i)) ? 1 : 0, priv->regs + PRIORITY_BASE + i * PRIORITY_PER_ID); --=20 2.51.0