From nobody Thu Oct 2 15:35:41 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 90B8634A30F; Mon, 15 Sep 2025 15:21:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757949696; cv=none; b=vF5g/at5aCVMiR96yXkq3VYChUSyCXU7jkPb+2PKDcl2OWKnMEn/S9MGiOFfCj6LroDo6E/XWRWJ7ivZ9NSwz7Bei6WMKUichcvv+cpChLiguy3ljZ0LVJpoNrhUQ+ncaSaVxkj8Ko2T1tJqP6hQWqlFppiVkVl2xcJt3l0gF+Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757949696; c=relaxed/simple; bh=/quwpo3Td+EOEF9Gi50+IzfkKTC4g4fSCb+/GxjyPG8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=CUl94mmoBQsy5ReVrdGHnprQqzO/xkyzRyHbmD4/OZRrqpYgdLoKgffGWw80uHUagkF2rCsl82KJNiRuDQHHPr4jSylSB6G180UzCgX6e31of/94mCVbc/TAffMcTlPjjiwuDFsOr3gvqy4iQDwHNx0YIVrKoM2ZcyumOhuYFHk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=Wlxrhv5T; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="Wlxrhv5T" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1757949693; bh=/quwpo3Td+EOEF9Gi50+IzfkKTC4g4fSCb+/GxjyPG8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Wlxrhv5TJ/yhFaAyi8jghgEbjAz38LTpaL99dsAhBQQ90FI9UsHbygerNclJWga+M jqFnXfb4ufivWjBB8NCh1/EdyNQDHKymiHrC694Rv8jB97x4kZ06Wml2k9cKe5k1CU qZzg4WZoMQggpAtD/fbbigsgSvXd/02BVyYcONlFdjkX/JL5mwpcDvEW7g0CMGc55E fNMPUIxy2MkBIBgMr0dGOkDpkwbtI2i8QDTd6VWJTHBoP3jQwQLVjXw1pXuyeAjBhe U5uy+yOEa4hMbuWUV4ZlxhOEwZH/BUOZtdhaNNXKxjQRGy68LvDnhUHB7adW0+OuuF DZFe6SPlaFjMw== Received: from laura.lan (unknown [IPv6:2001:b07:646b:e2:1c8d:f5ba:823d:730b]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laura.nao) by bali.collaboradmins.com (Postfix) with ESMTPSA id 4403E17E132A; Mon, 15 Sep 2025 17:21:32 +0200 (CEST) From: Laura Nao To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, richardcochran@gmail.com Cc: guangjie.song@mediatek.com, wenst@chromium.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, kernel@collabora.com, Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= Subject: [PATCH v6 08/27] clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro Date: Mon, 15 Sep 2025 17:19:28 +0200 Message-Id: <20250915151947.277983-9-laura.nao@collabora.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250915151947.277983-1-laura.nao@collabora.com> References: <20250915151947.277983-1-laura.nao@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On MT8196, some clocks use one register for parent selection and gating, and a separate register for frequency division. Since composite clocks can combine a mux, divider, and gate in a single entity, add a macro to simplify registration of such clocks by combining parent selection, frequency scaling, and enable control into one definition. Reviewed-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Signed-off-by: Laura Nao --- drivers/clk/mediatek/clk-mtk.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index c381d6a6d908..5417b9264e6d 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -175,6 +175,25 @@ struct mtk_composite { .flags =3D 0, \ } =20 +#define MUX_DIV_GATE(_id, _name, _parents, \ + _mux_reg, _mux_shift, _mux_width, \ + _div_reg, _div_shift, _div_width, \ + _gate_reg, _gate_shift) { \ + .id =3D _id, \ + .name =3D _name, \ + .parent_names =3D _parents, \ + .num_parents =3D ARRAY_SIZE(_parents), \ + .mux_reg =3D _mux_reg, \ + .mux_shift =3D _mux_shift, \ + .mux_width =3D _mux_width, \ + .divider_reg =3D _div_reg, \ + .divider_shift =3D _div_shift, \ + .divider_width =3D _div_width, \ + .gate_reg =3D _gate_reg, \ + .gate_shift =3D _gate_shift, \ + .flags =3D CLK_SET_RATE_PARENT, \ + } + int mtk_clk_register_composites(struct device *dev, const struct mtk_composite *mcs, int num, void __iomem *base, spinlock_t *lock, --=20 2.39.5