From nobody Thu Oct 2 15:34:57 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76FFF3376BC; Mon, 15 Sep 2025 15:21:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757949691; cv=none; b=BYv6mtdm22NSdMGTcLjZjqMHGKyuq6ksOgAod1Wg8blDEupuUD2sZ/TCSfD8oTwU39c3w/qtMdfDYfaGJoXiSA4ipWzdwE6UovSIn8SdI3hFqKmi++ouRl95ks28CjuCOyw19RQ97jDvn250W0RkBnwmh00h/KmhEMyimukLTdQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757949691; c=relaxed/simple; bh=XfcmfGHRmWdOlEuhQ9p5peLB10CoGZdkoIDy+k+bKXw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=s018+JUDd5WP2DXErOsr6WP29URTkBoMpubjyqqDSMLI7yeyBRfzAqCZ73zA1u1s4IFqSUXblmr+WitwKUxC3MIZk4ZB6DluQT47sruy7gi6yMEqKponHvjEN8/w+VWATasgvzrpVsVG6mMARvE3R10mgc5vk/d/f+HtQBlQ63E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=ik46wrf9; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="ik46wrf9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1757949687; bh=XfcmfGHRmWdOlEuhQ9p5peLB10CoGZdkoIDy+k+bKXw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ik46wrf9By+ENaD3+nlLA2NBJNrnjBB04j442V+i0B2mRK2SNuU5XmCI33WJfgl1t nwB1W/CLjWZMuWmk5ZSMOq2GBDwySSlWpsLEkpPDt5nJMaSB5xNPVRnmbvS4UwtPcn 21Yu07FEO9zMTuUvKykSSFl1yaQ8W1nTz/GQHh87PWAHSej3cGX48Pn4ct1M/0fp1Z LzUZubt/tR2JaTj10QsL83rRNDwOw+v85RbwqpS7gDE4Smxz7EATsb2HLnr5qLiP1l eThj81982O0Lgrf7OIemfwnn1JfGs13nNzSt1eCspTi13U5VnGzSm0AjmMvlUGZRIK uuSb3nXn4kiZg== Received: from laura.lan (unknown [IPv6:2001:b07:646b:e2:1c8d:f5ba:823d:730b]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laura.nao) by bali.collaboradmins.com (Postfix) with ESMTPSA id A43B117E1340; Mon, 15 Sep 2025 17:21:26 +0200 (CEST) From: Laura Nao To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, richardcochran@gmail.com Cc: guangjie.song@mediatek.com, wenst@chromium.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, kernel@collabora.com, Laura Nao , =?UTF-8?q?N=C3=ADcolas=20F=20=2E=20R=20=2E=20A=20=2E=20Prado?= Subject: [PATCH v6 03/27] clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd and FENC Date: Mon, 15 Sep 2025 17:19:23 +0200 Message-Id: <20250915151947.277983-4-laura.nao@collabora.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250915151947.277983-1-laura.nao@collabora.com> References: <20250915151947.277983-1-laura.nao@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MT8196 uses set/clr/upd registers for mux gate enable/disable control, along with a FENC bit to check the status. Add new set of mux gate clock operations with support for set/clr/upd and FENC status logic. Reviewed-by: N=C3=ADcolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Signed-off-by: Laura Nao --- drivers/clk/mediatek/clk-mux.c | 49 ++++++++++++++++++++++++++++++++++ drivers/clk/mediatek/clk-mux.h | 45 +++++++++++++++++++++++++++++++ 2 files changed, 94 insertions(+) diff --git a/drivers/clk/mediatek/clk-mux.c b/drivers/clk/mediatek/clk-mux.c index 60990296450b..3931d157b262 100644 --- a/drivers/clk/mediatek/clk-mux.c +++ b/drivers/clk/mediatek/clk-mux.c @@ -17,6 +17,8 @@ =20 #include "clk-mux.h" =20 +#define MTK_WAIT_FENC_DONE_US 30 + struct mtk_clk_mux { struct clk_hw hw; struct regmap *regmap; @@ -30,6 +32,33 @@ static inline struct mtk_clk_mux *to_mtk_clk_mux(struct = clk_hw *hw) return container_of(hw, struct mtk_clk_mux, hw); } =20 +static int mtk_clk_mux_fenc_enable_setclr(struct clk_hw *hw) +{ + struct mtk_clk_mux *mux =3D to_mtk_clk_mux(hw); + unsigned long flags; + u32 val; + int ret; + + if (mux->lock) + spin_lock_irqsave(mux->lock, flags); + else + __acquire(mux->lock); + + regmap_write(mux->regmap, mux->data->clr_ofs, + BIT(mux->data->gate_shift)); + + ret =3D regmap_read_poll_timeout_atomic(mux->regmap, mux->data->fenc_sta_= mon_ofs, + val, val & BIT(mux->data->fenc_shift), 1, + MTK_WAIT_FENC_DONE_US); + + if (mux->lock) + spin_unlock_irqrestore(mux->lock, flags); + else + __release(mux->lock); + + return ret; +} + static int mtk_clk_mux_enable_setclr(struct clk_hw *hw) { struct mtk_clk_mux *mux =3D to_mtk_clk_mux(hw); @@ -70,6 +99,16 @@ static void mtk_clk_mux_disable_setclr(struct clk_hw *hw) BIT(mux->data->gate_shift)); } =20 +static int mtk_clk_mux_fenc_is_enabled(struct clk_hw *hw) +{ + struct mtk_clk_mux *mux =3D to_mtk_clk_mux(hw); + u32 val; + + regmap_read(mux->regmap, mux->data->fenc_sta_mon_ofs, &val); + + return !!(val & BIT(mux->data->fenc_shift)); +} + static int mtk_clk_mux_is_enabled(struct clk_hw *hw) { struct mtk_clk_mux *mux =3D to_mtk_clk_mux(hw); @@ -168,6 +207,16 @@ const struct clk_ops mtk_mux_gate_clr_set_upd_ops =3D= { }; EXPORT_SYMBOL_GPL(mtk_mux_gate_clr_set_upd_ops); =20 +const struct clk_ops mtk_mux_gate_fenc_clr_set_upd_ops =3D { + .enable =3D mtk_clk_mux_fenc_enable_setclr, + .disable =3D mtk_clk_mux_disable_setclr, + .is_enabled =3D mtk_clk_mux_fenc_is_enabled, + .get_parent =3D mtk_clk_mux_get_parent, + .set_parent =3D mtk_clk_mux_set_parent_setclr_lock, + .determine_rate =3D mtk_clk_mux_determine_rate, +}; +EXPORT_SYMBOL_GPL(mtk_mux_gate_fenc_clr_set_upd_ops); + static struct clk_hw *mtk_clk_register_mux(struct device *dev, const struct mtk_mux *mux, struct regmap *regmap, diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h index 943ad1d7ce4b..a4fd17a18532 100644 --- a/drivers/clk/mediatek/clk-mux.h +++ b/drivers/clk/mediatek/clk-mux.h @@ -28,11 +28,13 @@ struct mtk_mux { u32 set_ofs; u32 clr_ofs; u32 upd_ofs; + u32 fenc_sta_mon_ofs; =20 u8 mux_shift; u8 mux_width; u8 gate_shift; s8 upd_shift; + u8 fenc_shift; =20 const struct clk_ops *ops; signed char num_parents; @@ -77,6 +79,7 @@ struct mtk_mux { =20 extern const struct clk_ops mtk_mux_clr_set_upd_ops; extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops; +extern const struct clk_ops mtk_mux_gate_fenc_clr_set_upd_ops; =20 #define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \ _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ @@ -118,6 +121,48 @@ extern const struct clk_ops mtk_mux_gate_clr_set_upd_o= ps; 0, _upd_ofs, _upd, CLK_SET_RATE_PARENT, \ mtk_mux_clr_set_upd_ops) =20 +#define MUX_GATE_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, _paridx, \ + _num_parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ + _shift, _width, _gate, _upd_ofs, _upd, \ + _fenc_sta_mon_ofs, _fenc, _flags) { \ + .id =3D _id, \ + .name =3D _name, \ + .mux_ofs =3D _mux_ofs, \ + .set_ofs =3D _mux_set_ofs, \ + .clr_ofs =3D _mux_clr_ofs, \ + .upd_ofs =3D _upd_ofs, \ + .fenc_sta_mon_ofs =3D _fenc_sta_mon_ofs, \ + .mux_shift =3D _shift, \ + .mux_width =3D _width, \ + .gate_shift =3D _gate, \ + .upd_shift =3D _upd, \ + .fenc_shift =3D _fenc, \ + .parent_names =3D _parents, \ + .parent_index =3D _paridx, \ + .num_parents =3D _num_parents, \ + .flags =3D _flags, \ + .ops =3D &mtk_mux_gate_fenc_clr_set_upd_ops, \ + } + +#define MUX_GATE_FENC_CLR_SET_UPD(_id, _name, _parents, \ + _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ + _shift, _width, _gate, _upd_ofs, _upd, \ + _fenc_sta_mon_ofs, _fenc) \ + MUX_GATE_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, \ + NULL, ARRAY_SIZE(_parents), _mux_ofs, \ + _mux_set_ofs, _mux_clr_ofs, _shift, \ + _width, _gate, _upd_ofs, _upd, \ + _fenc_sta_mon_ofs, _fenc, 0) + +#define MUX_GATE_FENC_CLR_SET_UPD_INDEXED(_id, _name, _parents, _paridx, \ + _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \ + _shift, _width, _gate, _upd_ofs, _upd, \ + _fenc_sta_mon_ofs, _fenc) \ + MUX_GATE_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, _paridx, \ + ARRAY_SIZE(_paridx), _mux_ofs, _mux_set_ofs, \ + _mux_clr_ofs, _shift, _width, _gate, _upd_ofs, _upd, \ + _fenc_sta_mon_ofs, _fenc, 0) + int mtk_clk_register_muxes(struct device *dev, const struct mtk_mux *muxes, int num, struct device_node *node, --=20 2.39.5