From nobody Thu Oct 2 15:35:40 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EBCB7352FD2; Mon, 15 Sep 2025 15:21:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757949704; cv=none; b=EC+zgW5yV/x/vug7veuM09b47Xu+wyrMh0KmZhUxafyDk2HKl/u6jKWY/YhJw7ZC8Dm0vI/3T8fla60K22miBJ4kHalIT0kfROO4UqEiCuYoSxoFKMrw+Rvz9Xky6cq+p/bb1XRaxj7dHS3WHmiwjSB2IkrptQEyafqB51/Ejtw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757949704; c=relaxed/simple; bh=jC75rB+Lke4gWl62vx9sxSQmr6S/cEz/wfc7oqd/dvA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=LUicH7Lbf7Xa4n9tzwKU2GWakba1iL/f++W8xDCvXJxCHJ2bRBoNgGwoqDjbv3aCT17CZFSvzRMF7BkfNN07ave7An5da9t678sugsNVvt/FCBKUWEEWTo/Fb/UV5q1cj76zEyYnwLVQqb4TYbeLeAFpucSzmnMqC/oAzD0H2yg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=n8O4VJWy; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="n8O4VJWy" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1757949700; bh=jC75rB+Lke4gWl62vx9sxSQmr6S/cEz/wfc7oqd/dvA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=n8O4VJWyADhlCFLuUtbM1C/XZpQFn1MaIVVsBuUFnXlGsspuIM3V7L2g7U7nn0g/x bJ1mduH4JWnJH3qoOxSNz5XVLCX+fNBFwdJU0x2ru4Zprf/ksc9cZBI1jzxccGthh1 diLmCYfCYIoU58kqDQbNWfSpOQqHgSgr8qX4CSApYdXUGv7yZSG963DLaovfCAXome 2R7eAtgN9QYq1lOsWdrBT9V4GE8H/6BKamlOSaBC2xowLhHwoEqi98STcQ1E5PTcO2 ZjuMS+kySi4q1x3J9vr721ILQPjIg2z3XZnP46sOujXDgMUk4fpCf4HEmbjxIFwotQ tycVMS/FuRmdg== Received: from laura.lan (unknown [IPv6:2001:b07:646b:e2:1c8d:f5ba:823d:730b]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laura.nao) by bali.collaboradmins.com (Postfix) with ESMTPSA id 5CDD417E1389; Mon, 15 Sep 2025 17:21:39 +0200 (CEST) From: Laura Nao To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, richardcochran@gmail.com Cc: guangjie.song@mediatek.com, wenst@chromium.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, kernel@collabora.com, Laura Nao Subject: [PATCH v6 14/27] clk: mediatek: Add MT8196 peripheral clock support Date: Mon, 15 Sep 2025 17:19:34 +0200 Message-Id: <20250915151947.277983-15-laura.nao@collabora.com> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250915151947.277983-1-laura.nao@collabora.com> References: <20250915151947.277983-1-laura.nao@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the MT8196 peripheral clock controller, which provides clock gate control for dma/flashif/msdc/pwm/spi/uart. Reviewed-by: Chen-Yu Tsai # CLK_OPS_PARENT_ENABLE chan= ge Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Laura Nao --- drivers/clk/mediatek/Makefile | 3 +- drivers/clk/mediatek/clk-mt8196-peri_ao.c | 142 ++++++++++++++++++++++ 2 files changed, 144 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/mediatek/clk-mt8196-peri_ao.c diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 031e7ac38804..8888ffd3d7ba 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -151,7 +151,8 @@ obj-$(CONFIG_COMMON_CLK_MT8195_VENCSYS) +=3D clk-mt8195= -venc.o obj-$(CONFIG_COMMON_CLK_MT8195_VPPSYS) +=3D clk-mt8195-vpp0.o clk-mt8195-v= pp1.o obj-$(CONFIG_COMMON_CLK_MT8195_WPESYS) +=3D clk-mt8195-wpe.o obj-$(CONFIG_COMMON_CLK_MT8196) +=3D clk-mt8196-apmixedsys.o clk-mt8196-to= pckgen.o \ - clk-mt8196-topckgen2.o clk-mt8196-vlpckgen.o + clk-mt8196-topckgen2.o clk-mt8196-vlpckgen.o \ + clk-mt8196-peri_ao.o obj-$(CONFIG_COMMON_CLK_MT8365) +=3D clk-mt8365-apmixedsys.o clk-mt8365.o obj-$(CONFIG_COMMON_CLK_MT8365_APU) +=3D clk-mt8365-apu.o obj-$(CONFIG_COMMON_CLK_MT8365_CAM) +=3D clk-mt8365-cam.o diff --git a/drivers/clk/mediatek/clk-mt8196-peri_ao.c b/drivers/clk/mediat= ek/clk-mt8196-peri_ao.c new file mode 100644 index 000000000000..f227a86c5d60 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8196-peri_ao.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 MediaTek Inc. + * Guangjie Song + * Copyright (c) 2025 Collabora Ltd. + * Laura Nao + */ +#include + +#include +#include +#include +#include + +#include "clk-gate.h" +#include "clk-mtk.h" + +static const struct mtk_gate_regs peri_ao0_cg_regs =3D { + .set_ofs =3D 0x24, + .clr_ofs =3D 0x28, + .sta_ofs =3D 0x10, +}; + +static const struct mtk_gate_regs peri_ao1_cg_regs =3D { + .set_ofs =3D 0x2c, + .clr_ofs =3D 0x30, + .sta_ofs =3D 0x14, +}; + +static const struct mtk_gate_regs peri_ao1_hwv_regs =3D { + .set_ofs =3D 0x0008, + .clr_ofs =3D 0x000c, + .sta_ofs =3D 0x2c04, +}; + +static const struct mtk_gate_regs peri_ao2_cg_regs =3D { + .set_ofs =3D 0x34, + .clr_ofs =3D 0x38, + .sta_ofs =3D 0x18, +}; + +#define GATE_PERI_AO0(_id, _name, _parent, _shift) { \ + .id =3D _id, \ + .name =3D _name, \ + .parent_name =3D _parent, \ + .regs =3D &peri_ao0_cg_regs, \ + .shift =3D _shift, \ + .ops =3D &mtk_clk_gate_ops_setclr, \ + } + +#define GATE_PERI_AO1(_id, _name, _parent, _shift) { \ + .id =3D _id, \ + .name =3D _name, \ + .parent_name =3D _parent, \ + .regs =3D &peri_ao1_cg_regs, \ + .shift =3D _shift, \ + .ops =3D &mtk_clk_gate_ops_setclr, \ + } + +#define GATE_HWV_PERI_AO1(_id, _name, _parent, _shift) {\ + .id =3D _id, \ + .name =3D _name, \ + .parent_name =3D _parent, \ + .regs =3D &peri_ao1_cg_regs, \ + .hwv_regs =3D &peri_ao1_hwv_regs, \ + .shift =3D _shift, \ + .ops =3D &mtk_clk_gate_hwv_ops_setclr, \ + } + +#define GATE_PERI_AO2(_id, _name, _parent, _shift) { \ + .id =3D _id, \ + .name =3D _name, \ + .parent_name =3D _parent, \ + .regs =3D &peri_ao2_cg_regs, \ + .shift =3D _shift, \ + .ops =3D &mtk_clk_gate_ops_setclr, \ + } + +static const struct mtk_gate peri_ao_clks[] =3D { + /* PERI_AO0 */ + GATE_PERI_AO0(CLK_PERI_AO_UART0_BCLK, "peri_ao_uart0_bclk", "uart", 0), + GATE_PERI_AO0(CLK_PERI_AO_UART1_BCLK, "peri_ao_uart1_bclk", "uart", 1), + GATE_PERI_AO0(CLK_PERI_AO_UART2_BCLK, "peri_ao_uart2_bclk", "uart", 2), + GATE_PERI_AO0(CLK_PERI_AO_UART3_BCLK, "peri_ao_uart3_bclk", "uart", 3), + GATE_PERI_AO0(CLK_PERI_AO_UART4_BCLK, "peri_ao_uart4_bclk", "uart", 4), + GATE_PERI_AO0(CLK_PERI_AO_UART5_BCLK, "peri_ao_uart5_bclk", "uart", 5), + GATE_PERI_AO0(CLK_PERI_AO_PWM_X16W_HCLK, "peri_ao_pwm_x16w", "p_axi", 12), + GATE_PERI_AO0(CLK_PERI_AO_PWM_X16W_BCLK, "peri_ao_pwm_x16w_bclk", "pwm", = 13), + GATE_PERI_AO0(CLK_PERI_AO_PWM_PWM_BCLK0, "peri_ao_pwm_pwm_bclk0", "pwm", = 14), + GATE_PERI_AO0(CLK_PERI_AO_PWM_PWM_BCLK1, "peri_ao_pwm_pwm_bclk1", "pwm", = 15), + GATE_PERI_AO0(CLK_PERI_AO_PWM_PWM_BCLK2, "peri_ao_pwm_pwm_bclk2", "pwm", = 16), + GATE_PERI_AO0(CLK_PERI_AO_PWM_PWM_BCLK3, "peri_ao_pwm_pwm_bclk3", "pwm", = 17), + /* PERI_AO1 */ + GATE_HWV_PERI_AO1(CLK_PERI_AO_SPI0_BCLK, "peri_ao_spi0_bclk", "spi0_b", 0= ), + GATE_HWV_PERI_AO1(CLK_PERI_AO_SPI1_BCLK, "peri_ao_spi1_bclk", "spi1_b", 2= ), + GATE_HWV_PERI_AO1(CLK_PERI_AO_SPI2_BCLK, "peri_ao_spi2_bclk", "spi2_b", 3= ), + GATE_HWV_PERI_AO1(CLK_PERI_AO_SPI3_BCLK, "peri_ao_spi3_bclk", "spi3_b", 4= ), + GATE_HWV_PERI_AO1(CLK_PERI_AO_SPI4_BCLK, "peri_ao_spi4_bclk", "spi4_b", 5= ), + GATE_HWV_PERI_AO1(CLK_PERI_AO_SPI5_BCLK, "peri_ao_spi5_bclk", "spi5_b", 6= ), + GATE_HWV_PERI_AO1(CLK_PERI_AO_SPI6_BCLK, "peri_ao_spi6_bclk", "spi6_b", 7= ), + GATE_HWV_PERI_AO1(CLK_PERI_AO_SPI7_BCLK, "peri_ao_spi7_bclk", "spi7_b", 8= ), + GATE_PERI_AO1(CLK_PERI_AO_FLASHIF_FLASH, "peri_ao_flashif_flash", "peri_a= o_flashif_27m", + 18), + GATE_PERI_AO1(CLK_PERI_AO_FLASHIF_27M, "peri_ao_flashif_27m", "sflash", 1= 9), + GATE_PERI_AO1(CLK_PERI_AO_FLASHIF_DRAM, "peri_ao_flashif_dram", "p_axi", = 20), + GATE_PERI_AO1(CLK_PERI_AO_FLASHIF_AXI, "peri_ao_flashif_axi", "peri_ao_fl= ashif_dram", 21), + GATE_PERI_AO1(CLK_PERI_AO_FLASHIF_BCLK, "peri_ao_flashif_bclk", "p_axi", = 22), + GATE_PERI_AO1(CLK_PERI_AO_AP_DMA_X32W_BCLK, "peri_ao_ap_dma_x32w_bclk", "= p_axi", 26), + /* PERI_AO2 */ + GATE_PERI_AO2(CLK_PERI_AO_MSDC1_MSDC_SRC, "peri_ao_msdc1_msdc_src", "msdc= 30_1", 1), + GATE_PERI_AO2(CLK_PERI_AO_MSDC1_HCLK, "peri_ao_msdc1", "peri_ao_msdc1_axi= ", 2), + GATE_PERI_AO2(CLK_PERI_AO_MSDC1_AXI, "peri_ao_msdc1_axi", "p_axi", 3), + GATE_PERI_AO2(CLK_PERI_AO_MSDC1_HCLK_WRAP, "peri_ao_msdc1_h_wrap", "peri_= ao_msdc1", 4), + GATE_PERI_AO2(CLK_PERI_AO_MSDC2_MSDC_SRC, "peri_ao_msdc2_msdc_src", "msdc= 30_2", 10), + GATE_PERI_AO2(CLK_PERI_AO_MSDC2_HCLK, "peri_ao_msdc2", "peri_ao_msdc2_axi= ", 11), + GATE_PERI_AO2(CLK_PERI_AO_MSDC2_AXI, "peri_ao_msdc2_axi", "p_axi", 12), + GATE_PERI_AO2(CLK_PERI_AO_MSDC2_HCLK_WRAP, "peri_ao_msdc2_h_wrap", "peri_= ao_msdc2", 13), +}; + +static const struct mtk_clk_desc peri_ao_mcd =3D { + .clks =3D peri_ao_clks, + .num_clks =3D ARRAY_SIZE(peri_ao_clks), +}; + +static const struct of_device_id of_match_clk_mt8196_peri_ao[] =3D { + { .compatible =3D "mediatek,mt8196-pericfg-ao", .data =3D &peri_ao_mcd }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8196_peri_ao); + +static struct platform_driver clk_mt8196_peri_ao_drv =3D { + .probe =3D mtk_clk_simple_probe, + .remove =3D mtk_clk_simple_remove, + .driver =3D { + .name =3D "clk-mt8196-peri-ao", + .of_match_table =3D of_match_clk_mt8196_peri_ao, + }, +}; + +MODULE_DESCRIPTION("MediaTek MT8196 pericfg_ao clock controller driver"); +module_platform_driver(clk_mt8196_peri_ao_drv); +MODULE_LICENSE("GPL"); --=20 2.39.5