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Mon, 15 Sep 2025 06:50:04 -0700 (PDT) Received: from cachyos-x8664 ([185.221.23.200]) by smtp.gmail.com with ESMTPSA id af79cd13be357-82a0d349ca3sm167578685a.64.2025.09.15.06.49.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Sep 2025 06:50:04 -0700 (PDT) From: Jia Qingtong X-Google-Original-From: Jia Qingtong To: oliver.upton@linux.dev, maz@kernel.org Cc: will@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, cohuck@redhat.com, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, jiaqingtong@huawei.com, jiaqingtong97@gmail.com, yuzenghui@huawei.com, jiangkunkun@huawei.com Subject: [RFC RESEND PATCH] arm64: Rename is_midr_in_range_list and add is_midr_subset_of_range_list Date: Mon, 15 Sep 2025 21:49:29 +0800 Message-ID: <20250915134932.8137-1-jiaqingtong@huawei.com> X-Mailer: git-send-email 2.51.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jia Qingtong Regarding the is_midr_in_range_list function, from the early discussions during submission [1][2], we know: 1. The VMM must ensure the correctness of the target impl CPU set. 2. For errata-related fixes, if any target impl CPU is affected, then all CPUs are considered affected. However, in commit e403e8538359 ("arm64: errata: Assume that unknown CPUs _are_ vulnerable to Spectre BHB") and commit d4647f0a2ad7 ("arm64: Rewrite Spectre-v2 mitigation code"), the functions is_spectre_bhb_safe and spectre_v2_get_cpu_hw_mitigation_state use is_midr_in_range_list to determine whether the current chip is not affected by the issue (rather than, as we might expect, whether it is affected by the erratum). Therefore, for the arg ranges of is_midr_in_range_list being tested, as long as there is one MIDR present in the target impl CPUs, the current VM (and the target impl CPUs) are considered not affected by the issue. This seems somewhat contrary to the original idea, since the VMM does not know whether KVM implements positive or negative logic. Hence, we may need to rename is_midr_in_range_list to is_any_midr_in_range_listto explicitly mean "if any target impl CPU is in range_list" and additionally introduce is_midr_subset_of_range_list for someone like is_spectre_bhb_safe to use. This patch just show is_midr_subset_of_range_list and it's example usage. [1] https://lore.kernel.org/kvmarm/86cyftty9q.wl-maz@kernel.org/ [2] https://lore.kernel.org/kvmarm/ZyG3FiUiyOi4t3rQ@linux.dev/ Fixes: 86edf6bdcf05 ("smccc/kvm_guest: Enable errata based on implementatio= n CPUs") Signed-off-by: Jia Qingtong --- arch/arm64/include/asm/cputype.h | 1 + arch/arm64/kernel/cpu_errata.c | 41 +++++++++++++++++++++++++++++++- arch/arm64/kernel/proton-pack.c | 4 ++-- 3 files changed, 43 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cput= ype.h index 661735616787..1339a2e37104 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -304,6 +304,7 @@ struct target_impl_cpu { =20 bool cpu_errata_set_target_impl(u64 num, void *impl_cpus); bool is_midr_in_range_list(struct midr_range const *ranges); +bool is_midr_subset_of_range_list(struct midr_range const *ranges); =20 static inline u64 __attribute_const__ read_cpuid_mpidr(void) { diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 59d723c9ab8f..30cc91f875d9 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -53,6 +53,45 @@ bool is_midr_in_range_list(struct midr_range const *rang= es) } EXPORT_SYMBOL_GPL(is_midr_in_range_list); =20 +bool is_midr_subset_of_range_list(struct midr_range const *ranges) +{ + int i; + unsigned long midr; + struct midr_range const *range_ptr; + + if (!target_impl_cpu_num) { + midr =3D read_cpuid_id(); + range_ptr =3D ranges; + while (range_ptr->model) { + if (midr_is_cpu_model_range(midr, range_ptr->model, + range_ptr->rv_min, range_ptr->rv_max)) + break; + range_ptr++; + } + return range_ptr->model !=3D 0; + } + + for (i =3D 0; i < target_impl_cpu_num; i++) { + bool found =3D false; + + midr =3D target_impl_cpus[i].midr; + range_ptr =3D ranges; + + while (range_ptr->model) { + if (midr_is_cpu_model_range(midr, range_ptr->model, + range_ptr->rv_min, range_ptr->rv_max)) { + found =3D true; + break; + } + range_ptr++; + } + if (!found) + return false; + } + return true; +} +EXPORT_SYMBOL_GPL(is_midr_subset_of_range_list); + static bool __maybe_unused __is_affected_midr_range(const struct arm64_cpu_capabilities *entry, u32 midr, u32 revidr) @@ -276,7 +315,7 @@ static bool has_impdef_pmuv3(const struct arm64_cpu_cap= abilities *entry, int sco if (pmuver !=3D ID_AA64DFR0_EL1_PMUVer_IMP_DEF) return false; =20 - return is_midr_in_range_list(impdef_pmuv3_cpus); + return is_midr_subset_of_range_list(impdef_pmuv3_cpus); } =20 static void cpu_enable_impdef_pmuv3_traps(const struct arm64_cpu_capabilit= ies *__unused) diff --git a/arch/arm64/kernel/proton-pack.c b/arch/arm64/kernel/proton-pac= k.c index edf1783ffc81..ce3660625743 100644 --- a/arch/arm64/kernel/proton-pack.c +++ b/arch/arm64/kernel/proton-pack.c @@ -172,7 +172,7 @@ static enum mitigation_state spectre_v2_get_cpu_hw_miti= gation_state(void) return SPECTRE_UNAFFECTED; =20 /* Alternatively, we have a list of unaffected CPUs */ - if (is_midr_in_range_list(spectre_v2_safe_list)) + if (is_midr_subset_of_range_list(spectre_v2_safe_list)) return SPECTRE_UNAFFECTED; =20 return SPECTRE_VULNERABLE; @@ -864,7 +864,7 @@ static bool is_spectre_bhb_safe(int scope) if (scope !=3D SCOPE_LOCAL_CPU) return all_safe; =20 - if (is_midr_in_range_list(spectre_bhb_safe_list)) + if (is_midr_subset_of_range_list(spectre_bhb_safe_list)) return true; =20 all_safe =3D false; base-commit: d69eb204c255c35abd9e8cb621484e8074c75eaa --=20 2.51.0