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Mon, 15 Sep 2025 09:45:09 +0000 (GMT) From: Raghav Sharma To: krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, conor+dt@kernel.org, sunyeal.hong@samsung.com, shin.son@samsung.com Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, chandan.vn@samsung.com, dev.tailor@samsung.com, karthik.sun@samsung.com, Raghav Sharma Subject: [PATCH v2 1/3] dt-bindings: clock: exynosautov920: add m2m clock definitions Date: Mon, 15 Sep 2025 15:23:59 +0530 Message-Id: <20250915095401.3699849-2-raghav.s@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250915095401.3699849-1-raghav.s@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250915094512epcas5p223e2eb264967508527f478eb2200be83 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-543,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250915094512epcas5p223e2eb264967508527f478eb2200be83 References: <20250915095401.3699849-1-raghav.s@samsung.com> Add device tree clock binding definitions for CMU_M2M Signed-off-by: Raghav Sharma Acked-by: Rob Herring (Arm) Reviewed-by: Alim Akhtar --- .../clock/samsung,exynosautov920-clock.yaml | 21 +++++++++++++++++++ .../clock/samsung,exynosautov920.h | 5 +++++ 2 files changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/samsung,exynosautov920= -clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynosautov92= 0-clock.yaml index 72f59db73f76..b2dfe6ed353a 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.= yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.= yaml @@ -38,6 +38,7 @@ properties: - samsung,exynosautov920-cmu-hsi0 - samsung,exynosautov920-cmu-hsi1 - samsung,exynosautov920-cmu-hsi2 + - samsung,exynosautov920-cmu-m2m - samsung,exynosautov920-cmu-misc - samsung,exynosautov920-cmu-peric0 - samsung,exynosautov920-cmu-peric1 @@ -226,6 +227,26 @@ allOf: - const: embd - const: ethernet =20 + - if: + properties: + compatible: + contains: + const: samsung,exynosautov920-cmu-m2m + + then: + properties: + clocks: + items: + - description: External reference clock (38.4 MHz) + - description: CMU_M2M NOC clock (from CMU_TOP) + - description: CMU_M2M JPEG clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: noc + - const: jpeg + required: - compatible - "#clock-cells" diff --git a/include/dt-bindings/clock/samsung,exynosautov920.h b/include/d= t-bindings/clock/samsung,exynosautov920.h index 93e6233d1358..0342a988565a 100644 --- a/include/dt-bindings/clock/samsung,exynosautov920.h +++ b/include/dt-bindings/clock/samsung,exynosautov920.h @@ -295,4 +295,9 @@ #define CLK_DOUT_HSI2_ETHERNET 6 #define CLK_DOUT_HSI2_ETHERNET_PTP 7 =20 +/* CMU_M2M */ +#define CLK_MOUT_M2M_JPEG_USER 1 +#define CLK_MOUT_M2M_NOC_USER 2 +#define CLK_DOUT_M2M_NOCP 3 + #endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */ --=20 2.34.1 From nobody Thu Oct 2 15:35:35 2025 Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 877882F99B0 for ; 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Mon, 15 Sep 2025 09:45:16 +0000 (GMT) Received: from epcas5p1.samsung.com (unknown [182.195.38.94]) by epsnrtp04.localdomain (Postfix) with ESMTP id 4cQKrq564Tz6B9m6; Mon, 15 Sep 2025 09:45:15 +0000 (GMT) Received: from epsmtip2.samsung.com (unknown [182.195.34.31]) by epcas5p3.samsung.com (KnoxPortal) with ESMTPA id 20250915094515epcas5p3210f5c66a24a7a7f23a04075e7636a89~la5R8b5L52434524345epcas5p3j; Mon, 15 Sep 2025 09:45:15 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250915094512epsmtip265804811e091d1c92f81b7275247ed9c~la5PipG0g0931709317epsmtip2j; Mon, 15 Sep 2025 09:45:12 +0000 (GMT) From: Raghav Sharma To: krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, conor+dt@kernel.org, sunyeal.hong@samsung.com, shin.son@samsung.com Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, chandan.vn@samsung.com, dev.tailor@samsung.com, karthik.sun@samsung.com, Raghav Sharma Subject: [PATCH v2 2/3] clk: samsung: exynosautov920: add clock support Date: Mon, 15 Sep 2025 15:24:00 +0530 Message-Id: <20250915095401.3699849-3-raghav.s@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250915095401.3699849-1-raghav.s@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250915094515epcas5p3210f5c66a24a7a7f23a04075e7636a89 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-543,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250915094515epcas5p3210f5c66a24a7a7f23a04075e7636a89 References: <20250915095401.3699849-1-raghav.s@samsung.com> Add support for CMU_M2M which provides clocks to M2M block, and register the required compatible and cmu_info for the same. Signed-off-by: Raghav Sharma Reviewed-by: Alim Akhtar --- drivers/clk/samsung/clk-exynosautov920.c | 45 ++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/clk/samsung/clk-exynosautov920.c b/drivers/clk/samsung= /clk-exynosautov920.c index 572b6ace14ac..75deec8bece5 100644 --- a/drivers/clk/samsung/clk-exynosautov920.c +++ b/drivers/clk/samsung/clk-exynosautov920.c @@ -27,6 +27,7 @@ #define CLKS_NR_HSI0 (CLK_DOUT_HSI0_PCIE_APB + 1) #define CLKS_NR_HSI1 (CLK_MOUT_HSI1_USBDRD + 1) #define CLKS_NR_HSI2 (CLK_DOUT_HSI2_ETHERNET_PTP + 1) +#define CLKS_NR_M2M (CLK_DOUT_M2M_NOCP + 1) =20 /* ---- CMU_TOP ----------------------------------------------------------= -- */ =20 @@ -1821,6 +1822,47 @@ static const struct samsung_cmu_info hsi2_cmu_info _= _initconst =3D { .clk_name =3D "noc", }; =20 +/* ---- CMU_M2M --------------------------------------------------------- = */ + +/* Register Offset definitions for CMU_M2M (0x1a800000) */ +#define PLL_CON0_MUX_CLKCMU_M2M_JPEG_USER 0x600 +#define PLL_CON0_MUX_CLKCMU_M2M_NOC_USER 0x610 +#define CLK_CON_DIV_DIV_CLK_M2M_NOCP 0x1800 + +static const unsigned long m2m_clk_regs[] __initconst =3D { + PLL_CON0_MUX_CLKCMU_M2M_JPEG_USER, + PLL_CON0_MUX_CLKCMU_M2M_NOC_USER, + CLK_CON_DIV_DIV_CLK_M2M_NOCP, +}; + +/* List of parent clocks for Muxes in CMU_M2M */ +PNAME(mout_clkcmu_m2m_noc_user_p) =3D { "oscclk", "dout_clkcmu_m2m_noc" }; +PNAME(mout_clkcmu_m2m_jpeg_user_p) =3D { "oscclk", "dout_clkcmu_m2m_jpeg" = }; + +static const struct samsung_mux_clock m2m_mux_clks[] __initconst =3D { + MUX(CLK_MOUT_M2M_JPEG_USER, "mout_clkcmu_m2m_jpeg_user", + mout_clkcmu_m2m_jpeg_user_p, PLL_CON0_MUX_CLKCMU_M2M_JPEG_USER, 4, 1), + MUX(CLK_MOUT_M2M_NOC_USER, "mout_clkcmu_m2m_noc_user", + mout_clkcmu_m2m_noc_user_p, PLL_CON0_MUX_CLKCMU_M2M_NOC_USER, 4, 1), +}; + +static const struct samsung_div_clock m2m_div_clks[] __initconst =3D { + DIV(CLK_DOUT_M2M_NOCP, "dout_m2m_nocp", + "mout_clkcmu_m2m_noc_user", CLK_CON_DIV_DIV_CLK_M2M_NOCP, + 0, 3), +}; + +static const struct samsung_cmu_info m2m_cmu_info __initconst =3D { + .mux_clks =3D m2m_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(m2m_mux_clks), + .div_clks =3D m2m_div_clks, + .nr_div_clks =3D ARRAY_SIZE(m2m_div_clks), + .nr_clk_ids =3D CLKS_NR_M2M, + .clk_regs =3D m2m_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(m2m_clk_regs), + .clk_name =3D "noc", +}; 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Mon, 15 Sep 2025 09:45:17 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20250915094515epsmtip24dc5a7988d4add454ce9185519ae6d2d~la5SLhp3X0834508345epsmtip2S; Mon, 15 Sep 2025 09:45:15 +0000 (GMT) From: Raghav Sharma To: krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, conor+dt@kernel.org, sunyeal.hong@samsung.com, shin.son@samsung.com Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, chandan.vn@samsung.com, dev.tailor@samsung.com, karthik.sun@samsung.com, Raghav Sharma Subject: [PATCH v2 3/3] arm64: dts: exynosautov920: add CMU_M2M clock DT nodes Date: Mon, 15 Sep 2025 15:24:01 +0530 Message-Id: <20250915095401.3699849-4-raghav.s@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250915095401.3699849-1-raghav.s@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250915094517epcas5p2186fc92cca758b6fe610c0ec91ee51bc X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-543,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250915094517epcas5p2186fc92cca758b6fe610c0ec91ee51bc References: <20250915095401.3699849-1-raghav.s@samsung.com> Add required dt node for CMU_M2M block, which provides clocks for M2M IP Signed-off-by: Raghav Sharma Reviewed-by: Alim Akhtar --- arch/arm64/boot/dts/exynos/exynosautov920.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/bo= ot/dts/exynos/exynosautov920.dtsi index 0fdf2062930a..d19d71faa6f8 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -1454,6 +1454,19 @@ pinctrl_aud: pinctrl@1a460000 { reg =3D <0x1a460000 0x10000>; }; =20 + cmu_m2m: clock-controller@1a800000 { + compatible =3D "samsung,exynosautov920-cmu-m2m"; + reg =3D <0x1a800000 0x8000>; + #clock-cells =3D <1>; + + clocks =3D <&xtcxo>, + <&cmu_top DOUT_CLKCMU_M2M_NOC>, + <&cmu_top DOUT_CLKCMU_M2M_JPEG>; + clock-names =3D "oscclk", + "noc", + "jpeg"; + }; + cmu_cpucl0: clock-controller@1ec00000 { compatible =3D "samsung,exynosautov920-cmu-cpucl0"; reg =3D <0x1ec00000 0x8000>; --=20 2.34.1