From nobody Thu Oct 2 16:59:08 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C23A02F39B5; Mon, 15 Sep 2025 08:57:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757926634; cv=none; b=I2IGkfh6xCSyX0xqpjnWbJAYm/2NPiBoqyWb4aGWsy6+VpHYomEHWZ7R8q2i4V5qgAiY5DJjdF7dk7e77PO5L+wKp/GX0nta+6LKq2+jNHt/u4ouBQYu/9T/WfG2w86UhE/GX1Z6we4dGxMmmOQ9aX1wMg9uBb7vZjjiT9lxjY8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757926634; c=relaxed/simple; bh=b54oXtSJ1jOB+4cqyMvjMq57VTZoxc0ThWvLI8ltuVk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=RrFgpaSHt5tq5t87zmaXviILCBLavB53X0oyR9O2DPpaJmSmkmlaDOK7GMARZr+Swr4Dp4CUwGZ/o8LxjZCG8OG/lGGWSwF87G9DLN0IyOBhTC4oMlQL8YYbvsaUtvSLmTtNx+Wj45aUP9QIe0S04zLroPxse9JvfZCRNWhyxHc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KjPSf40E; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KjPSf40E" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6571EC4CEFE; Mon, 15 Sep 2025 08:57:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757926634; bh=b54oXtSJ1jOB+4cqyMvjMq57VTZoxc0ThWvLI8ltuVk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KjPSf40E6TotVtFTseCZ7k5hHBxe+ZImDQR8/ElNulpp1ve3o5p7KZtWzGE1Uievc HNEo1y0XrLTxaI+SS7UgL5iihkLl4XwI1HrDaVkNG5jVMH41Y8giZbualFPiUGSupB ADA2Xj49/pL8+VMyijdfe2CSY/h4EwDaQ3I6kyOqU5lbKqqwGQogwlZdUv/AM5+wah Q+1KtZu2QYlaXID8IHFsUfizBmipkYTno0xtl/ZPrdmgJD0SOcXrWTnTjmIK+iMCtS UlF4BP4og2EADhqlcbUPOPkW8BFFli5xuCGxoAo8/DcXiZjQRDn7mvFqHACbtPmspZ Ymky/Wof7u3yw== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1uy51M-00000006IHP-1kaB; Mon, 15 Sep 2025 08:57:12 +0000 From: Marc Zyngier To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org Cc: Thomas Gleixner , Mark Rutland , Will Deacon , "Rafael J. Wysocki" , Rob Herring , Saravana Kannan , Greg Kroah-Hartman , Sven Peter , Janne Grunau , Suzuki K Poulose , James Clark Subject: [PATCH v2 05/25] irqchip/gic-v3: Add FW info retrieval support Date: Mon, 15 Sep 2025 09:56:42 +0100 Message-Id: <20250915085702.519996-6-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250915085702.519996-1-maz@kernel.org> References: <20250915085702.519996-1-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, tglx@linutronix.de, mark.rutland@arm.com, will@kernel.org, rafael@kernel.org, robh@kernel.org, saravanak@google.com, gregkh@linuxfoundation.org, sven@kernel.org, j@jannau.net, suzuki.poulose@arm.com, james.clark@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Content-Type: text/plain; charset="utf-8" Plug the new .get_info() callback into the GICv3 core driver, using some of the existing PPI affinity handling infrastructure. Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-gic-v3.c | 53 ++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index dbeb85677b08c..71c278ddd1e39 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -69,6 +69,8 @@ struct gic_chip_data { bool has_rss; unsigned int ppi_nr; struct partition_desc **ppi_descs; + struct partition_affinity *parts; + unsigned int nr_parts; }; =20 #define T241_CHIPS_MAX 4 @@ -1796,11 +1798,58 @@ static int gic_irq_domain_select(struct irq_domain = *d, return d =3D=3D partition_get_domain(gic_data.ppi_descs[ppi_idx]); } =20 +static int gic_irq_get_fwspec_info(struct irq_fwspec *fwspec, struct irq_f= wspec_info *info) +{ + const struct cpumask *mask =3D NULL; + + info->flags =3D 0; + info->affinity =3D NULL; + + /* ACPI is not capable of describing PPI affinity -- yet */ + if (!is_of_node(fwspec->fwnode)) + return 0; + + /* If the specifier provides an affinity, use it */ + if (fwspec->param_count =3D=3D 4 && fwspec->param[3]) { + struct fwnode_handle *fw; + + switch (fwspec->param[0]) { + case 1: /* PPI */ + case 3: /* EPPI */ + break; + default: + return 0; + } + + fw =3D of_node_to_fwnode(of_find_node_by_phandle(fwspec->param[3])); + if (!fw) + return -ENOENT; + + for (int i =3D 0; i < gic_data.nr_parts; i++) { + if (gic_data.parts[i].partition_id =3D=3D fw) { + mask =3D &gic_data.parts[i].mask; + break; + } + } + + if (!mask) + return -ENOENT; + } else { + mask =3D cpu_possible_mask; + } + + info->affinity =3D mask; + info->flags =3D IRQ_FWSPEC_INFO_AFFINITY_VALID; + + return 0; +} + static const struct irq_domain_ops gic_irq_domain_ops =3D { .translate =3D gic_irq_domain_translate, .alloc =3D gic_irq_domain_alloc, .free =3D gic_irq_domain_free, .select =3D gic_irq_domain_select, + .get_fwspec_info =3D gic_irq_get_fwspec_info, }; =20 static int partition_domain_translate(struct irq_domain *d, @@ -1839,6 +1888,7 @@ static int partition_domain_translate(struct irq_doma= in *d, static const struct irq_domain_ops partition_domain_ops =3D { .translate =3D partition_domain_translate, .select =3D gic_irq_domain_select, + .get_fwspec_info =3D gic_irq_get_fwspec_info, }; =20 static bool gic_enable_quirk_msm8996(void *data) @@ -2231,6 +2281,9 @@ static void __init gic_populate_ppi_partitions(struct= device_node *gic_node) part_idx++; } =20 + gic_data.parts =3D parts; + gic_data.nr_parts =3D nr_parts; + for (i =3D 0; i < gic_data.ppi_nr; i++) { unsigned int irq; struct partition_desc *desc; --=20 2.39.2