From nobody Thu Oct 2 15:35:02 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A56462D7388; Mon, 15 Sep 2025 07:39:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757921983; cv=none; b=I+RABGEjq8gZFmr/M9uEhERVANqxhUJzmly627hnjU7lyh65Np7HmZU7XGYw93lhYlLOd/XuMgI6YhJJQ3Uhy0ei16Gd8Q1IYr/lAvMhyjqkULQy6axKeq4UpU7lfj1lj/jEjragARZJnx44NHmeinQ+T3VIKpEmOxJFHg0d83A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757921983; c=relaxed/simple; bh=qSuz+bKGDq7k+juHcdsrwoGO+rS155RqVm52v5DFmnA=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kyLCumzl3jhttXiU1loaQnW98N4HNqFq7D4x6HTUhMrQ9iWeTJ9ErJJldA50CN02vYk9N1xkI+99oHJCCxJw9Za7U3EJH/BQR3DgqzocqUQEKesAKQUEfjKOZpJ1LQQyrVClNNp21MCnMG/8PYVwVdktgjyzJIqlYig9R8wtuYQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 15 Sep 2025 15:39:26 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 15 Sep 2025 15:39:26 +0800 From: Ryan Chen To: ryan_chen , Greg Kroah-Hartman , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Alan Stern" , Philipp Zabel , , , Subject: [PATCH 1/4] dt-bindings: usb: uhci: Add reset property Date: Mon, 15 Sep 2025 15:39:23 +0800 Message-ID: <20250915073926.3057368-2-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250915073926.3057368-1-ryan_chen@aspeedtech.com> References: <20250915073926.3057368-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The UHCI controller on Aspeed SoCs (including AST2700) requires its reset line to be deasserted before the controller can be used. Add an optional "resets" property to the UHCI device tree bindings to describe the phandle to the reset controller. This property is optional for platforms which do not require explicit reset handling. Signed-off-by: Ryan Chen --- Documentation/devicetree/bindings/usb/usb-uhci.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/usb-uhci.yaml b/Document= ation/devicetree/bindings/usb/usb-uhci.yaml index d8336f72dc1f..b1f2b9bd7921 100644 --- a/Documentation/devicetree/bindings/usb/usb-uhci.yaml +++ b/Documentation/devicetree/bindings/usb/usb-uhci.yaml @@ -28,6 +28,9 @@ properties: interrupts: maxItems: 1 =20 + resets: + maxItems: 1 + '#ports': $ref: /schemas/types.yaml#/definitions/uint32 =20 --=20 2.34.1 From nobody Thu Oct 2 15:35:02 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35F532D8797; Mon, 15 Sep 2025 07:39:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757921985; cv=none; b=fPS3JFwbYgQ52Mr7oV1GAQ5Lj5lfkqf9MvDGA88qjqPJ5e+ZnVKLv2J0KLRL1z9Zny935UIa4Pl+t7fyPTCvXV9cz3IRbwzu0YfZgRaXK3laRBHaeTVhFuVlsGRMfZu+gSzyFjFhAauY9SlMzhV6uaAdokw2b9nuTqiO4uuPmk0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757921985; c=relaxed/simple; bh=v0Fdq4yGYjrYVEXfEEiJnFpHWGc7NwCZylOn0tkbZEQ=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QCpvwe1TBwO8Wyf0gi3IDT4kO7OA1vxr5kypSdfDmYjGdec7HOFqPnZCgW1FxTZhwlaZaZ7jNm5mXMuWvPhKlaP3cFzvMqXC/sGK/mpQA9Yq4kCmYuRGmIbuFF7zhECBUc1JF3pNzwPIhohoFnCER4wo3Hl3+LMobY5wJwNSxsw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 15 Sep 2025 15:39:26 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 15 Sep 2025 15:39:26 +0800 From: Ryan Chen To: ryan_chen , Greg Kroah-Hartman , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Alan Stern" , Philipp Zabel , , , Subject: [PATCH 2/4] usb: uhci: Add reset control support Date: Mon, 15 Sep 2025 15:39:24 +0800 Message-ID: <20250915073926.3057368-3-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250915073926.3057368-1-ryan_chen@aspeedtech.com> References: <20250915073926.3057368-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some SoCs, such as the Aspeed AST2700, require the UHCI controller to be taken out of reset before it can operate. Add optional reset control support to the UHCI platform driver. The driver now acquires an optional reset line from device tree, deasserts it during probe, and asserts it again in the error path and shutdown. Signed-off-by: Ryan Chen --- drivers/usb/host/uhci-hcd.h | 1 + drivers/usb/host/uhci-platform.c | 19 +++++++++++++++++-- 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/usb/host/uhci-hcd.h b/drivers/usb/host/uhci-hcd.h index 13ee2a6144b2..4326d1f3ca76 100644 --- a/drivers/usb/host/uhci-hcd.h +++ b/drivers/usb/host/uhci-hcd.h @@ -445,6 +445,7 @@ struct uhci_hcd { short load[MAX_PHASE]; /* Periodic allocations */ =20 struct clk *clk; /* (optional) clock source */ + struct reset_control *rsts; /* (optional) clock reset */ =20 /* Reset host controller */ void (*reset_hc) (struct uhci_hcd *uhci); diff --git a/drivers/usb/host/uhci-platform.c b/drivers/usb/host/uhci-platf= orm.c index 62318291f566..010c458e7d8f 100644 --- a/drivers/usb/host/uhci-platform.c +++ b/drivers/usb/host/uhci-platform.c @@ -11,6 +11,7 @@ #include #include #include +#include =20 static int uhci_platform_init(struct usb_hcd *hcd) { @@ -132,19 +133,33 @@ static int uhci_hcd_platform_probe(struct platform_de= vice *pdev) goto err_rmr; } =20 + uhci->rsts =3D devm_reset_control_array_get_optional_shared(&pdev->dev); + if (IS_ERR(uhci->rsts)) { + ret =3D PTR_ERR(uhci->rsts); + goto err_clk; + } + ret =3D reset_control_deassert(uhci->rsts); + if (ret) + goto err_clk; + ret =3D platform_get_irq(pdev, 0); if (ret < 0) - goto err_clk; + goto err_reset; =20 ret =3D usb_add_hcd(hcd, ret, IRQF_SHARED); if (ret) - goto err_clk; + goto err_reset; =20 device_wakeup_enable(hcd->self.controller); return 0; =20 err_clk: clk_disable_unprepare(uhci->clk); + +err_reset: + if (!IS_ERR_OR_NULL(uhci->rsts)) + reset_control_assert(uhci->rsts); + err_rmr: usb_put_hcd(hcd); =20 --=20 2.34.1 From nobody Thu Oct 2 15:35:02 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 690442D6E56; Mon, 15 Sep 2025 07:39:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757921987; cv=none; b=UwgLCS3lB9e8rZJ/+9YhuntwSMDf8A24xCsAGC/gsxG4t7hugXElq6RKCD/S2PrMKlCbjDOtV8FUGTckmIYo7s1uPMQYxLffBTA22IUo6zC5nHlUmM09Mh5PzZneQSAJIRGGUy7JmY+2VQpKiXx600GOEowyUyT3cGf2XdRejqo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757921987; c=relaxed/simple; bh=KfOzNMOyr47r5TWJb+mjDVqIqZsvhicYJRw828QT7Uk=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=CJJH1BRXGWAw8HRGiM/av48F96fyTOvjo0qdETX0om5wVZjX/MoUSe6GGEQ2pNk9JgPPIA2SNvXzvVNQE91sTLiK6Mgc2EXDyXx4tP9Ma8MI+SZcHp26wzJsik7/FPjzX8C10P6ypuBuCnJXb6brpO38RHfBJyweTV3A1epmWCo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 15 Sep 2025 15:39:26 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 15 Sep 2025 15:39:26 +0800 From: Ryan Chen To: ryan_chen , Greg Kroah-Hartman , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Alan Stern" , Philipp Zabel , , , Subject: [PATCH 3/4] dt-bindings: usb: uhci: Add Aspeed AST2700 compatible Date: Mon, 15 Sep 2025 15:39:25 +0800 Message-ID: <20250915073926.3057368-4-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250915073926.3057368-1-ryan_chen@aspeedtech.com> References: <20250915073926.3057368-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the compatible string for Aspeed AST2700 SoC. Signed-off-by: Ryan Chen Acked-by: Conor Dooley --- Documentation/devicetree/bindings/usb/usb-uhci.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/usb-uhci.yaml b/Document= ation/devicetree/bindings/usb/usb-uhci.yaml index b1f2b9bd7921..6861c1d3c5eb 100644 --- a/Documentation/devicetree/bindings/usb/usb-uhci.yaml +++ b/Documentation/devicetree/bindings/usb/usb-uhci.yaml @@ -20,6 +20,7 @@ properties: - aspeed,ast2400-uhci - aspeed,ast2500-uhci - aspeed,ast2600-uhci + - aspeed,ast2700-uhci - const: generic-uhci =20 reg: --=20 2.34.1 From nobody Thu Oct 2 15:35:02 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67E562DC34B; Mon, 15 Sep 2025 07:39:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757921989; cv=none; b=lA1IgNs67AYfdzihM9gjMzwNZl9QViWUzIdCkRMtn0BC6ntqNDJh5Q4f70WTyXN1+oYNIJcx1GTNkNjXGTcax0wej6OzGv/PN+1X91+LcbNNCtmVW1DjvKqLsh1OkGqf6aC95s5ZnuoVzwB3Z2L9hRUMq/GjHVqixM5tE6T3bN4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757921989; c=relaxed/simple; bh=AsQ0kXWPHX6N8RSiom5wtRA4QFYaJO1fYEXrO99sRBs=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kc3x4EZjTs0f4VC5y54fDi/d4b5YySS7tU6aqW//WaBwUKo68gKz/Z8387Hf3ZGvcjUCXn8+39KgTwgubA7lwuLUTYz/Kb+ACCU51F2SupwNIcdbz6Bv28Vtdqiae1cvnU/M6QOwrO6NJFR+JRCLjGk1MBt+9/iCsNbOLk/G44w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 15 Sep 2025 15:39:26 +0800 Received: from twmbx02.aspeed.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 15 Sep 2025 15:39:26 +0800 From: Ryan Chen To: ryan_chen , Greg Kroah-Hartman , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Alan Stern" , Philipp Zabel , , , Subject: [PATCH 4/4] usb: uhci: Add Aspeed AST2700 support Date: Mon, 15 Sep 2025 15:39:26 +0800 Message-ID: <20250915073926.3057368-5-ryan_chen@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250915073926.3057368-1-ryan_chen@aspeedtech.com> References: <20250915073926.3057368-1-ryan_chen@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unlike earlier Aspeed SoCs (AST2400/2500/2600) which are limited to 32-bit DMA addressing, the UHCI controller in AST2700 supports 64-bit DMA. Update the platform UHCI driver to select the appropriate DMA mask based on the device tree compatible string. Signed-off-by: Ryan Chen --- drivers/usb/host/uhci-platform.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/usb/host/uhci-platform.c b/drivers/usb/host/uhci-platf= orm.c index 010c458e7d8f..24628b0ce99b 100644 --- a/drivers/usb/host/uhci-platform.c +++ b/drivers/usb/host/uhci-platform.c @@ -71,6 +71,7 @@ static int uhci_hcd_platform_probe(struct platform_device= *pdev) struct usb_hcd *hcd; struct uhci_hcd *uhci; struct resource *res; + u64 *dma_mask_ptr; int ret; =20 if (usb_disabled()) @@ -81,7 +82,8 @@ static int uhci_hcd_platform_probe(struct platform_device= *pdev) * Since shared usb code relies on it, set it here for now. * Once we have dma capability bindings this can go away. */ - ret =3D dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); + dma_mask_ptr =3D (u64 *)of_device_get_match_data(&pdev->dev); + ret =3D dma_coerce_mask_and_coherent(&pdev->dev, *dma_mask_ptr); if (ret) return ret; =20 @@ -114,7 +116,8 @@ static int uhci_hcd_platform_probe(struct platform_devi= ce *pdev) } if (of_device_is_compatible(np, "aspeed,ast2400-uhci") || of_device_is_compatible(np, "aspeed,ast2500-uhci") || - of_device_is_compatible(np, "aspeed,ast2600-uhci")) { + of_device_is_compatible(np, "aspeed,ast2600-uhci") || + of_device_is_compatible(np, "aspeed,ast2700-uhci")) { uhci->is_aspeed =3D 1; dev_info(&pdev->dev, "Enabled Aspeed implementation workarounds\n"); @@ -190,9 +193,13 @@ static void uhci_hcd_platform_shutdown(struct platform= _device *op) uhci_hc_died(hcd_to_uhci(hcd)); } =20 +static const u64 dma_mask_32 =3D DMA_BIT_MASK(32); +static const u64 dma_mask_64 =3D DMA_BIT_MASK(64); + static const struct of_device_id platform_uhci_ids[] =3D { - { .compatible =3D "generic-uhci", }, - { .compatible =3D "platform-uhci", }, + { .compatible =3D "generic-uhci", .data =3D &dma_mask_32}, + { .compatible =3D "platform-uhci", .data =3D &dma_mask_32}, + { .compatible =3D "aspeed,ast2700-uhci", .data =3D &dma_mask_64}, {} }; MODULE_DEVICE_TABLE(of, platform_uhci_ids); --=20 2.34.1