From nobody Thu Oct 2 16:34:32 2025 Received: from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 80D5D2627EC for ; Mon, 15 Sep 2025 04:07:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.33 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757909268; cv=none; b=ujBmndtDeISshOMjT1j4OlM6SE54XAfzIyDMYnwwUdO1JoDWbp929QCvODW98PdnpOTeDx0XnMA4Udyw9DFIY/8gOqCvZOFek4IfT1ANdW3+ovvBNrsjysWDvbQVllURpV6BQl4NzME9YuMxogcfMYthwsMZE6zQCfu3DyzXNsE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757909268; c=relaxed/simple; bh=/OKMi0PnO4k+dDlZzQopdGGaUBSxmOlHHX8LMLoa7Tc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:MIME-Version: Content-Type:References; b=JWZZKZOt94dKRYXIuASA6Ws0Wd0cLnLsgSUmwQdOmrg8zbbzHiCmIUHk1FKE4aloeJ672+BhC1EJc4rwKOOb3BaqvZYh03Ml0cCsA524oSCujhNJixJ/YPJcLHcSLkdu19+ZEHYh4+Qs4TmqS32vdsmivOaqWPNokdSOAyCaS0I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=U7LIIgpu; arc=none smtp.client-ip=203.254.224.33 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="U7LIIgpu" Received: from epcas2p4.samsung.com (unknown [182.195.41.56]) by mailout3.samsung.com (KnoxPortal) with ESMTP id 20250915040744epoutp03284476add525e2e4d71505faea8dd1a7~lWSmFKsZo2703127031epoutp03H for ; Mon, 15 Sep 2025 04:07:44 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout3.samsung.com 20250915040744epoutp03284476add525e2e4d71505faea8dd1a7~lWSmFKsZo2703127031epoutp03H DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1757909264; bh=2lZzaMhkerEF9X8trQsLpjUpa3JpSWLt4zEQJ0GLguw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=U7LIIgpuGUhCXSZnPDcOsUAc9ZRqaGGj77Fhp8+/CFpc/QGaitY4fo47RvgyN8Pbe CLTQm2fRC3f8J3hzZBRkKG6sN5S0KiQEZ3ehE3cJ25FgwjGgOfhu4QeydFHAobqR8p mXbRk3995l2jhu3SQSFbnP/52XjTmO0OaxqHgCrk= Received: from epsnrtp04.localdomain (unknown [182.195.42.156]) by epcas2p1.samsung.com (KnoxPortal) with ESMTPS id 20250915040743epcas2p12771b571ce7f5fc30b1a2d5c21cf092f~lWSlknehV2098120981epcas2p19; Mon, 15 Sep 2025 04:07:43 +0000 (GMT) Received: from epcas2p2.samsung.com (unknown [182.195.36.101]) by epsnrtp04.localdomain (Postfix) with ESMTP id 4cQBMM1dXrz6B9m6; Mon, 15 Sep 2025 04:07:43 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas2p4.samsung.com (KnoxPortal) with ESMTPA id 20250915040742epcas2p4ddc37eb56eb9d96313a5c3fac8befe5d~lWSkYbScR0669406694epcas2p47; Mon, 15 Sep 2025 04:07:42 +0000 (GMT) Received: from asswp60 (unknown [10.229.9.60]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250915040742epsmtip1c26994646df08c79e3a53cfd16ff13e9~lWSkRItFT3249532495epsmtip1e; Mon, 15 Sep 2025 04:07:42 +0000 (GMT) From: Shin Son To: Bartlomiej Zolnierkiewicz , Krzysztof Kozlowski , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Conor Dooley , Alim Akhtar , Henrik Grimler Cc: Shin Son , linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/3] dt-bindings: thermal: samsung: Add a hw-sensor-indices property Date: Mon, 15 Sep 2025 13:07:13 +0900 Message-ID: <20250915040715.486733-2-shin.son@samsung.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250915040715.486733-1-shin.son@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250915040742epcas2p4ddc37eb56eb9d96313a5c3fac8befe5d X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P cpgsPolicy: CPGSC10-234,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250915040742epcas2p4ddc37eb56eb9d96313a5c3fac8befe5d References: <20250915040715.486733-1-shin.son@samsung.com> The exynosautov920 TMU requires per-sensor interrupt enablement for its critical trip points. - **samsung,hw-sensor-indices**: List of sensor indices physically monitored by this TMU block. Indicies not listed exist in the SoC register map but are not part of this TMU instance Additionally, add myself to the bindings' maintainers list, as I plan to actively work on the exynosautov920 TMU support and handle further updates in this area. I also restrict 'samsung,hw-sensor-indices' to the V920 variant. To ensure properties introduced in 'if/then' blocks are recognized, I replace 'addtionalProperties: false' with 'unevaluatedProperties: false'. Signed-off-by: Shin Son --- .../thermal/samsung,exynos-thermal.yaml | 40 ++++++++++++++++++- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/samsung,exynos-therm= al.yaml b/Documentation/devicetree/bindings/thermal/samsung,exynos-thermal.= yaml index 29a08b0729ee..448c68986b10 100644 --- a/Documentation/devicetree/bindings/thermal/samsung,exynos-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/samsung,exynos-thermal.yaml @@ -8,6 +8,7 @@ title: Samsung Exynos SoC Thermal Management Unit (TMU) =20 maintainers: - Krzysztof Kozlowski + - Shin Son =20 description: | For multi-instance tmu each instance should have an alias correctly numb= ered @@ -27,6 +28,7 @@ properties: - samsung,exynos5420-tmu-ext-triminfo - samsung,exynos5433-tmu - samsung,exynos7-tmu + - samsung,exynosautov920-tmu =20 clocks: minItems: 1 @@ -62,7 +64,7 @@ properties: minItems: 1 =20 '#thermal-sensor-cells': - const: 0 + enum: [0, 1] =20 vtmu-supply: description: The regulator node supplying voltage to TMU. @@ -97,6 +99,8 @@ allOf: reg: minItems: 2 maxItems: 2 + '#thermal-sensor-cells': + const: 0 - if: properties: compatible: @@ -119,6 +123,8 @@ allOf: reg: minItems: 1 maxItems: 1 + '#thermal-sensor-cells': + const: 0 =20 - if: properties: @@ -139,8 +145,38 @@ allOf: reg: minItems: 1 maxItems: 1 + '#thermal-sensor-cells': + const: 0 =20 -additionalProperties: false + - if: + properties: + compatible: + contains: + const: samsung,exynosautov920-tmu + then: + properties: + clocks: + minItems: 1 + maxItems: 1 + reg: + minItems: 1 + maxItems: 1 + '#thermal-sensor-cells': + const: 1 + samsung,hw-sensor-indices: + description: + List of thermal sensor indices physically monitored by this TM= U instance. + Indices not listed correspond to registers that exist in the S= oC + but are not connected to this TMU hardware block. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 16 + uniqueItems: true + items: + minimum: 0 + maximum: 15 + +unevaluatedProperties: false =20 examples: - | --=20 2.50.1 From nobody Thu Oct 2 16:34:32 2025 Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 384D1255E40 for ; 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Mon, 15 Sep 2025 04:07:55 +0000 (GMT) Received: from epcas2p1.samsung.com (unknown [182.195.36.99]) by epsnrtp02.localdomain (Postfix) with ESMTP id 4cQBMb1Bgxz2SSKq; Mon, 15 Sep 2025 04:07:55 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas2p2.samsung.com (KnoxPortal) with ESMTPA id 20250915040754epcas2p2d715ac493a50a7714136e155fdb65d58~lWSvahKut3151431514epcas2p2L; Mon, 15 Sep 2025 04:07:54 +0000 (GMT) Received: from asswp60 (unknown [10.229.9.60]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250915040754epsmtip17187765a3f687c1a8002e9249582510c~lWSvU1VZ00190301903epsmtip1f; Mon, 15 Sep 2025 04:07:54 +0000 (GMT) From: Shin Son To: Bartlomiej Zolnierkiewicz , Krzysztof Kozlowski , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Conor Dooley , Alim Akhtar , Henrik Grimler Cc: Shin Son , linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/3] thermal: exynos_tmu: Support new hardware and update TMU interface Date: Mon, 15 Sep 2025 13:07:14 +0900 Message-ID: <20250915040715.486733-3-shin.son@samsung.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250915040715.486733-1-shin.son@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250915040754epcas2p2d715ac493a50a7714136e155fdb65d58 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P cpgsPolicy: CPGSC10-234,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250915040754epcas2p2d715ac493a50a7714136e155fdb65d58 References: <20250915040715.486733-1-shin.son@samsung.com> The Exynos tmu driver's private data structure has been extended to support the exynosautov920 hardware, which requires per-sensor interrupt enablement and dual-zone handling: - Add 'slope_comp' : compensation parameter below 25 degrees. - Add 'calib_temp' : stores the fused calibaration temperature. - Add 'tz_count' : reflects the new 1:2 hardware-to-thermal-zone ratio. - Add 'valid_sensor_bitmap' : bitmap to enable interrupts for each valid sensor. - Rename 'tzd' -> 'tzd_array' to register multiple thermal zones. Since splitting this patch causes runtime errors during temperature emulation or problems where the read temperature feature fails to retrieve values, I have submitted it as a single commit. To add support for the exynosautov920 to the exisiting TMU interface, the following changes are included: 1. Simplify "temp_to_code" and "code_to_temp" to one computation path by normalizing calib_temp. 2. Loop over 'tz_count' in critical-point setup. 3. Introduce 'update_con_reg' for exynosautov920 control-register updates. 4. Add exynosautov920-specific branch in 'exynos_tmu_update_temp' function. 5. Skip high & low temperature threshold setup in exynosautov920. 6. Enable interrupts via bitmap in 'exynosautov920_tmu_set_crit_temp'. 7. Initialize all new members during 'exynosautov920_tmu_initialize'. 8. Clear IRQs by iterating the bitamp in exynosautov920. 9. Register each zone with 'devm_thermal_of_zone_register()' based on 'tz_count'. Signed-off-by: Shin Son --- drivers/thermal/samsung/exynos_tmu.c | 324 ++++++++++++++++++++++++--- 1 file changed, 287 insertions(+), 37 deletions(-) diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung= /exynos_tmu.c index 47a99b3c5395..e3e630c16469 100644 --- a/drivers/thermal/samsung/exynos_tmu.c +++ b/drivers/thermal/samsung/exynos_tmu.c @@ -121,8 +121,52 @@ =20 #define EXYNOS_NOISE_CANCEL_MODE 4 =20 +/* ExynosAutov920 specific registers */ +#define EXYNOSAUTOV920_SLOPE_COMP 25 +#define EXYNOSAUTOV920_SLOPE_COMP_MASK 0xf +#define EXYNOSAUTOV920_CALIB_SEL_TEMP 30 +#define EXYNOSAUTOV920_CALIB_SEL_TEMP_MASK 0x2 + +#define EXYNOSAUTOV920_SENSOR0_TRIM_INFO 0x10 +#define EXYNOSAUTOV920_TRIM_MASK 0x1ff +#define EXYNOSAUTOV920_TRIMINFO_25_SHIFT 0 +#define EXYNOSAUTOV920_TRIMINFO_85_SHIFT 9 + +#define EXYNOSAUTOV920_TMU_REG_TRIMINFO2 0x04 +#define EXYNOSAUTOV920_MAX_SENSOR_NUMBER 16 + +#define EXYNOSAUTOV920_TMU_REG_THRESHOLD(p) (((p)) * 0x50 + 0x00d0) +#define EXYNOSAUTOV920_TMU_REG_INTEN(p) (((p)) * 0x50 + 0x00f0) +#define EXYNOSAUTOV920_TMU_REG_INT_PEND(p) (((p)) * 0x50 + 0x00f8) + +#define EXYNOSAUTOV920_CURRENT_TEMP_P1_P0 0x084 +#define EXYNOSAUTOV920_TMU_REG_EMUL_CON 0x0b0 + +#define EXYNOSAUTOV920_TMU_REG_CONTROL 0x50 +#define EXYNOSAUTOV920_TMU_REG_CONTROL1 0x54 +#define EXYNOSAUTOV920_TMU_REG_AVG_CONTROL 0x58 +#define EXYNOSAUTOV920_TMU_SAMPLING_INTERVAL 0x70 +#define EXYNOSAUTOV920_TMU_REG_COUNTER_VALUE0 0x74 +#define EXYNOSAUTOV920_TMU_REG_COUNTER_VALUE1 0x78 + +#define EXYNOSAUTOV920_TMU_T_BUF_VREF_SEL_SHIFT 8 +#define EXYNOSAUTOV920_TMU_T_BUF_VREF_SEL_MASK 0x1f +#define EXYNOSAUTOV920_TMU_T_BUF_SLOPE_SEL_SHIFT 3 +#define EXYNOSAUTOV920_TMU_T_BUF_SLOPE_SEL_MASK 0xf +#define EXYNOSAUTOV920_TMU_NUM_PROBE_MASK 0xf +#define EXYNOSAUTOV920_TMU_NUM_PROBE_SHIFT 16 +#define EXYNOSAUTOV920_TMU_LPI_MODE_MASK 1 +#define EXYNOSAUTOV920_TMU_LPI_MODE_SHIFT 10 + +#define EXYNOSAUTOV920_TMU_AVG_CON_UPDATE 0x0008011a +#define EXYNOSAUTOV920_TMU_COUNTER_VALUE0_UPDATE 0x030003c0 +#define EXYNOSAUTOV920_TMU_COUNTER_VALUE1_UPDATE 0x03c0004d + #define MCELSIUS 1000 =20 +#define EXYNOS_DEFAULT_TZ_COUNT 1 +#define EXYNOS_MAX_TZ_COUNT 2 + enum soc_type { SOC_ARCH_EXYNOS3250 =3D 1, SOC_ARCH_EXYNOS4210, @@ -133,6 +177,7 @@ enum soc_type { SOC_ARCH_EXYNOS5420_TRIMINFO, SOC_ARCH_EXYNOS5433, SOC_ARCH_EXYNOS7, + SOC_ARCH_EXYNOSAUTOV920, }; =20 /** @@ -150,6 +195,8 @@ enum soc_type { * @efuse_value: SoC defined fuse value * @min_efuse_value: minimum valid trimming data * @max_efuse_value: maximum valid trimming data + * @slope_comp: allocated value of the slope compensation. + * @calib_temp: calibration temperature of the TMU. * @temp_error1: fused value of the first point trim. * @temp_error2: fused value of the second point trim. * @gain: gain of amplifier in the positive-TC generator block @@ -157,7 +204,9 @@ enum soc_type { * @reference_voltage: reference voltage of amplifier * in the positive-TC generator block * 0 < reference_voltage <=3D 31 - * @tzd: pointer to thermal_zone_device structure + * @tz_count: The allocated number of the thermal zone + * @tzd_array: pointer array of thermal_zone_device structure + * @valid_sensor_bitmap: The enabled sensor of the TMU device * @enabled: current status of TMU device * @tmu_set_low_temp: SoC specific method to set trip (falling threshold) * @tmu_set_high_temp: SoC specific method to set trip (rising threshold) @@ -181,10 +230,14 @@ struct exynos_tmu_data { u32 efuse_value; u32 min_efuse_value; u32 max_efuse_value; + u16 slope_comp; + u16 calib_temp; u16 temp_error1, temp_error2; u8 gain; u8 reference_voltage; - struct thermal_zone_device *tzd; + u8 tz_count; + unsigned long valid_sensor_bitmap; + struct thermal_zone_device *tzd_array[EXYNOS_MAX_TZ_COUNT]; bool enabled; =20 void (*tmu_set_low_temp)(struct exynos_tmu_data *data, u8 temp); @@ -205,13 +258,20 @@ struct exynos_tmu_data { */ static int temp_to_code(struct exynos_tmu_data *data, u8 temp) { + s32 temp_diff, code; + if (data->cal_type =3D=3D TYPE_ONE_POINT_TRIMMING) return temp + data->temp_error1 - EXYNOS_FIRST_POINT_TRIM; =20 - return (temp - EXYNOS_FIRST_POINT_TRIM) * - (data->temp_error2 - data->temp_error1) / - (EXYNOS_SECOND_POINT_TRIM - EXYNOS_FIRST_POINT_TRIM) + - data->temp_error1; + temp_diff =3D temp - EXYNOS_FIRST_POINT_TRIM; + + code =3D temp_diff * (data->temp_error2 - data->temp_error1) * MCELSIUS / + (data->calib_temp - EXYNOS_FIRST_POINT_TRIM); + + if (data->soc =3D=3D SOC_ARCH_EXYNOSAUTOV920 && temp_diff < 0) + code =3D code * (57 + data->slope_comp) / 65; + + return code / MCELSIUS + data->temp_error1; } =20 /* @@ -220,13 +280,20 @@ static int temp_to_code(struct exynos_tmu_data *data,= u8 temp) */ static int code_to_temp(struct exynos_tmu_data *data, u16 temp_code) { + s32 code_diff, temp; + if (data->cal_type =3D=3D TYPE_ONE_POINT_TRIMMING) return temp_code - data->temp_error1 + EXYNOS_FIRST_POINT_TRIM; =20 - return (temp_code - data->temp_error1) * - (EXYNOS_SECOND_POINT_TRIM - EXYNOS_FIRST_POINT_TRIM) / - (data->temp_error2 - data->temp_error1) + - EXYNOS_FIRST_POINT_TRIM; + code_diff =3D temp_code - data->temp_error1; + + temp =3D code_diff * (data->calib_temp - EXYNOS_FIRST_POINT_TRIM) * MCELS= IUS / + (data->temp_error2 - data->temp_error1); + + if (data->soc =3D=3D SOC_ARCH_EXYNOSAUTOV920 && code_diff < 0) + temp =3D temp * 65 / (57 + data->slope_comp); + + return temp / MCELSIUS + EXYNOS_FIRST_POINT_TRIM; } =20 static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_inf= o) @@ -262,6 +329,9 @@ static int exynos_tmu_initialize(struct platform_device= *pdev) clk_enable(data->clk_sec); =20 status =3D readb(data->base + EXYNOS_TMU_REG_STATUS); + if (data->soc =3D=3D SOC_ARCH_EXYNOSAUTOV920) + status =3D readl(data->base + EXYNOS_TMU_REG_TRIMINFO); + if (!status) { ret =3D -EBUSY; } else { @@ -280,27 +350,31 @@ static int exynos_tmu_initialize(struct platform_devi= ce *pdev) static int exynos_thermal_zone_configure(struct platform_device *pdev) { struct exynos_tmu_data *data =3D platform_get_drvdata(pdev); - struct thermal_zone_device *tzd =3D data->tzd; - int ret, temp; + struct thermal_zone_device *tzd; + int ret, temp, idx; =20 - ret =3D thermal_zone_get_crit_temp(tzd, &temp); - if (ret) { - /* FIXME: Remove this special case */ - if (data->soc =3D=3D SOC_ARCH_EXYNOS5433) - return 0; + for (idx =3D 0; idx < data->tz_count; ++idx) { + tzd =3D data->tzd_array[idx]; =20 - dev_err(&pdev->dev, - "No CRITICAL trip point defined in device tree!\n"); - return ret; - } + ret =3D thermal_zone_get_crit_temp(tzd, &temp); + if (ret) { + /* FIXME: Remove this special case */ + if (data->soc =3D=3D SOC_ARCH_EXYNOS5433) + return 0; =20 - mutex_lock(&data->lock); - clk_enable(data->clk); + dev_err(&pdev->dev, + "No CRITICAL trip point defined in device tree!\n"); + return ret; + } =20 - data->tmu_set_crit_temp(data, temp / MCELSIUS); + mutex_lock(&data->lock); + clk_enable(data->clk); =20 - clk_disable(data->clk); - mutex_unlock(&data->lock); + data->tmu_set_crit_temp(data, temp / MCELSIUS); + + clk_disable(data->clk); + mutex_unlock(&data->lock); + } =20 return 0; } @@ -323,6 +397,38 @@ static u32 get_con_reg(struct exynos_tmu_data *data, u= 32 con) return con; } =20 +static void update_con_reg(struct exynos_tmu_data *data) +{ + u32 val, t_buf_vref_sel, t_buf_slope_sel; + + val =3D readl(data->base + EXYNOS_TMU_REG_TRIMINFO); + t_buf_vref_sel =3D (val >> EXYNOSAUTOV920_TMU_T_BUF_VREF_SEL_SHIFT) + & EXYNOSAUTOV920_TMU_T_BUF_VREF_SEL_MASK; + t_buf_slope_sel =3D (val >> EXYNOSAUTOV920_TMU_T_BUF_SLOPE_SEL_SHIFT) + & EXYNOSAUTOV920_TMU_T_BUF_SLOPE_SEL_MASK; + + val =3D readl(data->base + EXYNOSAUTOV920_TMU_REG_CONTROL); + val &=3D ~(EXYNOS_TMU_REF_VOLTAGE_MASK << EXYNOS_TMU_REF_VOLTAGE_SHIFT); + val |=3D (t_buf_vref_sel << EXYNOS_TMU_REF_VOLTAGE_SHIFT); + val &=3D ~(EXYNOS_TMU_BUF_SLOPE_SEL_MASK << EXYNOS_TMU_BUF_SLOPE_SEL_SHIF= T); + val |=3D (t_buf_slope_sel << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT); + writel(val, data->base + EXYNOSAUTOV920_TMU_REG_CONTROL); + + val =3D readl(data->base + EXYNOSAUTOV920_TMU_REG_CONTROL1); + val &=3D ~(EXYNOSAUTOV920_TMU_NUM_PROBE_MASK << EXYNOSAUTOV920_TMU_NUM_PR= OBE_SHIFT); + val &=3D ~(EXYNOSAUTOV920_TMU_LPI_MODE_MASK << EXYNOSAUTOV920_TMU_LPI_MOD= E_SHIFT); + val |=3D (find_last_bit(&data->valid_sensor_bitmap, EXYNOSAUTOV920_MAX_SE= NSOR_NUMBER) + << EXYNOSAUTOV920_TMU_NUM_PROBE_SHIFT); + writel(val, data->base + EXYNOSAUTOV920_TMU_REG_CONTROL1); + + writel(1, data->base + EXYNOSAUTOV920_TMU_SAMPLING_INTERVAL); + writel(EXYNOSAUTOV920_TMU_AVG_CON_UPDATE, data->base + EXYNOSAUTOV920_TMU= _REG_AVG_CONTROL); + writel(EXYNOSAUTOV920_TMU_COUNTER_VALUE0_UPDATE, + data->base + EXYNOSAUTOV920_TMU_REG_COUNTER_VALUE0); + writel(EXYNOSAUTOV920_TMU_COUNTER_VALUE1_UPDATE, + data->base + EXYNOSAUTOV920_TMU_REG_COUNTER_VALUE1); +} + static void exynos_tmu_control(struct platform_device *pdev, bool on) { struct exynos_tmu_data *data =3D platform_get_drvdata(pdev); @@ -354,9 +460,8 @@ static void exynos_tmu_update_temp(struct exynos_tmu_da= ta *data, int reg_off, u16 tmu_temp_mask; u32 th; =20 - tmu_temp_mask =3D - (data->soc =3D=3D SOC_ARCH_EXYNOS7) ? EXYNOS7_TMU_TEMP_MASK - : EXYNOS_TMU_TEMP_MASK; + tmu_temp_mask =3D (data->soc =3D=3D SOC_ARCH_EXYNOS7 || data->soc =3D=3D = SOC_ARCH_EXYNOSAUTOV920) + ? EXYNOS7_TMU_TEMP_MASK : EXYNOS_TMU_TEMP_MASK; =20 th =3D readl(data->base + reg_off); th &=3D ~(tmu_temp_mask << bit_off); @@ -582,6 +687,65 @@ static void exynos7_tmu_initialize(struct platform_dev= ice *pdev) sanitize_temp_error(data, trim_info); } =20 +static void exynosautov920_tmu_set_low_temp(struct exynos_tmu_data *data, = u8 temp) +{ + /* + * Failing thresholds are not supported on Exynosautov920. + * We use polling instead. + */ +} + +static void exynosautov920_tmu_set_high_temp(struct exynos_tmu_data *data,= u8 temp) +{ + /* + * Rising thresholds are not supported on Exynosautov920. + * We use polling instead. + */ +} + +static void exynosautov920_tmu_disable_low(struct exynos_tmu_data *data) +{ + /* Again, this is handled by polling. */ +} + +static void exynosautov920_tmu_disable_high(struct exynos_tmu_data *data) +{ + /* Again, this is handled by polling. */ +} + +static void exynosautov920_tmu_set_crit_temp(struct exynos_tmu_data *data,= u8 temp) +{ + unsigned int idx; + + for_each_set_bit(idx, &data->valid_sensor_bitmap, EXYNOSAUTOV920_MAX_SENS= OR_NUMBER) { + exynos_tmu_update_temp(data, EXYNOSAUTOV920_TMU_REG_THRESHOLD(idx), 16, = temp); + exynos_tmu_update_bit(data, EXYNOSAUTOV920_TMU_REG_INTEN(idx), 7, true); + } +} + +static void exynosautov920_tmu_initialize(struct platform_device *pdev) +{ + struct exynos_tmu_data *data =3D platform_get_drvdata(pdev); + unsigned int val; + + data->tmu_control(pdev, false); + + update_con_reg(data); + + val =3D readl(data->base + EXYNOS_TMU_REG_TRIMINFO); + data->cal_type =3D TYPE_TWO_POINT_TRIMMING; + data->slope_comp =3D (val >> EXYNOSAUTOV920_SLOPE_COMP) & EXYNOSAUTOV920_= SLOPE_COMP_MASK; + + val =3D readl(data->base + EXYNOSAUTOV920_SENSOR0_TRIM_INFO); + data->temp_error1 =3D (val >> EXYNOSAUTOV920_TRIMINFO_25_SHIFT) & EXYNOSA= UTOV920_TRIM_MASK; + data->temp_error2 =3D (val >> EXYNOSAUTOV920_TRIMINFO_85_SHIFT) & EXYNOSA= UTOV920_TRIM_MASK; + + val =3D readl(data->base + EXYNOSAUTOV920_TMU_REG_TRIMINFO2); + val =3D (val >> EXYNOSAUTOV920_CALIB_SEL_TEMP) & EXYNOSAUTOV920_CALIB_SEL= _TEMP_MASK; + + data->calib_temp =3D (EXYNOS_SECOND_POINT_TRIM + (20 * val)); +} + static void exynos4210_tmu_control(struct platform_device *pdev, bool on) { struct exynos_tmu_data *data =3D platform_get_drvdata(pdev); @@ -633,6 +797,24 @@ static void exynos7_tmu_control(struct platform_device= *pdev, bool on) writel(con, data->base + EXYNOS_TMU_REG_CONTROL); } =20 +static void exynosautov920_tmu_control(struct platform_device *pdev, bool = on) +{ + struct exynos_tmu_data *data =3D platform_get_drvdata(pdev); + unsigned int con; + + con =3D readl(data->base + EXYNOSAUTOV920_TMU_REG_CONTROL); + + if (on) { + con |=3D BIT(EXYNOS_TMU_THERM_TRIP_EN_SHIFT); + con |=3D BIT(EXYNOS_TMU_CORE_EN_SHIFT); + } else { + con &=3D ~BIT(EXYNOS_TMU_THERM_TRIP_EN_SHIFT); + con &=3D ~BIT(EXYNOS_TMU_CORE_EN_SHIFT); + } + + writel(con, data->base + EXYNOSAUTOV920_TMU_REG_CONTROL); +} + static int exynos_get_temp(struct thermal_zone_device *tz, int *temp) { struct exynos_tmu_data *data =3D thermal_zone_device_priv(tz); @@ -671,7 +853,7 @@ static u32 get_emul_con_reg(struct exynos_tmu_data *dat= a, unsigned int val, =20 val &=3D ~(EXYNOS_EMUL_TIME_MASK << EXYNOS_EMUL_TIME_SHIFT); val |=3D (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT); - if (data->soc =3D=3D SOC_ARCH_EXYNOS7) { + if (data->soc =3D=3D SOC_ARCH_EXYNOS7 || data->soc =3D=3D SOC_ARCH_EXYNO= SAUTOV920) { val &=3D ~(EXYNOS7_EMUL_DATA_MASK << EXYNOS7_EMUL_DATA_SHIFT); val |=3D (temp_to_code(data, temp) << @@ -703,6 +885,8 @@ static void exynos4412_tmu_set_emulation(struct exynos_= tmu_data *data, emul_con =3D EXYNOS5433_TMU_EMUL_CON; else if (data->soc =3D=3D SOC_ARCH_EXYNOS7) emul_con =3D EXYNOS7_TMU_REG_EMUL_CON; + else if (data->soc =3D=3D SOC_ARCH_EXYNOSAUTOV920) + emul_con =3D EXYNOSAUTOV920_TMU_REG_EMUL_CON; else emul_con =3D EXYNOS_EMUL_CON; =20 @@ -756,11 +940,19 @@ static int exynos7_tmu_read(struct exynos_tmu_data *d= ata) EXYNOS7_TMU_TEMP_MASK; } =20 +static int exynosautov920_tmu_read(struct exynos_tmu_data *data) +{ + return readw(data->base + EXYNOSAUTOV920_CURRENT_TEMP_P1_P0) & + EXYNOS7_TMU_TEMP_MASK; +} + static irqreturn_t exynos_tmu_threaded_irq(int irq, void *id) { struct exynos_tmu_data *data =3D id; + int idx; =20 - thermal_zone_device_update(data->tzd, THERMAL_EVENT_UNSPECIFIED); + for (idx =3D 0; idx < data->tz_count; ++idx) + thermal_zone_device_update(data->tzd_array[idx], THERMAL_EVENT_UNSPECIFI= ED); =20 mutex_lock(&data->lock); clk_enable(data->clk); @@ -805,6 +997,16 @@ static void exynos4210_tmu_clear_irqs(struct exynos_tm= u_data *data) writel(val_irq, data->base + tmu_intclear); } =20 +static void exynosautov920_tmu_clear_irqs(struct exynos_tmu_data *data) +{ + unsigned int idx, val_irq; + + for_each_set_bit(idx, &data->valid_sensor_bitmap, EXYNOSAUTOV920_MAX_SENS= OR_NUMBER) { + val_irq =3D readl(data->base + EXYNOSAUTOV920_TMU_REG_INT_PEND(idx)); + writel(val_irq, data->base + EXYNOSAUTOV920_TMU_REG_INT_PEND(idx)); + } +} + static const struct of_device_id exynos_tmu_match[] =3D { { .compatible =3D "samsung,exynos3250-tmu", @@ -833,6 +1035,9 @@ static const struct of_device_id exynos_tmu_match[] = =3D { }, { .compatible =3D "samsung,exynos7-tmu", .data =3D (const void *)SOC_ARCH_EXYNOS7, + }, { + .compatible =3D "samsung,exynosautov920-tmu", + .data =3D (const void *)SOC_ARCH_EXYNOSAUTOV920, }, { }, }; @@ -865,6 +1070,10 @@ static int exynos_map_dt_data(struct platform_device = *pdev) =20 data->soc =3D (uintptr_t)of_device_get_match_data(&pdev->dev); =20 + data->tz_count =3D EXYNOS_DEFAULT_TZ_COUNT; + + data->calib_temp =3D EXYNOS_SECOND_POINT_TRIM; + switch (data->soc) { case SOC_ARCH_EXYNOS4210: data->tmu_set_low_temp =3D exynos4210_tmu_set_low_temp; @@ -945,6 +1154,19 @@ static int exynos_map_dt_data(struct platform_device = *pdev) data->min_efuse_value =3D 15; data->max_efuse_value =3D 100; break; + case SOC_ARCH_EXYNOSAUTOV920: + data->tmu_set_low_temp =3D exynosautov920_tmu_set_low_temp; + data->tmu_set_high_temp =3D exynosautov920_tmu_set_high_temp; + data->tmu_disable_low =3D exynosautov920_tmu_disable_low; + data->tmu_disable_high =3D exynosautov920_tmu_disable_high; + data->tmu_set_crit_temp =3D exynosautov920_tmu_set_crit_temp; + data->tmu_initialize =3D exynosautov920_tmu_initialize; + data->tmu_control =3D exynosautov920_tmu_control; + data->tmu_read =3D exynosautov920_tmu_read; + data->tmu_set_emulation =3D exynos4412_tmu_set_emulation; + data->tmu_clear_irqs =3D exynosautov920_tmu_clear_irqs; + data->tz_count =3D EXYNOS_MAX_TZ_COUNT; + break; default: dev_err(&pdev->dev, "Platform not supported\n"); return -EINVAL; @@ -952,6 +1174,31 @@ static int exynos_map_dt_data(struct platform_device = *pdev) =20 data->cal_type =3D TYPE_ONE_POINT_TRIMMING; =20 + if (data->soc =3D=3D SOC_ARCH_EXYNOSAUTOV920) { + const char *samsung_prop_name =3D "samsung,hw-sensor-indices"; + unsigned int *sensor_idx; + int i, count; + + count =3D device_property_count_u32(&pdev->dev, samsung_prop_name); + if (count < 0) { + dev_err(&pdev->dev, "failed to get count of %s\n", samsung_prop_name); + return -ENODEV; + } + + sensor_idx =3D kmalloc_array(count, sizeof(*sensor_idx), GFP_KERNEL); + if (!sensor_idx) + return -ENOMEM; + + if (device_property_read_u32_array(&pdev->dev, samsung_prop_name, + sensor_idx, count)) { + dev_err(&pdev->dev, "failed to read array from %s\n", samsung_prop_name= ); + return -ENODEV; + } + + for (i =3D 0; i < count; ++i) + __set_bit(sensor_idx[i], &data->valid_sensor_bitmap); + } + /* * Check if the TMU shares some registers and then try to map the * memory of common registers. @@ -1006,7 +1253,7 @@ static int exynos_tmu_probe(struct platform_device *p= dev) { struct device *dev =3D &pdev->dev; struct exynos_tmu_data *data; - int ret; + int ret, idx; =20 data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); if (!data) @@ -1084,11 +1331,14 @@ static int exynos_tmu_probe(struct platform_device = *pdev) goto err_sclk; } =20 - data->tzd =3D devm_thermal_of_zone_register(dev, 0, data, - &exynos_sensor_ops); - if (IS_ERR(data->tzd)) { - ret =3D dev_err_probe(dev, PTR_ERR(data->tzd), "Failed to register senso= r\n"); - goto err_sclk; + for (idx =3D 0; idx < data->tz_count; ++idx) { + data->tzd_array[idx] =3D devm_thermal_of_zone_register(dev, idx, data, + &exynos_sensor_ops); + if (IS_ERR(data->tzd_array[idx])) { + ret =3D dev_err_probe(dev, PTR_ERR(data->tzd_array[idx]), + "Failed to register sensor\n"); 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Mon, 15 Sep 2025 04:08:02 +0000 (GMT) From: Shin Son To: Bartlomiej Zolnierkiewicz , Krzysztof Kozlowski , "Rafael J . Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Conor Dooley , Alim Akhtar , Henrik Grimler Cc: Shin Son , linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/3] arm64: dts: exynosautov920: Add tmu hardware binding Date: Mon, 15 Sep 2025 13:07:15 +0900 Message-ID: <20250915040715.486733-4-shin.son@samsung.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250915040715.486733-1-shin.son@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250915040802epcas2p3bcc88e1958bf0f6cf4133e687c54b81c X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: AUTO_CONFIDENTIAL CMS-TYPE: 102P cpgsPolicy: CPGSC10-234,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250915040802epcas2p3bcc88e1958bf0f6cf4133e687c54b81c References: <20250915040715.486733-1-shin.son@samsung.com> Create a new exynosautov920-tmu.dtsi describing new TMU hardware and include it from exynosautov920.dtsi. The exynosautov920-tmu node uses the misc clock as its source and exposes new DT property: - samsung,hw-sensor-indices: List of hardware sensor indices physically connected to this TMU block. This TMU binding defines six thermal zones with a critical trip point at 125 degrees: tmu_top : cpucl0-0, cpucl1 tmu_sub0: cpucl0-1, cpucl2 tmu_sub1: g3d, npu Signed-off-by: Shin Son --- .../boot/dts/exynos/exynosautov920-tmu.dtsi | 97 +++++++++++++++++++ .../arm64/boot/dts/exynos/exynosautov920.dtsi | 31 ++++++ 2 files changed, 128 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/exynosautov920-tmu.dtsi diff --git a/arch/arm64/boot/dts/exynos/exynosautov920-tmu.dtsi b/arch/arm6= 4/boot/dts/exynos/exynosautov920-tmu.dtsi new file mode 100644 index 000000000000..eb1864e69bef --- /dev/null +++ b/arch/arm64/boot/dts/exynos/exynosautov920-tmu.dtsi @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's ExynosAuto920 TMU configurations device tree source + * + * Copyright (c) 2020 Samsung Electronics Co., Ltd. + * + * Samsung's ExynosAuto920 SoC TMU(Thermal Managemenut Unit) are listed as + * device tree nodes in this file. + */ + +/ { + thermal-zones { + cpucl0-0-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 0>; + + trips { + cpucl0_0_critical: cpucl0-0-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpucl0-1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub0 0>; + + trips { + cpucl0_1_critical: cpucl0-1-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpucl1-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_top 1>; + + trips { + cpucl1_critical: cpucl1-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + cpucl2-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub0 1>; + + trips { + cpucl2_critical: cpucl2-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + g3d-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub1 0>; + + trips { + g3d_critical: g3d-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + + npu-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tmu_sub1 1>; + + trips { + npu_critical: npu-critical { + temperature =3D <125000>; /* millicelsius */ + hysteresis =3D <0>; /* millicelsius */ + type =3D "critical"; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/bo= ot/dts/exynos/exynosautov920.dtsi index 0fdf2062930a..642f766d4106 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi @@ -330,6 +330,36 @@ watchdog_cl1: watchdog@10070000 { samsung,cluster-index =3D <1>; }; =20 + tmu_top: tmu@100a0000 { + compatible =3D "samsung,exynosautov920-tmu"; + reg =3D <0x100A0000 0x1000>; + interrupts =3D ; + #thermal-sensor-cells =3D <1>; + clocks =3D <&cmu_misc CLK_DOUT_MISC_NOCP>; + clock-names =3D "tmu_apbif"; + samsung,hw-sensor-indices =3D <1 2 3 4 5 6 7 8 9 10 11 12>; + }; + + tmu_sub0: tmu@100b0000 { + compatible =3D "samsung,exynosautov920-tmu"; + reg =3D <0x100B0000 0x1000>; + interrupts =3D ; + #thermal-sensor-cells =3D <1>; + clocks =3D <&cmu_misc CLK_DOUT_MISC_NOCP>; + clock-names =3D "tmu_apbif"; + samsung,hw-sensor-indices =3D <3 4 5 6 7 8 9 10>; + }; + + tmu_sub1: tmu@100c0000 { + compatible =3D "samsung,exynosautov920-tmu"; + reg =3D <0x100C0000 0x1000>; + interrupts =3D ; + #thermal-sensor-cells =3D <1>; + clocks =3D <&cmu_misc CLK_DOUT_MISC_NOCP>; + clock-names =3D "tmu_apbif"; + samsung,hw-sensor-indices =3D <1 2 3 4 6 7>; + }; + gic: interrupt-controller@10400000 { compatible =3D "arm,gic-v3"; #interrupt-cells =3D <3>; @@ -1507,3 +1537,4 @@ timer { }; =20 #include "exynosautov920-pinctrl.dtsi" +#include "exynosautov920-tmu.dtsi" --=20 2.50.1