From nobody Thu Oct 2 18:08:29 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5088822A1E1; Mon, 15 Sep 2025 03:02:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757905358; cv=none; b=QkIQr9IRaf2Us28n/6Y3t3saWTXG+dV5n53k9m2JgdQVDFRfibH4O9oT7g9Emq49/141d2EsImQE/quon9rv88cTbqiALfn6KhGs1MvZQk3IS+Wp6DalzIg4GEJzLtkpLWCifXhLER5cgbH7/L+6ghKhxcnRqIlEtZsc7rgvUHI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757905358; c=relaxed/simple; bh=FestdFsPRbuQOpG0IOjSEP5H4M+ZsZ5gjhElVGYF0s0=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=vB0cUHUKI600EUk6Bp1mBJei7/kcCF3eY8LbzZhJ8SDWrGmw7vKqlQmEUxeJEBlYedtNFS6VSlcFEePZrv8nERtpFPpWBW1PJUYOPfTi/M0offQWgI5rIG1pqTmVaqri9zmG0SkINB5WXjBGfNpXYzhnIYJzfu434hPH9Ziv3+4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=ckRM7Dz+; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="ckRM7Dz+" X-UUID: 69e61a8691e011f0b33aeb1e7f16c2b6-20250915 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:To:From; bh=Zq2gfn8d5RYuZ4H1kCO+wDGtqzkjbvPC2hL+uKq/iFs=; b=ckRM7Dz+UMz4Ga9Dq373V4RokVG4ei5laJy2ymw/CJWyD/rlQS4cUB1tMQQVp1nSMrC1BW8/VblnQLSWn8SZUYIcKyl8HcgXLH3qZ+WnRYVH/QJ6eSe6iTzprAS0AYWVH1hlDgMoFYJkv2AvHCxvnvxxu5ybLTh8etjCUCczK20=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.4,REQID:13e297fe-b75b-40f7-88b3-0fffa096a31d,IP:0,UR L:0,TC:0,Content:-5,EDM:25,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:20 X-CID-META: VersionHash:1ca6b93,CLOUDID:fbda50a9-24df-464e-9c88-e53ab7cf7153,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:-5,Content:0|15|50,EDM: 5,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,A V:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 69e61a8691e011f0b33aeb1e7f16c2b6-20250915 Received: from mtkmbs09n2.mediatek.inc [(172.21.101.94)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 311820843; Mon, 15 Sep 2025 11:02:28 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Mon, 15 Sep 2025 11:02:25 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Mon, 15 Sep 2025 11:02:26 +0800 From: Kyrie Wu To: Hans Verkuil , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Kyrie Wu , , , , , Subject: [PATCH v9 05/12] media: mediatek: jpeg: fix multi-core clk suspend and resume setting Date: Mon, 15 Sep 2025 11:02:04 +0800 Message-ID: <20250915030212.22078-6-kyrie.wu@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250915030212.22078-1-kyrie.wu@mediatek.com> References: <20250915030212.22078-1-kyrie.wu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" The suspend/resume callback function is defined in the dev_pm_ops structure, which is defined in platform_driver. For multiple-core architecture, each hardware driver will register a platform_driver structure, so it is necessary to add a suspend/resume callback function for each hardware to support this operation. Fixes: 934e8bccac95 ("mtk-jpegenc: support jpegenc multi-hardware") Fixes: 0fa49df4222f ("media: mtk-jpegdec: support jpegdec multi-hardware") Signed-off-by: Kyrie Wu --- .../platform/mediatek/jpeg/mtk_jpeg_core.c | 28 +++---- .../platform/mediatek/jpeg/mtk_jpeg_dec_hw.c | 75 ++++++++++++++++++- .../platform/mediatek/jpeg/mtk_jpeg_enc_hw.c | 75 ++++++++++++++++++- 3 files changed, 151 insertions(+), 27 deletions(-) diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c b/drivers= /media/platform/mediatek/jpeg/mtk_jpeg_core.c index 0d379a01f9a7..32b20d97a5e8 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_core.c @@ -1122,6 +1122,9 @@ static void mtk_jpeg_clk_on(struct mtk_jpeg_dev *jpeg) { int ret; =20 + if (jpeg->variant->multi_core) + return; + ret =3D clk_bulk_prepare_enable(jpeg->variant->num_clks, jpeg->variant->clks); if (ret) @@ -1130,6 +1133,9 @@ static void mtk_jpeg_clk_on(struct mtk_jpeg_dev *jpeg) =20 static void mtk_jpeg_clk_off(struct mtk_jpeg_dev *jpeg) { + if (jpeg->variant->multi_core) + return; + clk_bulk_disable_unprepare(jpeg->variant->num_clks, jpeg->variant->clks); } @@ -1659,13 +1665,6 @@ static void mtk_jpegenc_worker(struct work_struct *w= ork) goto enc_end; } =20 - ret =3D clk_prepare_enable(comp_jpeg[hw_id]->venc_clk.clks->clk); - if (ret) { - dev_err(jpeg->dev, "%s : %d, jpegenc clk_prepare_enable fail\n", - __func__, __LINE__); - goto enc_end; - } - v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); =20 @@ -1763,20 +1762,13 @@ static void mtk_jpegdec_worker(struct work_struct *= work) jpeg_dst_buf->frame_num =3D ctx->total_frame_num; =20 mtk_jpegdec_set_hw_param(ctx, hw_id, src_buf, dst_buf); - ret =3D pm_runtime_get_sync(comp_jpeg[hw_id]->dev); + ret =3D pm_runtime_resume_and_get(comp_jpeg[hw_id]->dev); if (ret < 0) { dev_err(jpeg->dev, "%s : %d, pm_runtime_get_sync fail !!!\n", __func__, __LINE__); goto dec_end; } =20 - ret =3D clk_prepare_enable(comp_jpeg[hw_id]->jdec_clk.clks->clk); - if (ret) { - dev_err(jpeg->dev, "%s : %d, jpegdec clk_prepare_enable fail\n", - __func__, __LINE__); - goto clk_end; - } - v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); =20 @@ -1786,7 +1778,7 @@ static void mtk_jpegdec_worker(struct work_struct *wo= rk) &dst_buf->vb2_buf, &fb)) { dev_err(jpeg->dev, "%s : %d, mtk_jpeg_set_dec_dst fail\n", __func__, __LINE__); - goto setdst_end; + goto set_dst_fail; } =20 schedule_delayed_work(&comp_jpeg[hw_id]->job_timeout_work, @@ -1808,9 +1800,7 @@ static void mtk_jpegdec_worker(struct work_struct *wo= rk) =20 return; =20 -setdst_end: - clk_disable_unprepare(comp_jpeg[hw_id]->jdec_clk.clks->clk); -clk_end: +set_dst_fail: pm_runtime_put(comp_jpeg[hw_id]->dev); dec_end: v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c b/drive= rs/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c index 84d12eea35f7..5f1557dafad6 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_dec_hw.c @@ -540,14 +540,13 @@ static void mtk_jpegdec_timeout_work(struct work_stru= ct *work) v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true); =20 mtk_jpeg_dec_reset(cjpeg->reg_base); - clk_disable_unprepare(cjpeg->jdec_clk.clks->clk); - pm_runtime_put(cjpeg->dev); cjpeg->hw_state =3D MTK_JPEG_HW_IDLE; atomic_inc(&master_jpeg->hw_rdy); wake_up(&master_jpeg->hw_wq); v4l2_m2m_buf_done(src_buf, buf_state); mtk_jpegdec_put_buf(cjpeg); jpeg_buf_queue_dec(ctx); + pm_runtime_put(cjpeg->dev); } =20 static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq, void *priv) @@ -589,12 +588,11 @@ static irqreturn_t mtk_jpegdec_hw_irq_handler(int irq= , void *priv) v4l2_m2m_buf_done(src_buf, buf_state); mtk_jpegdec_put_buf(jpeg); jpeg_buf_queue_dec(ctx); - pm_runtime_put(ctx->jpeg->dev); - clk_disable_unprepare(jpeg->jdec_clk.clks->clk); =20 jpeg->hw_state =3D MTK_JPEG_HW_IDLE; wake_up(&master_jpeg->hw_wq); atomic_inc(&master_jpeg->hw_rdy); + pm_runtime_put(jpeg->dev); =20 return IRQ_HANDLED; } @@ -677,15 +675,84 @@ static int mtk_jpegdec_hw_probe(struct platform_devic= e *pdev) =20 platform_set_drvdata(pdev, dev); pm_runtime_enable(&pdev->dev); + ret =3D devm_clk_bulk_get(dev->dev, + jpegdec_clk->clk_num, + jpegdec_clk->clks); + if (ret) { + dev_err(&pdev->dev, "Failed to init clk\n"); + return ret; + } + + return 0; +} + +static void mtk_jpeg_clk_on(struct mtk_jpegdec_comp_dev *jpeg) +{ + int ret; + + ret =3D clk_bulk_prepare_enable(jpeg->jdec_clk.clk_num, + jpeg->jdec_clk.clks); + if (ret) + dev_err(jpeg->dev, "%s : %d, jpegdec clk_prepare_enable fail\n", + __func__, __LINE__); +} + +static void mtk_jpeg_clk_off(struct mtk_jpegdec_comp_dev *jpeg) +{ + clk_bulk_disable_unprepare(jpeg->jdec_clk.clk_num, + jpeg->jdec_clk.clks); +} + +static __maybe_unused int mtk_jpegdec_pm_suspend(struct device *dev) +{ + struct mtk_jpegdec_comp_dev *jpeg =3D dev_get_drvdata(dev); + + mtk_jpeg_clk_off(jpeg); =20 return 0; } =20 +static __maybe_unused int mtk_jpegdec_pm_resume(struct device *dev) +{ + struct mtk_jpegdec_comp_dev *jpeg =3D dev_get_drvdata(dev); + + mtk_jpeg_clk_on(jpeg); + + return 0; +} + +static __maybe_unused int mtk_jpegdec_suspend(struct device *dev) +{ + struct mtk_jpegdec_comp_dev *jpeg =3D dev_get_drvdata(dev); + + v4l2_m2m_suspend(jpeg->master_dev->m2m_dev); + return pm_runtime_force_suspend(dev); +} + +static __maybe_unused int mtk_jpegdec_resume(struct device *dev) +{ + struct mtk_jpegdec_comp_dev *jpeg =3D dev_get_drvdata(dev); + int ret; + + ret =3D pm_runtime_force_resume(dev); + if (ret < 0) + return ret; + + v4l2_m2m_resume(jpeg->master_dev->m2m_dev); + return ret; +} + +static const struct dev_pm_ops mtk_jpegdec_pm_ops =3D { + SET_SYSTEM_SLEEP_PM_OPS(mtk_jpegdec_suspend, mtk_jpegdec_resume) + SET_RUNTIME_PM_OPS(mtk_jpegdec_pm_suspend, mtk_jpegdec_pm_resume, NULL) +}; + static struct platform_driver mtk_jpegdec_hw_driver =3D { .probe =3D mtk_jpegdec_hw_probe, .driver =3D { .name =3D "mtk-jpegdec-hw", .of_match_table =3D mtk_jpegdec_hw_ids, + .pm =3D &mtk_jpegdec_pm_ops, }, }; =20 diff --git a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c b/drive= rs/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c index 625a0d350348..5fe709d4003a 100644 --- a/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c +++ b/drivers/media/platform/mediatek/jpeg/mtk_jpeg_enc_hw.c @@ -271,14 +271,13 @@ static void mtk_jpegenc_timeout_work(struct work_stru= ct *work) v4l2_m2m_buf_copy_metadata(src_buf, dst_buf, true); =20 mtk_jpeg_enc_reset(cjpeg->reg_base); - clk_disable_unprepare(cjpeg->venc_clk.clks->clk); - pm_runtime_put(cjpeg->dev); cjpeg->hw_state =3D MTK_JPEG_HW_IDLE; atomic_inc(&master_jpeg->hw_rdy); wake_up(&master_jpeg->hw_wq); v4l2_m2m_buf_done(src_buf, buf_state); mtk_jpegenc_put_buf(cjpeg); jpeg_buf_queue_dec(ctx); + pm_runtime_put(cjpeg->dev); } =20 static irqreturn_t mtk_jpegenc_hw_irq_handler(int irq, void *priv) @@ -313,12 +312,11 @@ static irqreturn_t mtk_jpegenc_hw_irq_handler(int irq= , void *priv) v4l2_m2m_buf_done(src_buf, buf_state); mtk_jpegenc_put_buf(jpeg); jpeg_buf_queue_dec(ctx); - pm_runtime_put(ctx->jpeg->dev); - clk_disable_unprepare(jpeg->venc_clk.clks->clk); =20 jpeg->hw_state =3D MTK_JPEG_HW_IDLE; wake_up(&master_jpeg->hw_wq); atomic_inc(&master_jpeg->hw_rdy); + pm_runtime_put(jpeg->dev); =20 return IRQ_HANDLED; } @@ -399,15 +397,84 @@ static int mtk_jpegenc_hw_probe(struct platform_devic= e *pdev) =20 platform_set_drvdata(pdev, dev); pm_runtime_enable(&pdev->dev); + ret =3D devm_clk_bulk_get(dev->dev, + jpegenc_clk->clk_num, + jpegenc_clk->clks); + if (ret) { + dev_err(&pdev->dev, "Failed to init clk\n"); + return ret; + } + + return 0; +} + +static void mtk_jpeg_clk_on(struct mtk_jpegenc_comp_dev *jpeg) +{ + int ret; + + ret =3D clk_bulk_prepare_enable(jpeg->venc_clk.clk_num, + jpeg->venc_clk.clks); + if (ret) + dev_err(jpeg->dev, "%s : %d, jpegenc clk_prepare_enable fail\n", + __func__, __LINE__); +} + +static void mtk_jpeg_clk_off(struct mtk_jpegenc_comp_dev *jpeg) +{ + clk_bulk_disable_unprepare(jpeg->venc_clk.clk_num, + jpeg->venc_clk.clks); +} + +static __maybe_unused int mtk_jpegenc_pm_suspend(struct device *dev) +{ + struct mtk_jpegenc_comp_dev *jpeg =3D dev_get_drvdata(dev); + + mtk_jpeg_clk_off(jpeg); =20 return 0; } =20 +static __maybe_unused int mtk_jpegenc_pm_resume(struct device *dev) +{ + struct mtk_jpegenc_comp_dev *jpeg =3D dev_get_drvdata(dev); + + mtk_jpeg_clk_on(jpeg); + + return 0; +} + +static __maybe_unused int mtk_jpegenc_suspend(struct device *dev) +{ + struct mtk_jpegenc_comp_dev *jpeg =3D dev_get_drvdata(dev); + + v4l2_m2m_suspend(jpeg->master_dev->m2m_dev); + return pm_runtime_force_suspend(dev); +} + +static __maybe_unused int mtk_jpegenc_resume(struct device *dev) +{ + struct mtk_jpegenc_comp_dev *jpeg =3D dev_get_drvdata(dev); + int ret; + + ret =3D pm_runtime_force_resume(dev); + if (ret < 0) + return ret; + + v4l2_m2m_resume(jpeg->master_dev->m2m_dev); + return ret; +} + +static const struct dev_pm_ops mtk_jpegenc_pm_ops =3D { + SET_SYSTEM_SLEEP_PM_OPS(mtk_jpegenc_suspend, mtk_jpegenc_resume) + SET_RUNTIME_PM_OPS(mtk_jpegenc_pm_suspend, mtk_jpegenc_pm_resume, NULL) +}; + static struct platform_driver mtk_jpegenc_hw_driver =3D { .probe =3D mtk_jpegenc_hw_probe, .driver =3D { .name =3D "mtk-jpegenc-hw", .of_match_table =3D mtk_jpegenc_drv_ids, + .pm =3D &mtk_jpegenc_pm_ops, }, }; =20 --=20 2.45.2