From nobody Thu Oct 2 17:02:09 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED8442F5469; Mon, 15 Sep 2025 08:50:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757926218; cv=none; b=MpkrBOdG820qzq5nD7NgiTCFZUwG+aExleRDp330iGFtOMypjJIwnrS0BeS6xYVjc7S+qLJpUgDzuSSHBJJKR/qEhvq4if6qM6P3RoBbOEqmL8z2jMo5+YYTKPeNcI8TV96WTVM7QIF8DA793po3vwOZesae0GSkBbBYTpVqtyw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757926218; c=relaxed/simple; bh=BeB7zw1Yr47qwTix1CPy5qpweNbSDIpz6FPY8JF38uY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=h1zaufd8t0nM1wG3b4fNx9yXa6++g3eJI52GS3wfg0DJdxaZwMhJqYYgtpdgPPkS3K7tm/QNV9HRwtImA5nYUZDHrfbGyxHVExA5OZb9Y782txa2/Co2GGLcNpE0pByTd9I0qE1CqljOx9xgKdiM9CzKbtrHEjtOVD48rGYtk+U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GtW/eqqH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GtW/eqqH" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4C38DC2BCAF; Mon, 15 Sep 2025 08:50:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1757926214; bh=BeB7zw1Yr47qwTix1CPy5qpweNbSDIpz6FPY8JF38uY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=GtW/eqqHcWMfuBt5NIeXV7+iQeOo2iS0uYe1NTnn5W3x5FO0PcRCyph/jznGySKK0 NUdElzPv0A+QAs+ziaY7mn25e8r6RhTCoqsy6WSW1SVWt9EcR5Hgn9sm95XAaAbivq R1lkIzOeaBu32YjyuodbDbx8Lo9uywGsskFP1rgYZEb/0Unr6TAobOYdl10niFjPVV E4pSOK6x7Ax5nXaZtjsVRQY9ftdX82qv8T8ciZl1d04Ji5EelZlI0Vo9PsEoYAh5X+ uG+bsFupJjndZ9F9XS2H9FtBtc56VUcsGSEjnJp6wKDmVtI223ZD0QUMKOauBBxIzT r+PSltpPheQiA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41D66CAC58E; Mon, 15 Sep 2025 08:50:14 +0000 (UTC) From: Fenglin Wu via B4 Relay Date: Mon, 15 Sep 2025 16:49:58 +0800 Subject: [PATCH v4 6/8] dt-bindings: soc: qcom,pmic-glink: Add charge limit nvmem properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250915-qcom_battmgr_update-v4-6-6f6464a41afe@oss.qualcomm.com> References: <20250915-qcom_battmgr_update-v4-0-6f6464a41afe@oss.qualcomm.com> In-Reply-To: <20250915-qcom_battmgr_update-v4-0-6f6464a41afe@oss.qualcomm.com> To: Sebastian Reichel , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heikki Krogerus , Greg Kroah-Hartman , Dmitry Baryshkov , Bryan O'Donoghue , Konrad Dybcio Cc: Subbaraman Narayanamurthy , David Collins , =?utf-8?q?Gy=C3=B6rgy_Kurucz?= , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, kernel@oss.qualcomm.com, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, Fenglin Wu , Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1757926212; l=1571; i=fenglin.wu@oss.qualcomm.com; s=20240327; h=from:subject:message-id; bh=r0dveNAduFjQEgggFyZyipCDUyI6ungTfqPcc80RgpY=; b=vTv8yPMPxWkB/XQII+CiZBVMu6B2WX4XZ1krRRGU4nWjaiZJhpzXimt6M8/MWqHaUx1u4VlU8 zY2ukDgtkDECHaQ2UA16dj81HIz35NOXBOmEgmMPLHCfE3kMPBLRsk1 X-Developer-Key: i=fenglin.wu@oss.qualcomm.com; a=ed25519; pk=BF8SA4IVDk8/EBCwlBehKtn2hp6kipuuAuDAHh9s+K4= X-Endpoint-Received: by B4 Relay for fenglin.wu@oss.qualcomm.com/20240327 with auth_id=406 X-Original-From: Fenglin Wu Reply-To: fenglin.wu@oss.qualcomm.com From: Fenglin Wu Add nvmem properties to retrieve charge control configurations from the PMIC SDAM registers. Acked-by: Rob Herring (Arm) Tested-by: Neil Armstrong # on Thinkpad T14S OL= ED Signed-off-by: Fenglin Wu --- .../devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml | 14 ++++++++++= ++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yam= l b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml index 4c9e78f29523e3d77aacb4299f64ab96f9b1a831..9d6db4825da389aa14d77f653d2= f8a3442e22162 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml @@ -55,6 +55,20 @@ properties: The array should contain a gpio entry for each PMIC Glink connector,= in reg order. It is defined that GPIO active level means "CC2" or Reversed/Flipped= orientation. =20 + nvmem-cells: + minItems: 3 + maxItems: 3 + description: + The nvmem cells contain the charge control settings, including the c= harge control + enable status, the battery state of charge (SoC) threshold for stopp= ing charging, + and the battery SoC delta required to restart charging. + + nvmem-cell-names: + items: + - const: charge_limit_en + - const: charge_limit_end + - const: charge_limit_delta + patternProperties: '^connector@\d$': $ref: /schemas/connector/usb-connector.yaml# --=20 2.34.1