From nobody Thu Oct 2 16:35:38 2025 Received: from sendmail.purelymail.com (sendmail.purelymail.com [34.202.193.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9F133019DA for ; Mon, 15 Sep 2025 12:47:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=34.202.193.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757940435; cv=none; b=oNXbLeRbsbvrz6i+9yy4E9KWpnk16R1IVojFR/6SSLT1Px+3PV6RKmgCBWZM//jeAhFOmDxvCk8xYzIJeCIs7zJG2fEsLiufFW8XufCvdPw9KGXU+zOmL0ZT1J7gMPGbZKeY2nu1kDS5zyt5/Km56aB/7cnqrAqb7deHxmwLtJ4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757940435; c=relaxed/simple; bh=irm5rOzkMCBKy8afw3JexKMiBbgIOkVmWCMIQ2l0hUY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Jc1SZllZlHCQmLPlZDzs4oet3FENeb5ihXf8tzGFOKGJu+qqQsKEEEQC2movkR/EZRW/s7TzgxeWMYGvlZ2muBU1YpBt9vZk8R9KBI4Fe09UuSFdbeYFDTClOCPH8mnBqTzY3jvzSXnRHEGig4nindzNh8W9/y++NfXgesq9H+c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=mentallysanemainliners.org; spf=pass smtp.mailfrom=mentallysanemainliners.org; dkim=pass (2048-bit key) header.d=purelymail.com header.i=@purelymail.com header.b=w508YE6u; arc=none smtp.client-ip=34.202.193.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=mentallysanemainliners.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mentallysanemainliners.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=purelymail.com header.i=@purelymail.com header.b="w508YE6u" Authentication-Results: purelymail.com; auth=pass DKIM-Signature: a=rsa-sha256; b=w508YE6uho32x7yE7/EJBlz8koT3SVa2CC+66Zgn5IwpQmySNfUD2ZfJwbFBkxQM8/C6rdlzbZwO4os4rYCikmo9NK5VnEg7aTqIToCZavahpCkVbfsEgomtNbKeeyX49mKmj1V5lfd8C2XHtAk4olDP3/zkM+iBBBk/CieHxETjcRZgjP0ojIBpT9CTfa8Fl0LYABIqmHmBnVdRQZ9c5WU7Amvn5725/7hAbIYe75uiIMSJ2k7zeXMMqNW+T/dGXb9vYjG3abowl/xUmY9S7Bg4ycXL3KEB2pymwAr5xKvrN11a2Rm2V3WMViQaFWwk1Iu1FuRo/5N23ppWHlAV/Q==; s=purelymail3; d=purelymail.com; v=1; bh=irm5rOzkMCBKy8afw3JexKMiBbgIOkVmWCMIQ2l0hUY=; h=Feedback-ID:Received:From:Date:Subject:To; Feedback-ID: 68247:10037:null:purelymail X-Pm-Original-To: linux-kernel@vger.kernel.org Received: by smtp.purelymail.com (Purelymail SMTP) with ESMTPSA id 1506483826; (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Mon, 15 Sep 2025 12:46:29 +0000 (UTC) From: Igor Belwon Date: Mon, 15 Sep 2025 14:46:23 +0200 Subject: [PATCH v3 1/4] dt-bindings: pinctrl: mediatek: Document MT6878 pin controller bindings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250915-mt6878-pinctrl-support-v3-1-593cc007d4cf@mentallysanemainliners.org> References: <20250915-mt6878-pinctrl-support-v3-0-593cc007d4cf@mentallysanemainliners.org> In-Reply-To: <20250915-mt6878-pinctrl-support-v3-0-593cc007d4cf@mentallysanemainliners.org> To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Sean Wang Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Igor Belwon X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1757940385; l=7159; i=igor.belwon@mentallysanemainliners.org; s=20250908; h=from:subject:message-id; bh=irm5rOzkMCBKy8afw3JexKMiBbgIOkVmWCMIQ2l0hUY=; b=kY5stO3TWCNOuMxLH3HOmWHosNYVTrd6ojPgwbhL4T3EnOKSMWAi11YFYNfSdBNc4j6tnRBwR saLN2TsUfLAC6fOtbKa39jJjOjYmxXQ4zXkQPqg/yU5KLOo9ckiVQIU X-Developer-Key: i=igor.belwon@mentallysanemainliners.org; a=ed25519; pk=t9Kz6B3jEwJD7YAKcp8XftfEz7SUSlGbrsfFlbrrFwA= Add device-tree bindings for the pin controller and the EINT controller found in the MediaTek MT6878 SoC. Signed-off-by: Igor Belwon Reviewed-by: Rob Herring (Arm) --- .../bindings/pinctrl/mediatek,mt6878-pinctrl.yaml | 211 +++++++++++++++++= ++++ 1 file changed, 211 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6878-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6878-pinctr= l.yaml new file mode 100644 index 0000000000000000000000000000000000000000..8d44194a79389663de339a422de= a7b68d8a060e2 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6878-pinctrl.yaml @@ -0,0 +1,211 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6878-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6878 Pin Controller + +maintainers: + - AngeloGioacchino Del Regno + - Igor Belwon + +description: + The MediaTek MT6878 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt6878-pinctrl + + reg: + items: + - description: pin controller base + - description: bl group IO + - description: bm group IO + - description: br group IO + - description: bl1 group IO + - description: br1 group IO + - description: lm group IO + - description: lt group IO + - description: rm group IO + - description: rt group IO + - description: EINT controller E block + - description: EINT controller S block + - description: EINT controller W block + - description: EINT controller C block + + reg-names: + items: + - const: base + - const: bl + - const: bm + - const: br + - const: bl1 + - const: br1 + - const: lm + - const: lt + - const: rm + - const: rt + - const: eint-e + - const: eint-s + - const: eint-w + - const: eint-c + + gpio-controller: true + + '#gpio-cells': + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is= used, + the amount of cells must be specified as 2. See the below mentioned = gpio + binding representation for description of particular cells. + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-line-names: + maxItems: 216 + + interrupts: + description: The interrupt outputs to sysirq + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +# PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^pins': + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + description: + A pinctrl node should contain at least one subnodes representing= the + pinctrl groups available on the machine. Each subnode will list = the + pins it needs, and how they should be configured, with regard to= muxer + configuration, pullups, drive strength, input enable/disable and= input + schmitt. + + properties: + pinmux: + description: + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux are defined as macros in + arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h for this SoC. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + drive-strength-microamp: + enum: [125, 250, 500, 1000] + + bias-pull-down: + oneOf: + - type: boolean + - enum: [75000, 5000] + description: Pull down RSEL type resistance values (in ohm= s) + description: + For normal pull down type there is no need to specify a resi= stance + value, hence this can be specified as a boolean property. + For RSEL pull down type a resistance value (in ohms) can be = added. + + bias-pull-up: + oneOf: + - type: boolean + - enum: [10000, 5000, 4000, 3000] + description: Pull up RSEL type resistance values (in ohms) + description: + For normal pull up type there is no need to specify a resist= ance + value, hence this can be specified as a boolean property. + For RSEL pull up type a resistance value (in ohms) can be ad= ded. + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + #include + #define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) + #define PINMUX_GPIO99__FUNC_SCL0 (MTK_PIN_NO(99) | 1) + #define PINMUX_GPIO100__FUNC_SDA0 (MTK_PIN_NO(100) | 1) + + pio: pinctrl@10005000 { + compatible =3D "mediatek,mt6878-pinctrl"; + reg =3D <0x10005000 0x1000>, + <0x11d10000 0x1000>, + <0x11d30000 0x1000>, + <0x11d40000 0x1000>, + <0x11d50000 0x1000>, + <0x11d60000 0x1000>, + <0x11e20000 0x1000>, + <0x11e30000 0x1000>, + <0x11eb0000 0x1000>, + <0x11ec0000 0x1000>, + <0x11ce0000 0x1000>, + <0x11de0000 0x1000>, + <0x11e60000 0x1000>, + <0x1c01e000 0x1000>; + reg-names =3D "base", "bl", "bm", "br", "bl1", "br1", + "lm", "lt", "rm", "rt", "eint-e", "eint-s", + "eint-w", "eint-c"; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pio 0 0 220>; + interrupt-controller; + interrupts =3D ; + #interrupt-cells =3D <2>; + + gpio-pins { + pins { + pinmux =3D ; + bias-pull-up =3D <4000>; + drive-strength =3D <6>; + }; + }; + + i2c0-pins { + pins-bus { + pinmux =3D , + ; + bias-pull-down =3D <75000>; + drive-strength-microamp =3D <1000>; + }; + }; + }; --=20 2.51.0