From nobody Thu Oct 2 18:08:03 2025 Received: from bisque.elm.relay.mailchannels.net (bisque.elm.relay.mailchannels.net [23.83.212.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2DC061FCE; Sun, 14 Sep 2025 18:51:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=23.83.212.18 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757875920; cv=pass; b=PbVFnt0RS9hwPryB11hLuzVjwReWv0iAeheBvy2fhlqdLzIERTlBJxr1DGRCtzntRTzyi33vKF3keVzWMJzrbLYWCKgJ1F3LfEXHRPc5tkr28dJI0aKEQ2kfPd+YbWBa0EMcoLmBoEaZLOxsHdurafotSUyuDoPY8RQ3qEsYIn8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757875920; c=relaxed/simple; bh=sFkPL5D4c1hjteIm6JdYyjczgjR0F7f60gG0jHK0aV4=; h=From:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc:Date; b=Kcv1IVooyIin4lZICWgh+Azjc8rOCB7DMHRLtVhkAKTdUFo6SH2heCofNVg2//M618QJxzqKK/iCWqrfqg1CIwWQvlPUglMgpYJUJu7KWtl6kuwx4QC8l4gf/9+7eFCFoJsAPz8eF03oQY4Dpswn9iQCsN2uchmh7mSohv/NPWA= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=smankusors.com; spf=pass smtp.mailfrom=smankusors.com; arc=pass smtp.client-ip=23.83.212.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=smankusors.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=smankusors.com X-Sender-Id: hostingeremail|x-authuser|linux@smankusors.com Received: from relay.mailchannels.net (localhost [127.0.0.1]) by relay.mailchannels.net (Postfix) with ESMTP id EC79D94164F; Sun, 14 Sep 2025 18:34:51 +0000 (UTC) Received: from uk-fast-smtpout10.hostinger.io (100-107-4-38.trex-nlb.outbound.svc.cluster.local [100.107.4.38]) (Authenticated sender: hostingeremail) by relay.mailchannels.net (Postfix) with ESMTPA id E9E109410B0; Sun, 14 Sep 2025 18:34:48 +0000 (UTC) ARC-Seal: i=1; s=arc-2022; d=mailchannels.net; t=1757874891; a=rsa-sha256; cv=none; b=TWkZLemTKfu1ng3g6Ixu0QrMia8FmgNzCKDgtOD2Yif2kKmpGNNFw8yUHkB4UfATSMMqFW ACVETXsuTifz28wkTiikRTAuqWXtsJiKzjdBmPfP5g9ntiFBdJr+M6E0jxYVFIeh8Bo/hM XtA9E5Ezis2Hjq5cd2cXp0sk2H0ggT8m+kqJCWqTOw7rW7BJfx4KXdRs8MWdxqmI1pHHvn MWwMZoRTvdcyTRjFCZrGl9YBx8dhmJ7k5i0n7EQcGaadQjP8oPTnKjxkAVU+PeQMpEoA7O LHnqiXgFu85QsQ4dqOFO9MGVqm3ig1QoChjDq0WRIHlgwh48RWey8Wd1CibNAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=mailchannels.net; s=arc-2022; t=1757874891; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ffgbElzgSMrOiH9y0+JGZC9YZyDCWdKMbfQBC82F8DA=; b=4icaK5Mwl2NtD/+FBT1eqLjE/oCdfVU2TFePF5QAXBdWq/W7rLW9wv3SxDIilyrfM0Dd97 vGLbgtYPyGCAWBFeEvzDmyLgN90kdXAcNnfCwqVUY6lgUwj5lYvi0ScC2z1yijFCukheoe JS9/cCpicf8uTiuC1J+8fgd4F2W33CFbY3Xz6v0FZ7K1tEWsIthzAXrmQiuv8v4UqyuKtw cl6c2SYQmpERoYN2M45jSYFsYD+8H7jGi/deSQGri4fBCMnJRRD9D8+8iU15KANN3LTSWo rd0lwr0RuoC2s5IEiJy2kqjEOwye0yvprqKyCwqsokk/jtN/tmfY3J5nPW+Pbw== ARC-Authentication-Results: i=1; rspamd-54bcd779b6-2b7fv; auth=pass smtp.auth=hostingeremail smtp.mailfrom=linux@smankusors.com X-Sender-Id: hostingeremail|x-authuser|linux@smankusors.com X-MC-Relay: Neutral X-MC-Copy: stored-urls X-MailChannels-SenderId: hostingeremail|x-authuser|linux@smankusors.com X-MailChannels-Auth-Id: hostingeremail X-Robust-Whimsical: 5cbb84bd5ed87d49_1757874891679_629862445 X-MC-Loop-Signature: 1757874891679:1387157911 X-MC-Ingress-Time: 1757874891678 Received: from uk-fast-smtpout10.hostinger.io (uk-fast-smtpout10.hostinger.io [145.14.155.68]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384) by 100.107.4.38 (trex/7.1.3); Sun, 14 Sep 2025 18:34:51 +0000 Received: from [172.17.0.2] (unknown [110.138.220.153]) (Authenticated sender: linux@smankusors.com) by smtp.hostinger.com (smtp.hostinger.com) with ESMTPSA id 4cPxfC3zYTzFK6mc; Sun, 14 Sep 2025 18:34:43 +0000 (UTC) From: Antony Kurniawan Soemardi Subject: [PATCH 1/6] ARM: dts: qcom: msm8960: reorder nodes and properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250915-msm8960-reorder-v1-1-84cadcd7c6e3@smankusors.com> References: <20250915-msm8960-reorder-v1-0-84cadcd7c6e3@smankusors.com> In-Reply-To: <20250915-msm8960-reorder-v1-0-84cadcd7c6e3@smankusors.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , linux-gpio@vger.kernel.org, David Heidelberg , Max Shevchenko , Rudraksha Gupta , Shinjo Park , Antony Kurniawan Soemardi X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1757874878; l=18367; i=linux@smankusors.com; s=20250609; h=from:subject:message-id; bh=sFkPL5D4c1hjteIm6JdYyjczgjR0F7f60gG0jHK0aV4=; b=KN8CCRhDkO8BsLg3Fi/s/5Rel+CQZTlY12HAHCUo+b5S78ATw26fYEtjd4ujldWEMqM2BamGU eIX0nq+owIzDi+87jHy3jb2V8qI6BmAOuV2/ShTRatUX03566Zw0GNn X-Developer-Key: i=linux@smankusors.com; a=ed25519; pk=65wTy06fJl2/h/EJwjr704YG+yjHFhZObJBWzzK+N00= Date: Sun, 14 Sep 2025 18:34:43 +0000 (UTC) X-CM-Envelope: MS4xfAsJYMF3LQl3SmszHoWbiBNQSY6opIcWkHKXAzzY12o6Yvt9H72PiFjvk0xxEM+8mazt0Ik0ouumz2/PjRK+1u18Gox3CBJIgrAotjVOUxPKZ5P7X3QP 2tcSsM30XyHBmVVio0oWQY0q3PYuTQN/FfsisAzs07LLFzw54aXYUX6MRqzgRw2Ygt3j/kY0lTu4F3kpyopBVu2CZzsn79zLmzOBV7gj5ae0WM2lA5cR7mdN jEhNV13mUtKR1DB9bGdQGBHDjsaLmsR33jLoqxfA5auBwMk2Li96mwOyhikpcVGwIxLHKeq1TTOhbI4+Q8OzkIZKsylXOCiaZptE1DFhpOTiWY6LwrUSGXhL YiBy4sfR3s7HF+SPpseviotvrKKdcnSOrMNDeIFaBRs7TvLjvqGPwcLUh78TNUGoVVjLfY78dWGVeE3l0hLVoolsKpTk5AgTiWJcOy9LJJUScnYe/fate6bH +aI50mNpeRJBDS/M/Yf/4SYU+H9oDcngJ5xaUtIXYRLYrJdWYKr3rlUdgY1ap4jqkUiQ2Hs9Oo8Alz0KIb/ZUgYHb50hC2ukiJKnZxOVNtCt8vznP394zKMU pTH/nmZ+F3mmpeyUIkJhCV9oK/AS+fYvHmFYwi+KK7NRFlD4eYqPDN7mK1A7aP6syhx2ITPfdIqvEQc0IKN7m7QInpcH1lAlnDQUhq6hE2ay6g== X-CM-Analysis: v=2.4 cv=LvvAyWdc c=1 sm=1 tr=0 ts=68c70ac7 a=3tJJDl7MZm1GcYeSp/W8Jw==:117 a=3tJJDl7MZm1GcYeSp/W8Jw==:17 a=IkcTkHD0fZMA:10 a=pGLkceISAAAA:8 a=wxLWbCv9AAAA:8 a=h3hH1uk4pShZJK_U8SsA:9 a=QEXdDO2ut3YA:10 a=QJY96suAAestDpCc5Gi9:22 X-AuthUser: linux@smankusors.com Reorder the nodes in qcom-msm8960.dtsi by unit address and sort properties, as recommended in the Devicetree style guide. This is a cosmetic change only, with no functional impact. Tested-by: Rudraksha Gupta Tested-by: Shinjo Park Signed-off-by: Antony Kurniawan Soemardi Reviewed-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 524 ++++++++++++++++-----------= ---- 1 file changed, 267 insertions(+), 257 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/q= com/qcom-msm8960.dtsi index 532f16458756101b37954b5db92abec552bbc8db..9a0c87fd6d4752f7ef3d91f480c= 48efc55a08e74 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -15,6 +15,35 @@ / { compatible =3D "qcom,msm8960"; interrupt-parent =3D <&intc>; =20 + clocks { + cxo_board: cxo_board { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <19200000>; + clock-output-names =3D "cxo_board"; + }; + + pxo_board: pxo_board { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <27000000>; + clock-output-names =3D "pxo_board"; + }; + + sleep_clk: sleep_clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32768>; + clock-output-names =3D "sleep_clk"; + }; + }; + + cpu-pmu { + compatible =3D "qcom,krait-pmu"; + interrupts =3D ; + qcom,no-pc-write; + }; + cpus { #address-cells =3D <1>; #size-cells =3D <0>; @@ -22,9 +51,9 @@ cpus { =20 cpu@0 { compatible =3D "qcom,krait"; + reg =3D <0>; enable-method =3D "qcom,kpss-acc-v1"; device_type =3D "cpu"; - reg =3D <0>; next-level-cache =3D <&l2>; qcom,acc =3D <&acc0>; qcom,saw =3D <&saw0>; @@ -32,9 +61,9 @@ cpu@0 { =20 cpu@1 { compatible =3D "qcom,krait"; + reg =3D <1>; enable-method =3D "qcom,kpss-acc-v1"; device_type =3D "cpu"; - reg =3D <1>; next-level-cache =3D <&l2>; qcom,acc =3D <&acc1>; qcom,saw =3D <&saw1>; @@ -52,111 +81,27 @@ memory@80000000 { reg =3D <0x80000000 0>; }; =20 - thermal-zones { - cpu0-thermal { - polling-delay-passive =3D <250>; - polling-delay =3D <1000>; - thermal-sensors =3D <&tsens 0>; - - trips { - cpu_alert0: trip0 { - temperature =3D <60000>; - hysteresis =3D <10000>; - type =3D "passive"; - }; - - cpu_crit0: trip1 { - temperature =3D <95000>; - hysteresis =3D <10000>; - type =3D "critical"; - }; - }; - }; - - cpu1-thermal { - polling-delay-passive =3D <250>; - polling-delay =3D <1000>; - thermal-sensors =3D <&tsens 1>; - - trips { - cpu_alert1: trip0 { - temperature =3D <60000>; - hysteresis =3D <10000>; - type =3D "passive"; - }; - - cpu_crit1: trip1 { - temperature =3D <95000>; - hysteresis =3D <10000>; - type =3D "critical"; - }; - }; - }; - }; - - cpu-pmu { - compatible =3D "qcom,krait-pmu"; - interrupts =3D ; - qcom,no-pc-write; - }; - - clocks { - cxo_board: cxo_board { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <19200000>; - clock-output-names =3D "cxo_board"; - }; - - pxo_board: pxo_board { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <27000000>; - clock-output-names =3D "pxo_board"; - }; - - sleep_clk: sleep_clk { - compatible =3D "fixed-clock"; - #clock-cells =3D <0>; - clock-frequency =3D <32768>; - clock-output-names =3D "sleep_clk"; - }; - }; - - /* Temporary fixed regulator */ - vsdcc_fixed: vsdcc-regulator { - compatible =3D "regulator-fixed"; - regulator-name =3D "SDCC Power"; - regulator-min-microvolt =3D <2700000>; - regulator-max-microvolt =3D <2700000>; - regulator-always-on; - }; - soc: soc { + compatible =3D "simple-bus"; + ranges; #address-cells =3D <1>; #size-cells =3D <1>; - ranges; - compatible =3D "simple-bus"; =20 - intc: interrupt-controller@2000000 { - compatible =3D "qcom,msm-qgic2"; - interrupt-controller; - #interrupt-cells =3D <3>; - reg =3D <0x02000000 0x1000>, - <0x02002000 0x1000>; + rpm: rpm@108000 { + compatible =3D "qcom,rpm-msm8960"; + reg =3D <0x108000 0x1000>; + qcom,ipc =3D <&l2cc 0x8 2>; + + interrupts =3D , + , + ; + interrupt-names =3D "ack", "err", "wakeup"; }; =20 - timer@200a000 { - compatible =3D "qcom,kpss-wdt-msm8960", "qcom,kpss-timer", - "qcom,msm-timer"; - interrupts =3D , - , - ; - reg =3D <0x0200a000 0x100>; - clock-frequency =3D <27000000>; - clocks =3D <&sleep_clk>; - clock-names =3D "sleep"; - cpu-offset =3D <0x80000>; + ssbi: ssbi@500000 { + compatible =3D "qcom,ssbi"; + reg =3D <0x500000 0x1000>; + qcom,controller-type =3D "pmic-arbiter"; }; =20 qfprom: efuse@700000 { @@ -176,20 +121,20 @@ tsens_backup: backup-calib@414 { =20 msmgpio: pinctrl@800000 { compatible =3D "qcom,msm8960-pinctrl"; + reg =3D <0x800000 0x4000>; gpio-controller; gpio-ranges =3D <&msmgpio 0 0 152>; #gpio-cells =3D <2>; interrupts =3D ; interrupt-controller; #interrupt-cells =3D <2>; - reg =3D <0x800000 0x4000>; }; =20 gcc: clock-controller@900000 { compatible =3D "qcom,gcc-msm8960", "syscon"; + reg =3D <0x900000 0x4000>; #clock-cells =3D <1>; #reset-cells =3D <1>; - reg =3D <0x900000 0x4000>; clocks =3D <&cxo_board>, <&pxo_board>, <&lcc PLL4>; @@ -208,49 +153,25 @@ tsens: thermal-sensor { }; }; =20 - lcc: clock-controller@28000000 { - compatible =3D "qcom,lcc-msm8960"; - reg =3D <0x28000000 0x1000>; - #clock-cells =3D <1>; - #reset-cells =3D <1>; - clocks =3D <&pxo_board>, - <&gcc PLL4_VOTE>, - <0>, - <0>, <0>, - <0>, <0>, - <0>; - clock-names =3D "pxo", - "pll4_vote", - "mi2s_codec_clk", - "codec_i2s_mic_codec_clk", - "spare_i2s_mic_codec_clk", - "codec_i2s_spkr_codec_clk", - "spare_i2s_spkr_codec_clk", - "pcm_codec_clk"; + intc: interrupt-controller@2000000 { + compatible =3D "qcom,msm-qgic2"; + reg =3D <0x02000000 0x1000>, + <0x02002000 0x1000>; + interrupt-controller; + #interrupt-cells =3D <3>; }; =20 - clock-controller@4000000 { - compatible =3D "qcom,mmcc-msm8960"; - reg =3D <0x4000000 0x1000>; - #clock-cells =3D <1>; - #power-domain-cells =3D <1>; - #reset-cells =3D <1>; - clocks =3D <&pxo_board>, - <&gcc PLL3>, - <&gcc PLL8_VOTE>, - <0>, - <0>, - <0>, - <0>, - <0>; - clock-names =3D "pxo", - "pll3", - "pll8_vote", - "dsi1pll", - "dsi1pllbyte", - "dsi2pll", - "dsi2pllbyte", - "hdmipll"; + timer@200a000 { + compatible =3D "qcom,kpss-wdt-msm8960", "qcom,kpss-timer", + "qcom,msm-timer"; + reg =3D <0x0200a000 0x100>; + interrupts =3D , + , + ; + clock-frequency =3D <27000000>; + clocks =3D <&sleep_clk>; + clock-names =3D "sleep"; + cpu-offset =3D <0x80000>; }; =20 l2cc: clock-controller@2011000 { @@ -261,17 +182,6 @@ l2cc: clock-controller@2011000 { #clock-cells =3D <0>; }; =20 - rpm: rpm@108000 { - compatible =3D "qcom,rpm-msm8960"; - reg =3D <0x108000 0x1000>; - qcom,ipc =3D <&l2cc 0x8 2>; - - interrupts =3D , - , - ; - interrupt-names =3D "ack", "err", "wakeup"; - }; - acc0: clock-controller@2088000 { compatible =3D "qcom,kpss-acc-v1"; reg =3D <0x02088000 0x1000>, <0x02008000 0x1000>; @@ -281,15 +191,6 @@ acc0: clock-controller@2088000 { #clock-cells =3D <0>; }; =20 - acc1: clock-controller@2098000 { - compatible =3D "qcom,kpss-acc-v1"; - reg =3D <0x02098000 0x1000>, <0x02008000 0x1000>; - clocks =3D <&gcc PLL8_VOTE>, <&pxo_board>; - clock-names =3D "pll8_vote", "pxo"; - clock-output-names =3D "acpu1_aux"; - #clock-cells =3D <0>; - }; - saw0: power-manager@2089000 { compatible =3D "qcom,msm8960-saw2-cpu", "qcom,saw2"; reg =3D <0x02089000 0x1000>, <0x02009000 0x1000>; @@ -300,6 +201,15 @@ saw0_vreg: regulator { }; }; =20 + acc1: clock-controller@2098000 { + compatible =3D "qcom,kpss-acc-v1"; + reg =3D <0x02098000 0x1000>, <0x02008000 0x1000>; + clocks =3D <&gcc PLL8_VOTE>, <&pxo_board>; + clock-names =3D "pll8_vote", "pxo"; + clock-output-names =3D "acpu1_aux"; + #clock-cells =3D <0>; + }; + saw1: power-manager@2099000 { compatible =3D "qcom,msm8960-saw2-cpu", "qcom,saw2"; reg =3D <0x02099000 0x1000>, <0x02009000 0x1000>; @@ -310,72 +220,34 @@ saw1_vreg: regulator { }; }; =20 - gsbi5: gsbi@16400000 { - compatible =3D "qcom,gsbi-v1.0.0"; - cell-index =3D <5>; - reg =3D <0x16400000 0x100>; - clocks =3D <&gcc GSBI5_H_CLK>; - clock-names =3D "iface"; - #address-cells =3D <1>; - #size-cells =3D <1>; - ranges; - - syscon-tcsr =3D <&tcsr>; - status =3D "disabled"; - - gsbi5_serial: serial@16440000 { - compatible =3D "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg =3D <0x16440000 0x1000>, - <0x16400000 0x1000>; - interrupts =3D ; - clocks =3D <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; - clock-names =3D "core", "iface"; - status =3D "disabled"; - }; - }; - - gsbi8: gsbi@1a000000 { - compatible =3D "qcom,gsbi-v1.0.0"; - cell-index =3D <8>; - reg =3D <0x1a000000 0x100>; - clocks =3D <&gcc GSBI8_H_CLK>; - clock-names =3D "iface"; - #address-cells =3D <1>; - #size-cells =3D <1>; - ranges; - - syscon-tcsr =3D <&tcsr>; - status =3D "disabled"; - - gsbi8_serial: serial@1a040000 { - compatible =3D "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg =3D <0x1a040000 0x1000>, - <0x1a000000 0x1000>; - interrupts =3D ; - clocks =3D <&gcc GSBI8_UART_CLK>, <&gcc GSBI8_H_CLK>; - clock-names =3D "core", "iface"; - status =3D "disabled"; - }; - }; - - ssbi: ssbi@500000 { - compatible =3D "qcom,ssbi"; - reg =3D <0x500000 0x1000>; - qcom,controller-type =3D "pmic-arbiter"; - }; - - rng@1a500000 { - compatible =3D "qcom,prng"; - reg =3D <0x1a500000 0x200>; - clocks =3D <&gcc PRNG_CLK>; - clock-names =3D "core"; + clock-controller@4000000 { + compatible =3D "qcom,mmcc-msm8960"; + reg =3D <0x4000000 0x1000>; + #clock-cells =3D <1>; + #power-domain-cells =3D <1>; + #reset-cells =3D <1>; + clocks =3D <&pxo_board>, + <&gcc PLL3>, + <&gcc PLL8_VOTE>, + <0>, + <0>, + <0>, + <0>, + <0>; + clock-names =3D "pxo", + "pll3", + "pll8_vote", + "dsi1pll", + "dsi1pllbyte", + "dsi2pll", + "dsi2pllbyte", + "hdmipll"; }; =20 sdcc3: mmc@12180000 { compatible =3D "arm,pl18x", "arm,primecell"; - arm,primecell-periphid =3D <0x00051180>; - status =3D "disabled"; reg =3D <0x12180000 0x2000>; + arm,primecell-periphid =3D <0x00051180>; interrupts =3D ; clocks =3D <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; clock-names =3D "mclk", "apb_pclk"; @@ -387,6 +259,8 @@ sdcc3: mmc@12180000 { vmmc-supply =3D <&vsdcc_fixed>; dmas =3D <&sdcc3bam 2>, <&sdcc3bam 1>; dma-names =3D "tx", "rx"; + + status =3D "disabled"; }; =20 sdcc3bam: dma-controller@12182000 { @@ -400,10 +274,9 @@ sdcc3bam: dma-controller@12182000 { }; =20 sdcc1: mmc@12400000 { - status =3D "disabled"; compatible =3D "arm,pl18x", "arm,primecell"; - arm,primecell-periphid =3D <0x00051180>; reg =3D <0x12400000 0x2000>; + arm,primecell-periphid =3D <0x00051180>; interrupts =3D ; clocks =3D <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; clock-names =3D "mclk", "apb_pclk"; @@ -415,6 +288,8 @@ sdcc1: mmc@12400000 { vmmc-supply =3D <&vsdcc_fixed>; dmas =3D <&sdcc1bam 2>, <&sdcc1bam 1>; dma-names =3D "tx", "rx"; + + status =3D "disabled"; }; =20 sdcc1bam: dma-controller@12402000 { @@ -427,36 +302,6 @@ sdcc1bam: dma-controller@12402000 { qcom,ee =3D <0>; }; =20 - tcsr: syscon@1a400000 { - compatible =3D "qcom,tcsr-msm8960", "syscon"; - reg =3D <0x1a400000 0x100>; - }; - - gsbi1: gsbi@16000000 { - compatible =3D "qcom,gsbi-v1.0.0"; - cell-index =3D <1>; - reg =3D <0x16000000 0x100>; - clocks =3D <&gcc GSBI1_H_CLK>; - clock-names =3D "iface"; - #address-cells =3D <1>; - #size-cells =3D <1>; - ranges; - status =3D "disabled"; - - gsbi1_spi: spi@16080000 { - compatible =3D "qcom,spi-qup-v1.1.1"; - #address-cells =3D <1>; - #size-cells =3D <0>; - reg =3D <0x16080000 0x1000>; - interrupts =3D ; - cs-gpios =3D <&msmgpio 8 0>; - - clocks =3D <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; - clock-names =3D "core", "iface"; - status =3D "disabled"; - }; - }; - usb1: usb@12500000 { compatible =3D "qcom,ci-hdrc"; reg =3D <0x12500000 0x200>, @@ -473,6 +318,7 @@ usb1: usb@12500000 { phys =3D <&usb_hs1_phy>; phy-names =3D "usb-phy"; #reset-cells =3D <1>; + status =3D "disabled"; =20 ulpi { @@ -488,6 +334,32 @@ usb_hs1_phy: phy { }; }; =20 + gsbi1: gsbi@16000000 { + compatible =3D "qcom,gsbi-v1.0.0"; + reg =3D <0x16000000 0x100>; + ranges; + cell-index =3D <1>; + clocks =3D <&gcc GSBI1_H_CLK>; + clock-names =3D "iface"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + status =3D "disabled"; + + gsbi1_spi: spi@16080000 { + compatible =3D "qcom,spi-qup-v1.1.1"; + reg =3D <0x16080000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + interrupts =3D ; + cs-gpios =3D <&msmgpio 8 0>; + clocks =3D <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; + clock-names =3D "core", "iface"; + + status =3D "disabled"; + }; + }; + gsbi3: gsbi@16200000 { compatible =3D "qcom,gsbi-v1.0.0"; reg =3D <0x16200000 0x100>; @@ -497,6 +369,7 @@ gsbi3: gsbi@16200000 { clock-names =3D "iface"; #address-cells =3D <1>; #size-cells =3D <1>; + status =3D "disabled"; =20 gsbi3_i2c: i2c@16280000 { @@ -511,9 +384,146 @@ gsbi3_i2c: i2c@16280000 { clock-names =3D "core", "iface"; #address-cells =3D <1>; #size-cells =3D <0>; + + status =3D "disabled"; + }; + }; + + gsbi5: gsbi@16400000 { + compatible =3D "qcom,gsbi-v1.0.0"; + reg =3D <0x16400000 0x100>; + ranges; + cell-index =3D <5>; + clocks =3D <&gcc GSBI5_H_CLK>; + clock-names =3D "iface"; + #address-cells =3D <1>; + #size-cells =3D <1>; + syscon-tcsr =3D <&tcsr>; + + status =3D "disabled"; + + gsbi5_serial: serial@16440000 { + compatible =3D "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg =3D <0x16440000 0x1000>, + <0x16400000 0x1000>; + interrupts =3D ; + clocks =3D <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; + clock-names =3D "core", "iface"; + + status =3D "disabled"; + }; + }; + + gsbi8: gsbi@1a000000 { + compatible =3D "qcom,gsbi-v1.0.0"; + reg =3D <0x1a000000 0x100>; + ranges; + cell-index =3D <8>; + clocks =3D <&gcc GSBI8_H_CLK>; + clock-names =3D "iface"; + #address-cells =3D <1>; + #size-cells =3D <1>; + syscon-tcsr =3D <&tcsr>; + + status =3D "disabled"; + + gsbi8_serial: serial@1a040000 { + compatible =3D "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg =3D <0x1a040000 0x1000>, + <0x1a000000 0x1000>; + interrupts =3D ; + clocks =3D <&gcc GSBI8_UART_CLK>, <&gcc GSBI8_H_CLK>; + clock-names =3D "core", "iface"; + status =3D "disabled"; }; }; + + tcsr: syscon@1a400000 { + compatible =3D "qcom,tcsr-msm8960", "syscon"; + reg =3D <0x1a400000 0x100>; + }; + + rng@1a500000 { + compatible =3D "qcom,prng"; + reg =3D <0x1a500000 0x200>; + clocks =3D <&gcc PRNG_CLK>; + clock-names =3D "core"; + }; + + lcc: clock-controller@28000000 { + compatible =3D "qcom,lcc-msm8960"; + reg =3D <0x28000000 0x1000>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + clocks =3D <&pxo_board>, + <&gcc PLL4_VOTE>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + clock-names =3D "pxo", + "pll4_vote", + "mi2s_codec_clk", + "codec_i2s_mic_codec_clk", + "spare_i2s_mic_codec_clk", + "codec_i2s_spkr_codec_clk", + "spare_i2s_spkr_codec_clk", + "pcm_codec_clk"; + }; + }; + + thermal-zones { + cpu0-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + thermal-sensors =3D <&tsens 0>; + + trips { + cpu_alert0: trip0 { + temperature =3D <60000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + cpu_crit0: trip1 { + temperature =3D <95000>; + hysteresis =3D <10000>; + type =3D "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive =3D <250>; + polling-delay =3D <1000>; + thermal-sensors =3D <&tsens 1>; + + trips { + cpu_alert1: trip0 { + temperature =3D <60000>; + hysteresis =3D <10000>; + type =3D "passive"; + }; + + cpu_crit1: trip1 { + temperature =3D <95000>; + hysteresis =3D <10000>; + type =3D "critical"; + }; + }; + }; + }; + + /* Temporary fixed regulator */ + vsdcc_fixed: vsdcc-regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "SDCC Power"; + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <2700000>; + regulator-always-on; }; }; #include "qcom-msm8960-pins.dtsi" --=20 2.34.1