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charset="utf-8" Add nodes for: - apm-sysreg - cam-sysreg - core-sysreg - cpucl0/1-sysreg - dispaud-sysreg - fsys-sysreg - g2d/g3d-sysreg - peri-sysreg Signed-off-by: Alexandru Chimac --- arch/arm64/boot/dts/exynos/exynos9610.dtsi | 60 ++++++++++++++++++++++++++= ++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos9610.dtsi b/arch/arm64/boot/d= ts/exynos/exynos9610.dtsi index 2a15986c459d6af9f83362c27cdcc3a2646c256b..8ac113ceddacc30b52fa35954c8= 5e1b8c320057d 100644 --- a/arch/arm64/boot/dts/exynos/exynos9610.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos9610.dtsi @@ -210,6 +210,12 @@ chipid@10000000 { reg =3D <0x10000000 0x100>; }; =20 + sysreg_peri: system-controller@10010000 { + compatible =3D "samsung,exynos9610-peri-sysreg", "syscon"; + reg =3D <0x10010000 0x10000>; + clocks =3D <&cmu_peri CLK_GOUT_PERI_SYSREG_PCLK>; + }; + cmu_peri: clock-controller@10030000 { compatible =3D "samsung,exynos9610-cmu-peri"; reg =3D <0x10030000 0x8000>; @@ -238,6 +244,12 @@ cmu_cpucl1: clock-controller@0x10800000 { "dout_cmu_hpm"; }; =20 + sysreg_cpucl1: system-controller@10810000 { + compatible =3D "samsung,exynos9610-cpucl1-sysreg", "syscon"; + reg =3D <0x10810000 0x10000>; + clocks =3D <&cmu_cpucl1 CLK_GOUT_CPUCL1_SYSREG_PCLK>; + }; + cmu_cpucl0: clock-controller@0x10900000 { compatible =3D "samsung,exynos9610-cmu-cpucl0"; reg =3D <0x10900000 0x8000>; @@ -253,12 +265,24 @@ cmu_cpucl0: clock-controller@0x10900000 { "dout_cmu_hpm"; }; =20 + sysreg_cpucl0: system-controller@10910000 { + compatible =3D "samsung,exynos9610-cpucl0-sysreg", "syscon"; + reg =3D <0x10910000 0x10000>; + clocks =3D <&cmu_cpucl0 CLK_GOUT_CPUCL0_SYSREG_PCLK>; + }; + pinctrl_shub: pinctrl@11080000 { compatible =3D "samsung,exynos9610-pinctrl"; reg =3D <0x11080000 0x1000>; interrupts =3D ; }; =20 + sysreg_g3d: system-controller@11410000 { + compatible =3D "samsung,exynos9610-g3d-sysreg", "syscon"; + reg =3D <0x11410000 0x10000>; + clocks =3D <&cmu_g3d CLK_GOUT_G3D_SYSREG_PCLK>; + }; + cmu_g3d: clock-controller@11430000 { compatible =3D "samsung,exynos9610-cmu-g3d"; reg =3D <0x11430000 0x8000>; @@ -285,6 +309,12 @@ cmu_apm: clock-controller@11800000 { "dout_cmu_apm_bus"; }; =20 + sysreg_apm: system-controller@11810000 { + compatible =3D "samsung,exynos9610-apm-sysreg", "syscon"; + reg =3D <0x11810000 0x10000>; + clocks =3D <&cmu_apm CLK_GOUT_APM_SYSREG_PCLK>; + }; + pinctrl_alive: pinctrl@11850000 { compatible =3D "samsung,exynos9610-pinctrl"; reg =3D <0x11850000 0x1000>; @@ -314,6 +344,12 @@ pinctrl_cmgp: pinctrl@11c20000 { reg =3D <0x11c20000 0x1000>; }; =20 + sysreg_core: system-controller@12010000 { + compatible =3D "samsung,exynos9610-core-sysreg", "syscon"; + reg =3D <0x12010000 0x10000>; + clocks =3D <&cmu_core CLK_GOUT_CORE_SYSREG_PCLK>; + }; + cmu_core: clock-controller@120f0000 { compatible =3D "samsung,exynos9610-cmu-core"; reg =3D <0x120f0000 0x8000>; @@ -365,6 +401,12 @@ cmu_g2d: clock-controller@12e00000 { "dout_cmu_g2d_mscl"; }; =20 + sysreg_g2d: system-controller@12e10000 { + compatible =3D "samsung,exynos9610-g2d-sysreg", "syscon"; + reg =3D <0x12e10000 0x10000>; + clocks =3D <&cmu_g2d CLK_GOUT_G2D_SYSREG_PCLK>; + }; + cmu_fsys: clock-controller@13400000 { compatible =3D "samsung,exynos9610-cmu-fsys"; reg =3D <0x13400000 0x8000>; @@ -382,6 +424,12 @@ cmu_fsys: clock-controller@13400000 { "dout_cmu_fsys_ufs_embd"; }; =20 + sysreg_fsys: system-controller@13410000 { + compatible =3D "samsung,exynos9610-fsys-sysreg", "syscon"; + reg =3D <0x13410000 0x10000>; + clocks =3D <&cmu_fsys CLK_GOUT_FSYS_SYSREG_PCLK>; + }; + pinctrl_fsys: pinctrl@13490000 { compatible =3D "samsung,exynos9610-pinctrl"; reg =3D <0x13490000 0x1000>; @@ -405,6 +453,18 @@ cmu_cam: clock-controller@14500000 { "dout_cmu_cam_bus"; }; =20 + sysreg_cam: system-controller@14510000 { + compatible =3D "samsung,exynos9610-cam-sysreg", "syscon"; + reg =3D <0x14510000 0x10000>; + clocks =3D <&cmu_cam CLK_GOUT_CAM_SYSREG_PCLK>; + }; + + sysreg_dispaud: system-controller@14810000 { + compatible =3D "samsung,exynos9610-dispaud-sysreg", "syscon"; + reg =3D <0x14810000 0x10000>; + clocks =3D <&cmu_dispaud CLK_GOUT_DISPAUD_SYSREG_PCLK>; + }; + cmu_dispaud: clock-controller@14980000 { compatible =3D "samsung,exynos9610-cmu-dispaud"; reg =3D <0x14980000 0x8000>; --=20 2.47.3