From nobody Thu Oct 2 16:35:37 2025 Received: from mail-10625.protonmail.ch (mail-10625.protonmail.ch [79.135.106.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A17CD2E5B02; Sun, 14 Sep 2025 21:19:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=79.135.106.25 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757884778; cv=none; b=sakz3p5F/j8cNJeNiSfsi4c3yV9ni4k8KnY6sTptcy3j1apSabGz/LyY6T2TwPeEHcFqCRcZR/8cjw3sl1LyYX2P+OrAnYaGj/lKjFxW3N5XdHe2JzSeSLCLCW6cQrzKnUVTVwnVHuqR2KKt//WBVKfeRramzDMl67gF4SoU9UE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757884778; c=relaxed/simple; bh=Tm2tkgwVfm/rSf7qiWCn1fx12NZ369907uxKBQf5w8w=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=UBoY9dWggKvzIhK5TGfu7NYTZylD83Z3zTSNgKSV5FXogyDNU93uEaxgYs5sZLtfccTnJNr7yp6zXbtmQui55XAMilac2uhNFuFDLwVzH1Rnk6Eg6QU9BoJiWxZ+zy0NkNvIhrojxPtERy/QSSLyq6Sb2+TqFIObduoRQcOVo64= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=chimac.ro; spf=pass smtp.mailfrom=chimac.ro; dkim=pass (2048-bit key) header.d=chimac.ro header.i=@chimac.ro header.b=QPVwBSgi; arc=none smtp.client-ip=79.135.106.25 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=chimac.ro Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chimac.ro Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=chimac.ro header.i=@chimac.ro header.b="QPVwBSgi" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chimac.ro; s=protonmail; t=1757884766; x=1758143966; bh=ODo9UZb3u8FT/19zOvc129UIw6FeGXUJ4RZq5xtxicA=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=QPVwBSgiLx0eZe6+FLy7vrDu8jE3VfAzFUD4QKvATByGhBZ2/qe7nxO949Ytj4klz aVA52nUmF6iUQZdjIqlsNLrl6kA/bd5CFpAlAaI3C9R6vKVD1awWteIhHqlhgcrFwp WzTmhJT9Ozt5saJWhcEkeVeGX+EsRDt/4K2UumjAGamRbojrKiaSCf6GSj4SNK5LKa vjm04Esk1F1yXI1GYh+EQJmKCfu65f4RKorXln+nfmY11/2BIbkjjCzZ5j4WzvqNYP LUargAibrr1BYqSrwLuvOmanSkW0H8v8lQ4GErvYSqyzbd09BN+aXCJ5o3eCCX6ZLz w6vukq/mFkb1Q== Date: Sun, 14 Sep 2025 21:19:19 +0000 To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Alexandru Chimac , Krzysztof Kozlowski From: Alexandru Chimac Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Alexandru Chimac Subject: [PATCH 1/8] dt-bindings: clock: samsung: Add Exynos9610 CMU bindings Message-ID: <20250915-exynos9610-clocks-v1-1-3f615022b178@chimac.ro> In-Reply-To: <20250915-exynos9610-clocks-v1-0-3f615022b178@chimac.ro> References: <20250915-exynos9610-clocks-v1-0-3f615022b178@chimac.ro> Feedback-ID: 139133584:user:proton X-Pm-Message-ID: b15908df5025982c6643690b9c1fe0b5d1b7c07b Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This clock management unit has a topmost block (CMU_TOP) that generates top clocks for other blocks, alongside 20 other blocks, out of which 11 are currently implemented. Signed-off-by: Alexandru Chimac --- .../bindings/clock/samsung,exynos9610-clock.yaml | 344 ++++++++++ include/dt-bindings/clock/samsung,exynos9610.h | 720 +++++++++++++++++= ++++ 2 files changed, 1064 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos9610-clo= ck.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos9610-clock.= yaml new file mode 100644 index 0000000000000000000000000000000000000000..f3b7bc49a6ab18c5dd3c54d1f5f= cdb7a67d15668 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/samsung,exynos9610-clock.yaml @@ -0,0 +1,344 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos9610-clock.yaml +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos9610 SoC clock controller + +maintainers: + - Alexandru Chimac + - Chanwoo Choi + - Krzysztof Kozlowski + +description: | + Exynos9610 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate de= vice + tree nodes, and might depend on each other. Root clocks in that clock tr= ee are + three external clocks:: OSCCLK (26MHz), DLL_DCO (360MHz), OSCCLK_RCO (CM= GP, 30MHz). + The external OSCCLK must be defined as fixed-rate clock in the device tr= ee. + + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs + and dividers; all other clocks of function blocks (other CMUs) are usual= ly derived + from CMU_TOP. + + Each clock is assigned an identifier and client nodes can use this ident= ifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros + in 'include/dt-bindings/clock/samsung,exynos9610.h'. + +properties: + compatible: + enum: + - samsung,exynos9610-cmu-top + - samsung,exynos9610-cmu-apm + - samsung,exynos9610-cmu-cam + - samsung,exynos9610-cmu-cmgp + - samsung,exynos9610-cmu-core + - samsung,exynos9610-cmu-cpucl0 + - samsung,exynos9610-cmu-cpucl1 + - samsung,exynos9610-cmu-dispaud + - samsung,exynos9610-cmu-fsys + - samsung,exynos9610-cmu-g2d + - samsung,exynos9610-cmu-g3d + - samsung,exynos9610-cmu-peri + + clocks: + minItems: 1 + maxItems: 7 + + clock-names: + minItems: 1 + maxItems: 7 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos9610-cmu-top + + then: + properties: + clocks: + items: + - description: External reference clock (26MHz) + + clock-names: + items: + - const: oscclk + + - if: + properties: + compatible: + contains: + const: samsung,exynos9610-cmu-apm + + then: + properties: + clocks: + items: + - description: External reference clock (26MHz) + - description: External reference clock (360Mhz) + - description: CMU_APM bus clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dll_dco + - const: dout_cmu_apm_bus + + - if: + properties: + compatible: + contains: + const: samsung,exynos9610-cmu-cam + + then: + properties: + clocks: + items: + - description: External reference clock (26MHz) + - description: CMU_CAM bus clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_cmu_cam_bus + + - if: + properties: + compatible: + contains: + const: samsung,exynos9610-cmu-cmgp + + then: + properties: + clocks: + items: + - description: External reference clock (26MHz) + - description: External reference clock (30MHz) + - description: CMU_CMGP bus clock (from CMU_APM) + + clock-names: + items: + - const: oscclk + - const: oscclk_rco + - const: gout_cmu_cmgp_bus + + - if: + properties: + compatible: + contains: + const: samsung,exynos9610-cmu-core + + then: + properties: + clocks: + items: + - description: External reference clock (26MHz) + - description: CMU_CORE bus clock (from CMU_TOP) + - description: CMU_CORE CCI clock (from CMU_TOP) + - description: CMU_CORE G3D clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: gout_cmu_core_bus + - const: gout_cmu_core_cci + - const: gout_cmu_core_g3d + + - if: + properties: + compatible: + contains: + const: samsung,exynos9610-cmu-cpucl0 + + then: + properties: + clocks: + items: + - description: External reference clock (26MHz) + - description: CMU_CPUCL0 debug clock (from CMU_TOP) + - description: CMU_CPUCL0 switch clock (from CMU_TOP) + - description: HPM clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_cmu_cpucl0_dbg + - const: dout_cmu_cpucl0_switch + - const: dout_cmu_hpm + + - if: + properties: + compatible: + contains: + const: samsung,exynos9610-cmu-cpucl1 + + then: + properties: + clocks: + items: + - description: External reference clock (26MHz) + - description: CMU_CPUCL1 switch clock (from CMU_TOP) + - description: HPM clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_cmu_cpucl1_switch + - const: dout_cmu_hpm + + - if: + properties: + compatible: + contains: + const: samsung,exynos9610-cmu-dispaud + + then: + properties: + clocks: + items: + - description: External reference clock (26MHz) + - description: External reference clock (10Mhz) + - description: External reference clock (100Mhz) + - description: External reference clock (60Mhz) + - description: CMU_DISPAUD audio clock (from CMU_TOP) + - description: CMU_DISPAUD CPU clock (from CMU_TOP) + - description: CMU_DISPAUD display clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: ioclk_audiocdclk0 + - const: ioclk_audiocdclk1 + - const: tick_usb + - const: dout_cmu_dispaud_aud + - const: dout_cmu_dispaud_cpu + - const: dout_cmu_dispaud_disp + + - if: + properties: + compatible: + contains: + const: samsung,exynos9610-cmu-fsys + + then: + properties: + clocks: + items: + - description: External reference clock (26MHz) + - description: CMU_FSYS bus clock (from CMU_TOP) + - description: CMU_FSYS external MMC clock (from CMU_TOP) + - description: CMU_FSYS embedded MMC clock (from CMU_TOP) + - description: CMU_FSYS embedded UFS clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_cmu_fsys_bus + - const: dout_cmu_fsys_mmc_card + - const: dout_cmu_fsys_mmc_embd + - const: dout_cmu_fsys_ufs_embd + + - if: + properties: + compatible: + contains: + const: samsung,exynos9610-cmu-g2d + + then: + properties: + clocks: + items: + - description: External reference clock (26MHz) + - description: CMU_G2D G2D clock (from CMU_TOP) + - description: CMU_G2D MSCL clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_cmu_g2d_g2d + - const: dout_cmu_g2d_mscl + + - if: + properties: + compatible: + contains: + const: samsung,exynos9610-cmu-g3d + + then: + properties: + clocks: + items: + - description: External reference clock (26MHz) + - description: CMU_G3D switch clock (from CMU_TOP) + - description: HPM clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_cmu_g3d_switch + - const: dout_cmu_hpm + + - if: + properties: + compatible: + contains: + const: samsung,exynos9610-cmu-peri + + then: + properties: + clocks: + items: + - description: External reference clock (26MHz) + - description: CMU_PERI bus clock (from CMU_TOP) + - description: CMU_PERI IP clock (from CMU_TOP) + - description: CMU_PERI UART clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_cmu_peri_bus + - const: dout_cmu_peri_ip + - const: dout_cmu_peri_uart + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + - reg + +additionalProperties: false + +examples: + # Clock controller node for CMU_FSYS + - | + #include + + cmu_fsys: clock-controller@13400000 { + compatible =3D "samsung,exynos9610-cmu-fsys"; + reg =3D <0x13400000 0x8000>; + #clock-cells =3D <1> + + clocks =3D <&oscclk>, + <&cmu_top CLK_DOUT_CMU_FSYS_BUS>, + <&cmu_top CLK_DOUT_CMU_FSYS_MMC_CARD>, + <&cmu_top CLK_DOUT_CMU_FSYS_MMC_EMBD>, + <&cmu_top CLK_DOUT_CMU_FSYS_UFS_EMBD>, + + clock-names =3D "oscclk", + "dout_cmu_fsys_bus", + "dout_cmu_fsys_mmc_card", + "dout_cmu_fsys_mmc_embd", + "dout_cmu_fsys_ufs_embd"; + }; +... diff --git a/include/dt-bindings/clock/samsung,exynos9610.h b/include/dt-bi= ndings/clock/samsung,exynos9610.h new file mode 100644 index 0000000000000000000000000000000000000000..047c35fd8bf133996aaa185f9c8= e5457499e707e --- /dev/null +++ b/include/dt-bindings/clock/samsung,exynos9610.h @@ -0,0 +1,720 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Device tree binding constants for Exynos9610 clocks + * + * Copyright (c) 2025, Alexandru Chimac + */ + +/* CMU_TOP PLLs */ +#define CLK_FOUT_SHARED0_PLL 1 +#define CLK_FOUT_SHARED1_PLL 2 +#define CLK_FOUT_MMC_PLL 3 + +/* CMU_TOP muxes */ +#define CLK_MOUT_PLL_SHARED0 4 +#define CLK_MOUT_PLL_SHARED1 5 +#define CLK_MOUT_PLL_MMC 6 +#define CLK_MOUT_CMU_APM_BUS 7 +#define CLK_MOUT_CMU_CAM_BUS 8 +#define CLK_MOUT_CMU_CIS_CLK0 9 +#define CLK_MOUT_CMU_CIS_CLK1 10 +#define CLK_MOUT_CMU_CIS_CLK2 11 +#define CLK_MOUT_CMU_CIS_CLK3 12 +#define CLK_MOUT_CMU_CORE_BUS 13 +#define CLK_MOUT_CMU_CORE_CCI 14 +#define CLK_MOUT_CMU_CORE_G3D 15 +#define CLK_MOUT_CMU_CPUCL0_DBG 16 +#define CLK_MOUT_CMU_CPUCL0_SWITCH 17 +#define CLK_MOUT_CMU_CPUCL1_SWITCH 18 +#define CLK_MOUT_CMU_DISPAUD_AUD 19 +#define CLK_MOUT_CMU_DISPAUD_CPU 20 +#define CLK_MOUT_CMU_DISPAUD_DISP 21 +#define CLK_MOUT_CMU_FSYS_BUS 22 +#define CLK_MOUT_CMU_FSYS_MMC_CARD 23 +#define CLK_MOUT_CMU_FSYS_MMC_EMBD 24 +#define CLK_MOUT_CMU_FSYS_UFS_EMBD 25 +#define CLK_MOUT_CMU_G2D_G2D 26 +#define CLK_MOUT_CMU_G2D_MSCL 27 +#define CLK_MOUT_CMU_G3D_SWITCH 28 +#define CLK_MOUT_CMU_HPM 29 +#define CLK_MOUT_CMU_ISP_BUS 30 +#define CLK_MOUT_CMU_ISP_GDC 31 +#define CLK_MOUT_CMU_ISP_VRA 32 +#define CLK_MOUT_CMU_MFC_MFC 33 +#define CLK_MOUT_CMU_MFC_WFD 34 +#define CLK_MOUT_CMU_MIF_BUSP 35 +#define CLK_MOUT_CMU_MIF_SWITCH 36 +#define CLK_MOUT_CMU_PERI_BUS 37 +#define CLK_MOUT_CMU_PERI_IP 38 +#define CLK_MOUT_CMU_PERI_UART 39 +#define CLK_MOUT_CMU_USB_BUS 40 +#define CLK_MOUT_CMU_USB_DPGTC 41 +#define CLK_MOUT_CMU_USB_USB30DRD 42 +#define CLK_MOUT_CMU_VIPX1_BUS 43 +#define CLK_MOUT_CMU_VIPX2_BUS 44 +#define CLK_MOUT_CLK_CMU_CMUREF 45 +#define CLK_MOUT_CMU_CMUREF 46 + +/* CMU_TOP dividers */ +#define CLK_DOUT_CMU_SHARED0_DIV2 47 +#define CLK_DOUT_CMU_SHARED0_DIV3 48 +#define CLK_DOUT_CMU_SHARED0_DIV4 49 +#define CLK_DOUT_CMU_SHARED1_DIV2 50 +#define CLK_DOUT_CMU_SHARED1_DIV3 51 +#define CLK_DOUT_CMU_SHARED1_DIV4 52 +#define CLK_DOUT_CMU_MMC_DIV2 53 +#define CLK_DOUT_AP2CP_SHARED0_PLL_CLK 54 +#define CLK_DOUT_AP2CP_SHARED1_PLL_CLK 55 +#define CLK_DOUT_CMU_APM_BUS 56 +#define CLK_DOUT_CMU_CAM_BUS 57 +#define CLK_DOUT_CMU_CIS_CLK0 58 +#define CLK_DOUT_CMU_CIS_CLK1 59 +#define CLK_DOUT_CMU_CIS_CLK2 60 +#define CLK_DOUT_CMU_CIS_CLK3 61 +#define CLK_DOUT_CMU_CORE_BUS 62 +#define CLK_DOUT_CMU_CORE_CCI 63 +#define CLK_DOUT_CMU_CORE_G3D 64 +#define CLK_DOUT_CMU_CPUCL0_DBG 65 +#define CLK_DOUT_CMU_CPUCL0_SWITCH 66 +#define CLK_DOUT_CMU_CPUCL1_SWITCH 67 +#define CLK_DOUT_CMU_DISPAUD_AUD 68 +#define CLK_DOUT_CMU_DISPAUD_CPU 69 +#define CLK_DOUT_CMU_DISPAUD_DISP 70 +#define CLK_DOUT_CMU_FSYS_BUS 71 +#define CLK_DOUT_CMU_FSYS_MMC_CARD 72 +#define CLK_DOUT_CMU_FSYS_MMC_EMBD 73 +#define CLK_DOUT_CMU_FSYS_UFS_EMBD 74 +#define CLK_DOUT_CMU_G2D_G2D 75 +#define CLK_DOUT_CMU_G2D_MSCL 76 +#define CLK_DOUT_CMU_G3D_SWITCH 77 +#define CLK_DOUT_CMU_HPM 78 +#define CLK_DOUT_CMU_ISP_BUS 79 +#define CLK_DOUT_CMU_ISP_GDC 80 +#define CLK_DOUT_CMU_ISP_VRA 81 +#define CLK_DOUT_CMU_MFD_MFC 82 +#define CLK_DOUT_CMU_MFD_WFD 83 +#define CLK_DOUT_CMU_MIF_BUSP 84 +#define CLK_DOUT_CMU_PERI_BUS 85 +#define CLK_DOUT_CMU_PERI_IP 86 +#define CLK_DOUT_CMU_PERI_UART 87 +#define CLK_DOUT_CMU_USB_BUS 88 +#define CLK_DOUT_CMU_USB_DPGTC 89 +#define CLK_DOUT_CMU_USB_USB30DRD 90 +#define CLK_DOUT_CMU_VIPX1_BUS 91 +#define CLK_DOUT_CMU_VIPX2_BUS 92 +#define CLK_DOUT_CLK_CMU_CMUREF 93 +#define CLK_DOUT_CMU_OTP 94 + +/* CMU_TOP gates */ +#define CLK_GOUT_CMU_MIF_SWITCH 95 +#define CLK_GOUT_CLK_CMU_OTP_CLK 96 +#define CLK_GOUT_CMU_APM_BUS 97 +#define CLK_GOUT_CMU_CAM_BUS 98 +#define CLK_GOUT_CMU_CIS_CLK0 99 +#define CLK_GOUT_CMU_CIS_CLK1 100 +#define CLK_GOUT_CMU_CIS_CLK2 101 +#define CLK_GOUT_CMU_CIS_CLK3 102 +#define CLK_GOUT_CMU_CORE_BUS 103 +#define CLK_GOUT_CMU_CORE_CCI 104 +#define CLK_GOUT_CMU_CORE_G3D 105 +#define CLK_GOUT_CMU_CPUCL0_DBG 106 +#define CLK_GOUT_CMU_CPUCL0_SWITCH 107 +#define CLK_GOUT_CMU_CPUCL1_SWITCH 108 +#define CLK_GOUT_CMU_DISPAUD_AUD 109 +#define CLK_GOUT_CMU_DISPAUD_CPU 110 +#define CLK_GOUT_CMU_DISPAUD_DISP 111 +#define CLK_GOUT_CMU_FSYS_BUS 112 +#define CLK_GOUT_CMU_FSYS_MMC_CARD 113 +#define CLK_GOUT_CMU_FSYS_MMC_EMBD 114 +#define CLK_GOUT_CMU_FSYS_UFS_EMBD 115 +#define CLK_GOUT_CMU_G2D_G2D 116 +#define CLK_GOUT_CMU_G2D_MSCL 117 +#define CLK_GOUT_CMU_G3D_SWITCH 118 +#define CLK_GOUT_CMU_HPM 119 +#define CLK_GOUT_CMU_ISP_BUS 120 +#define CLK_GOUT_CMU_ISP_GDC 121 +#define CLK_GOUT_CMU_ISP_VRA 122 +#define CLK_GOUT_CMU_MFC_MFC 123 +#define CLK_GOUT_CMU_MFC_WFD 124 +#define CLK_GOUT_CMU_MIF_BUSP 125 +#define CLK_GOUT_CMU_MODEM_SHARED0 126 +#define CLK_GOUT_CMU_MODEM_SHARED1 127 +#define CLK_GOUT_CMU_PERI_BUS 128 +#define CLK_GOUT_CMU_PERI_IP 129 +#define CLK_GOUT_CMU_PERI_UART 130 +#define CLK_GOUT_CMU_USB_BUS 131 +#define CLK_GOUT_CMU_USB_DPGTC 132 +#define CLK_GOUT_CMU_USB_USB30DRD 133 +#define CLK_GOUT_CMU_VIPX1_BUS 134 +#define CLK_GOUT_CMU_VIPX2_BUS 135 + +/* CMU_APM muxes */ +#define CLK_MOUT_PLL_APM_BUS_USER 1 +#define CLK_MOUT_PLL_DLL_USER 2 +#define CLK_MOUT_CMU_SHUB_BUS 3 +#define CLK_MOUT_CLK_APM_BUS 4 + +/* CMU_APM dividers */ +#define CLK_DOUT_CMU_SHUB_BUS 5 +#define CLK_DOUT_CLK_APM_BUS 6 + +/* CPU_APM gates */ +#define CLK_GOUT_CMU_CMGP_BUS 7 +#define CLK_GOUT_CLK_APM_CMU_PCLK 8 +#define CLK_GOUT_CLK_APM_OSCCLK_CLK 9 +#define CLK_GOUT_CLK_APM_OSCCLK_RCO_CLK 10 +#define CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 11 +#define CLK_GOUT_APM_APBIF_PMU_ALIVE_PCLK 12 +#define CLK_GOUT_APM_APBIF_RTC_ALIVE_PCLK 12 +#define CLK_GOUT_APM_APBIF_TOP_RTC_ALIVE_PCLK 13 +#define CLK_GOUT_APM_GREBEINTEGRATION_HCLK 14 +#define CLK_GOUT_APM_INTMEM_ACLK 15 +#define CLK_GOUT_APM_INTMEM_PCLK 16 +#define CLK_GOUT_APM_LHM_AXI_P_GNSS_CLK 17 +#define CLK_GOUT_APM_LHM_AXI_P_CLK 18 +#define CLK_GOUT_APM_LHM_AXI_P_MODEM_CLK 19 +#define CLK_GOUT_APM_LHM_AXI_P_SHUB_CLK 20 +#define CLK_GOUT_APM_LHM_AXI_P_WLBT_CLK 21 +#define CLK_GOUT_APM_LHS_AXI_D_CLK 22 +#define CLK_GOUT_APM_LHS_AXI_LP_SHUB_CLK 23 +#define CLK_GOUT_APM_MAILBOX_AP2CP_PCLK 24 +#define CLK_GOUT_APM_MAILBOX_AP2CP_S_PCLK 25 +#define CLK_GOUT_APM_MAILBOX_AP2GNSS_PCLK 26 +#define CLK_GOUT_APM_MAILBOX_AP2SHUB_PCLK 27 +#define CLK_GOUT_APM_MAILBOX_AP2WLBT_PCLK 28 +#define CLK_GOUT_APM_MAILBOX_APM2AP_PCLK 29 +#define CLK_GOUT_APM_MAILBOX_APM2CP_PCLK 30 +#define CLK_GOUT_APM_MAILBOX_APM2GNSS_PCLK 31 +#define CLK_GOUT_APM_MAILBOX_APM2SHUB_PCLK 32 +#define CLK_GOUT_APM_MAILBOX_APM2WLBT_PCLK 33 +#define CLK_GOUT_APM_MAILBOX_CP2GNSS_PCLK 34 +#define CLK_GOUT_APM_MAILBOX_CP2SHUB_PCLK 35 +#define CLK_GOUT_APM_MAILBOX_CP2WLBT_PCLK 36 +#define CLK_GOUT_APM_MAILBOX_SHUB2GNSS_PCLK 37 +#define CLK_GOUT_APM_MAILBOX_SHUB2WLBT_PCLK 38 +#define CLK_GOUT_APM_MAILBOX_WLBT2ABOX_PCLK 39 +#define CLK_GOUT_APM_MAILBOX_WLBT2GNSS_PCLK 40 +#define CLK_GOUT_APM_PEM_CLK 41 +#define CLK_GOUT_APM_PGEN_LITE_CLK 42 +#define CLK_GOUT_APM_PMU_INTR_GEN_PCLK 43 +#define CLK_GOUT_APM_BUS_CLK 44 +#define CLK_GOUT_APM_GREBE_CLK 45 +#define CLK_GOUT_APM_SPEEDY_PCLK 46 +#define CLK_GOUT_APM_SYSREG_PCLK 47 +#define CLK_GOUT_APM_WDT_PCLK 48 +#define CLK_GOUT_APM_XIU_DP_ACLK 49 + +/* CMU_CAM muxes */ +#define CLK_MOUT_PLL_CAM_BUS_USER 1 + +/* CMU_CAM dividers */ +#define CLK_DIV_CLK_CAM_BUSP 2 + +/* CMU_CAM gates */ +#define CLK_GAT_CLK_CAM_CMU_PCLK 3 +#define CLK_GAT_CLK_CAM_OSCCLK_CLK 4 +#define CLK_GOUT_CAM_BUSD 5 +#define CLK_GOUT_CAM_BTM_ACLK 6 +#define CLK_GOUT_CAM_BTM_PCLK 7 +#define CLK_GOUT_CAM_LHS_ATB_CAMISP_CLK 8 +#define CLK_GOUT_CAM_IS6P10P0_ACLK_3AA 9 +#define CLK_GOUT_CAM_IS6P10P0_ACLK_CSIS0 10 +#define CLK_GOUT_CAM_IS6P10P0_ACLK_CSIS1 11 +#define CLK_GOUT_CAM_IS6P10P0_ACLK_CSIS2 12 +#define CLK_GOUT_CAM_IS6P10P0_ACLK_CSIS3 13 +#define CLK_GOUT_CAM_IS6P10P0_ACLK_RDMA 14 +#define CLK_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS0 15 +#define CLK_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS1 16 +#define CLK_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS2 17 +#define CLK_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS3 18 +#define CLK_GOUT_CAM_IS6P10P0_ACLK_PAFSTAT_CORE 19 +#define CLK_GOUT_CAM_IS6P10P0_ACLK_PPMU_CAM 20 +#define CLK_GOUT_CAM_IS6P10P0_ACLK_DMA 21 +#define CLK_GOUT_CAM_IS6P10P0_ACLK_SMMU_CAM 22 +#define CLK_GOUT_CAM_IS6P10P0_ACLK_XIU_D_CAM 23 +#define CLK_GOUT_CAM_IS6P10P0_PCLK_PGEN_LITE_CAM0 24 +#define CLK_GOUT_CAM_IS6P10P0_PCLK_PGEN_LITE_CAM1 25 +#define CLK_GOUT_CAM_IS6P10P0_PCLK_PPMU_CAM 26 +#define CLK_GOUT_CAM_LHM_AXI_P_CLK 27 +#define CLK_GOUT_CAM_LHS_ACEL_D_CLK 28 +#define CLK_GOUT_CAM_BUSD_CLK 29 +#define CLK_GOUT_CAM_BUSP_CLK 30 +#define CLK_GOUT_CAM_SYSREG_PCLK 31 + +/* CMU_CMGP muxes */ +#define CLK_MOUT_CLK_CMGP_ADC 0 +#define CLK_MOUT_CLK_CMGP_I2C 1 +#define CLK_MOUT_CLK_CMGP_USI00 2 +#define CLK_MOUT_CLK_CMGP_USI01 3 +#define CLK_MOUT_CLK_CMGP_USI02 4 +#define CLK_MOUT_CLK_CMGP_USI03 5 +#define CLK_MOUT_CLK_CMGP_USI04 6 + +/* CMU_CMGP dividers */ +#define CLK_DOUT_CLK_CMGP_ADC 0 +#define CLK_DOUT_CLK_CMGP_I2C 1 +#define CLK_DOUT_CLK_CMGP_USI00 2 +#define CLK_DOUT_CLK_CMGP_USI01 3 +#define CLK_DOUT_CLK_CMGP_USI02 4 +#define CLK_DOUT_CLK_CMGP_USI03 5 +#define CLK_DOUT_CLK_CMGP_USI04 6 + +/* CMU_CMGP gates */ +#define CLK_GOUT_CMGP_CMU_PCLK 7 +#define CLK_GOUT_CLK_CMGP_OSCCLK_RCO_CLK 8 +#define CLK_GOUT_CMGP_ADC_PCLK_S0 9 +#define CLK_GOUT_CMGP_ADC_PCLK_S1 10 +#define CLK_GOUT_CMGP_GPIO_PCLK 11 +#define CLK_GOUT_CMGP_I2C_CMGP00_IPCLK 12 +#define CLK_GOUT_CMGP_I2C_CMGP00_PCLK 13 +#define CLK_GOUT_CMGP_I2C_CMGP01_IPCLK 14 +#define CLK_GOUT_CMGP_I2C_CMGP01_PCLK 15 +#define CLK_GOUT_CMGP_I2C_CMGP02_IPCLK 16 +#define CLK_GOUT_CMGP_I2C_CMGP02_PCLK 17 +#define CLK_GOUT_CMGP_I2C_CMGP03_IPCLK 18 +#define CLK_GOUT_CMGP_I2C_CMGP03_PCLK 19 +#define CLK_GOUT_CMGP_I2C_CMGP04_IPCLK 20 +#define CLK_GOUT_CMGP_I2C_CMGP04_PCLK 21 +#define CLK_GOUT_CMGP_BUS_CLK 22 +#define CLK_GOUT_CMGP_I2C_CLK 23 +#define CLK_GOUT_CMGP_USI00_CLK 24 +#define CLK_GOUT_CMGP_USI01_CLK 25 +#define CLK_GOUT_CMGP_USI02_CLK 26 +#define CLK_GOUT_CMGP_USI03_CLK 27 +#define CLK_GOUT_CMGP_USI04_CLK 28 +#define CLK_GOUT_CMGP_SYSREG_CMGP2CP_PCLK 29 +#define CLK_GOUT_CMGP_SYSREG_CMGP2GNSS_PCLK 30 +#define CLK_GOUT_CMGP_SYSREG_CMGP2PMU_AP_PCLK 31 +#define CLK_GOUT_CMGP_SYSREG_CMGP2PMU_SHUB_PCLK 32 +#define CLK_GOUT_CMGP_SYSREG_CMGP2SHUB_PCLK 33 +#define CLK_GOUT_CMGP_SYSREG_CMGP2WLBT_PCLK 34 +#define CLK_GOUT_CMGP_SYSREG_PCLK 35 +#define CLK_GOUT_CMGP_USI_CMGP00_IPCLK 36 +#define CLK_GOUT_CMGP_USI_CMGP00_PCLK 37 +#define CLK_GOUT_CMGP_USI_CMGP01_IPCLK 38 +#define CLK_GOUT_CMGP_USI_CMGP01_PCLK 39 +#define CLK_GOUT_CMGP_USI_CMGP02_IPCLK 40 +#define CLK_GOUT_CMGP_USI_CMGP02_PCLK 41 +#define CLK_GOUT_CMGP_USI_CMGP03_IPCLK 42 +#define CLK_GOUT_CMGP_USI_CMGP03_PCLK 43 +#define CLK_GOUT_CMGP_USI_CMGP04_IPCLK 44 +#define CLK_GOUT_CMGP_USI_CMGP04_PCLK 45 + +/* CMU_CORE muxes */ +#define CLK_MOUT_PLL_CORE_BUS_USER 1 +#define CLK_MOUT_PLL_CORE_CCI_USER 2 +#define CLK_MOUT_PLL_CORE_G3D_USER 3 +#define CLK_MOUT_CLK_CORE_GIC 4 + +/* CMU_CORE dividers */ +#define CLK_DOUT_CLK_CORE_BUSP 5 + +/* CMU_CORE gates */ +#define CLK_GOUT_CLK_CORE_CMU_PCLK 6 +#define CLK_GOUT_CORE_AD_APB_CCI_550_PCLKM 7 +#define CLK_GOUT_CORE_AD_APB_DIT_PCLKM 8 +#define CLK_GOUT_CORE_AD_APB_PDMA0_PCLKM 9 +#define CLK_GOUT_CORE_AD_APB_PGEN_PDMA_PCLKM 10 +#define CLK_GOUT_CORE_AD_APB_PPFW_MEM0_PCLKM 11 +#define CLK_GOUT_CORE_AD_APB_PPFW_MEM1_PCLKM 12 +#define CLK_GOUT_CORE_AD_APB_PPFW_PERI_PCLKM 13 +#define CLK_GOUT_CORE_AD_APB_SPDMA_PCLKM 14 +#define CLK_GOUT_CORE_AD_AXI_GIC_ACLKM 15 +#define CLK_GOUT_CORE_ASYNCSFR_WR_DMC0_PCLK 16 +#define CLK_GOUT_CORE_ASYNCSFR_WR_DMC1_PCLK 17 +#define CLK_GOUT_CORE_AXI_US_A40_64TO128_DIT_ACLK 18 +#define CLK_GOUT_CORE_BAAW_P_GNSS_PCLK 19 +#define CLK_GOUT_CORE_BAAW_P_MODEM_PCLK 20 +#define CLK_GOUT_CORE_BAAW_P_SHUB_PCLK 21 +#define CLK_GOUT_CORE_BAAW_P_WLBT_PCLK 22 +#define CLK_GOUT_CORE_CCI_550_ACLK 23 +#define CLK_GOUT_CORE_DIT_ICLKL2A 24 +#define CLK_GOUT_CORE_GIC400_AIHWACG_CLK 25 +#define CLK_GOUT_CORE_LHM_ACEL_D0_ISP_CLK 26 +#define CLK_GOUT_CORE_LHM_ACEL_D0_MFC_CLK 27 +#define CLK_GOUT_CORE_LHM_ACEL_D1_ISP_CLK 28 +#define CLK_GOUT_CORE_LHM_ACEL_D1_MFC_CLK 29 +#define CLK_GOUT_CORE_LHM_ACEL_D_CAM_CLK 30 +#define CLK_GOUT_CORE_LHM_ACEL_D_DPU_CLK 31 +#define CLK_GOUT_CORE_LHM_ACEL_D_FSYS_CLK 32 +#define CLK_GOUT_CORE_LHM_ACEL_D_G2D_CLK 33 +#define CLK_GOUT_CORE_LHM_ACEL_D_USB_CLK 34 +#define CLK_GOUT_CORE_LHM_ACEL_D_VIPX1_CLK 35 +#define CLK_GOUT_CORE_LHM_ACEL_D_VIPX2_CLK 36 +#define CLK_GOUT_CORE_LHM_ACE_D_CPUCL0_CLK 37 +#define CLK_GOUT_CORE_LHM_ACE_D_CPUCL1_CLK 38 +#define CLK_GOUT_CORE_LHM_AXI_D0_MODEM_CLK 39 +#define CLK_GOUT_CORE_LHM_AXI_D1_MODEM_CLK 40 +#define CLK_GOUT_CORE_LHM_AXI_D_ABOX_CLK 41 +#define CLK_GOUT_CORE_LHM_AXI_D_APM_CLK 42 +#define CLK_GOUT_CORE_LHM_AXI_D_CSSYS_CLK 43 +#define CLK_GOUT_CORE_LHM_AXI_D_G3D_CLK 44 +#define CLK_GOUT_CORE_LHM_AXI_D_GNSS_CLK 45 +#define CLK_GOUT_CORE_LHM_AXI_D_SHUB_CLK 46 +#define CLK_GOUT_CORE_LHM_AXI_D_WLBT_CLK 47 +#define CLK_GOUT_CORE_LHS_AXI_D0_MIF_CPU_CLK 48 +#define CLK_GOUT_CORE_LHS_AXI_D0_MIF_CP_CLK 49 +#define CLK_GOUT_CORE_LHS_AXI_D0_MIF_NRT_CLK 50 +#define CLK_GOUT_CORE_LHS_AXI_D0_MIF_RT_CLK 51 +#define CLK_GOUT_CORE_LHS_AXI_D1_MIF_CPU_CLK 52 +#define CLK_GOUT_CORE_LHS_AXI_D1_MIF_CP_CLK 53 +#define CLK_GOUT_CORE_LHS_AXI_D1_MIF_NRT_CLK 54 +#define CLK_GOUT_CORE_LHS_AXI_D1_MIF_RT_CLK 55 +#define CLK_GOUT_CORE_LHS_AXI_P_APM_CLK 56 +#define CLK_GOUT_CORE_LHS_AXI_P_CAM_CLK 57 +#define CLK_GOUT_CORE_LHS_AXI_P_CPUCL0_CLK 58 +#define CLK_GOUT_CORE_LHS_AXI_P_CPUCL1_CLK 59 +#define CLK_GOUT_CORE_LHS_AXI_P_DISPAUD_CLK 60 +#define CLK_GOUT_CORE_LHS_AXI_P_FSYS_CLK 61 +#define CLK_GOUT_CORE_LHS_AXI_P_G2D_CLK 62 +#define CLK_GOUT_CORE_LHS_AXI_P_G3D_CLK 63 +#define CLK_GOUT_CORE_LHS_AXI_P_GNSS_CLK 64 +#define CLK_GOUT_CORE_LHS_AXI_P_ISP_CLK 65 +#define CLK_GOUT_CORE_LHS_AXI_P_MFC_CLK 66 +#define CLK_GOUT_CORE_LHS_AXI_P_MIF0_CLK 67 +#define CLK_GOUT_CORE_LHS_AXI_P_MIF1_CLK 68 +#define CLK_GOUT_CORE_LHS_AXI_P_MODEM_CLK 69 +#define CLK_GOUT_CORE_LHS_AXI_P_PERI_CLK 70 +#define CLK_GOUT_CORE_LHS_AXI_P_SHUB_CLK 71 +#define CLK_GOUT_CORE_LHS_AXI_P_USB_CLK 72 +#define CLK_GOUT_CORE_LHS_AXI_P_VIPX1_CLK 73 +#define CLK_GOUT_CORE_LHS_AXI_P_VIPX2_CLK 74 +#define CLK_GOUT_CORE_LHS_AXI_P_WLBT_CLK 75 +#define CLK_GOUT_CORE_PDMA_CORE_ACLK_PDMA0 76 +#define CLK_GOUT_CORE_PGEN_LITE_SIREX_CLK 77 +#define CLK_GOUT_CORE_PGEN_PDMA_CLK 78 +#define CLK_GOUT_CORE_PPCFW_G3D_ACLK 79 +#define CLK_GOUT_CORE_PPCFW_G3D_PCLK 80 +#define CLK_GOUT_CORE_PPFW_CORE_MEM0_CLK 81 +#define CLK_GOUT_CORE_PPFW_CORE_MEM1_CLK 82 +#define CLK_GOUT_CORE_PPFW_CORE_PERI_CLK 83 +#define CLK_GOUT_CORE_PPMU_ACE_CPUCL0_ACLK 84 +#define CLK_GOUT_CORE_PPMU_ACE_CPUCL0_PCLK 85 +#define CLK_GOUT_CORE_PPMU_ACE_CPUCL1_ACLK 86 +#define CLK_GOUT_CORE_PPMU_ACE_CPUCL1_PCLK 87 +#define CLK_GOUT_CORE_BUSD_CLK 88 +#define CLK_GOUT_CORE_BUSP_G3D_OCC_CLK 89 +#define CLK_GOUT_CORE_BUSP_CLK 90 +#define CLK_GOUT_CORE_BUSP_OCC_CLK 91 +#define CLK_GOUT_CORE_CCI_CLK 92 +#define CLK_GOUT_CORE_CCI_OCC_CLK 93 +#define CLK_GOUT_CORE_G3D_CLK 94 +#define CLK_GOUT_CORE_G3D_OCC_CLK 95 +#define CLK_GOUT_CORE_GIC_CLK 96 +#define CLK_GOUT_CORE_OSCCLK_CLK 97 +#define CLK_GOUT_CORE_SFR_APBIF_CMU_TOPC_PCLK 98 +#define CLK_GOUT_CORE_SIREX_ACLK 99 +#define CLK_GOUT_CORE_SIREX_PCLK 100 +#define CLK_GOUT_CORE_SPDMA_CORE_ACLK_PDMA1 101 +#define CLK_GOUT_CORE_SYSREG_PCLK 102 +#define CLK_GOUT_CORE_TREX_D_ACLK 103 +#define CLK_GOUT_CORE_TREX_D_CCLK 104 +#define CLK_GOUT_CORE_TREX_D_GCLK 105 +#define CLK_GOUT_CORE_TREX_D_PCLK 106 +#define CLK_GOUT_CORE_TREX_D_NRT_ACLK 107 +#define CLK_GOUT_CORE_TREX_D_NRT_PCLK 108 +#define CLK_GOUT_CORE_TREX_P_ACLK_P_CORE 109 +#define CLK_GOUT_CORE_TREX_P_CCLK_P_CORE 110 +#define CLK_GOUT_CORE_TREX_P_PCLK 111 +#define CLK_GOUT_CORE_TREX_P_PCLK_P_CORE 112 +#define CLK_GOUT_CORE_XIU_D_ACLK 113 + +/* CMU_CPUCL0 PLLs */ +#define CLK_FOUT_CPUCL0_PLL 1 + +/* CMU_CPUCL0 muxes */ +#define CLK_MOUT_PLL_CPUCL0_DBG_USER 2 +#define CLK_MOUT_PLL_CPUCL0_SWITCH_USER 3 +#define CLK_MOUT_CLK_CPUCL0_PLL 4 + +/* CMU_CPUCL0 dividers */ +#define CLK_DOUT_CLK_CLUSTER0_ACLK 5 +#define CLK_DOUT_CLK_CLUSTER0_CNTCLK 6 +#define CLK_DOUT_CLK_CLUSTER0_PCLKDBG 7 +#define CLK_DOUT_CLK_CPUCL0_CMUREF 8 +#define CLK_DOUT_CLK_CPUCL0_CPU 9 +#define CLK_DOUT_CLK_CPUCL0_PCLK 10 + +/* CMU_CPUCL0 gates */ +#define CLK_GOUT_CLK_CPUCL0_CMU_PCLK 11 +#define CLK_GOUT_CLK_CPUCL0_HPM_TARGETCLK_C 12 +#define CLK_GOUT_CLK_CPUCL0_OSCCLK_CLK 13 +#define CLK_GOUT_CLK_CLUSTER0_CPU 14 +#define CLK_GOUT_CPUCL0_ADM_APB_G_CSSYS_CORE_PCLKM 15 +#define CLK_GOUT_CPUCL0_ADS_AHB_G_CSSYS_FSYS_HCLKS 16 +#define CLK_GOUT_CPUCL0_ADS_APB_G_CSSYS_CPUCL1_PCLKS 17 +#define CLK_GOUT_CPUCL0_ADS_APB_G_P8Q_PCLKS 18 +#define CLK_GOUT_CPUCL0_AD_APB_P_DUMP_PC_CPUCL0_PCLKM 19 +#define CLK_GOUT_CPUCL0_AD_APB_P_DUMP_PC_CPUCL1_PCLKM 20 +#define CLK_GOUT_CPUCL0_BUSIF_HPMCPUCL0_PCLK 21 +#define CLK_GOUT_CPUCL0_CSSYS_DBG_PCLKDBG 22 +#define CLK_GOUT_CPUCL0_DUMP_PC_CPUCL0_PCLK 23 +#define CLK_GOUT_CPUCL0_DUMP_PC_CPUCL1_PCLK 24 +#define CLK_GOUT_CPUCL0_LHM_AXI_P_CPUCL0_CLK 25 +#define CLK_GOUT_CPUCL0_LHS_AXI_D_CSSYS_CLK 26 +#define CLK_GOUT_CPUCL0_DBG_CLK 27 +#define CLK_GOUT_CPUCL0_PCLK_CLK 28 +#define CLK_GOUT_CPUCL0_SECJTAG_CLK 29 +#define CLK_GOUT_CPUCL0_SYSREG_PCLK 30 + +/* CMU_CPUCL1 PLLs */ +#define CLK_FOUT_CPUCL1_PLL 1 + +/* CMU_CPUCL1 muxes */ +#define CLK_MOUT_PLL_CPUCL1_SWITCH_USER 2 +#define CLK_MOUT_CLK_CPUCL1_PLL 3 + +/* CMU_CPUCL1 dividers */ +#define CLK_DOUT_CLK_CLUSTER1_ACLK 4 +#define CLK_DOUT_CLK_CLUSTER1_CNTCLK 5 +#define CLK_DOUT_CLK_CPUCL1_CMUREF 6 +#define CLK_DOUT_CLK_CPUCL1_CPU 7 +#define CLK_DOUT_CLK_CPUCL1_PCLK 8 +#define CLK_DOUT_CLK_CPUCL1_PCLKDBG 9 + +/* CMU_CPUCL1 gates */ +#define CLK_GOUT_CLK_CPUCL1_CMU_PCLK 10 +#define CLK_GOUT_CLK_CPUCL1_HPM_TARGETCLK_C 11 +#define CLK_GOUT_CLK_CPUCL1_OSCCLK_CLK 12 +#define CLK_GOUT_CLK_CLUSTER1_CPU 13 +#define CLK_GOUT_CPUCL1_ADM_APB_G_CSSYS_CPUCL1_PCLKM 14 +#define CLK_GOUT_CPUCL1_BUSIF_HPMCPUCL1_PCLK 15 +#define CLK_GOUT_CPUCL1_LHM_AXI_P_CPUCL1_CLK 16 +#define CLK_GOUT_CPUCL1_LHS_ACE_D_CLK 17 +#define CLK_GOUT_CPUCL1_ACLK_CLK 18 +#define CLK_GOUT_CPUCL1_PCLKDBG_CLK 19 +#define CLK_GOUT_CPUCL1_PCLK_CLK 20 +#define CLK_GOUT_CPUCL1_SYSREG_PCLK 21 + +/* CMU_DISPAUD PLLs */ +#define CLK_FOUT_AUD_PLL 1 + +/* CMU_DISPAUD muxes */ +#define CLK_MOUT_PLL_DISPAUD_AUD_USER 2 +#define CLK_MOUT_PLL_DISPAUD_CPU_USER 3 +#define CLK_MOUT_PLL_DISPAUD_DISP_USER 4 +#define CLK_MOUT_CLK_AUD_BUS 5 +#define CLK_MOUT_CLK_AUD_CPU 6 +#define CLK_MOUT_CLK_AUD_CPU_HCH 7 +#define CLK_MOUT_CLK_AUD_FM 8 +#define CLK_MOUT_CLK_AUD_UAIF0 9 +#define CLK_MOUT_CLK_AUD_UAIF1 10 +#define CLK_MOUT_CLK_AUD_UAIF2 11 + +/* CMU_DISPAUD dividers */ +#define CLK_DOUT_CLK_AUD_AUDIF 12 +#define CLK_DOUT_CLK_AUD_BUS 13 +#define CLK_DOUT_CLK_AUD_CPU 14 +#define CLK_DOUT_CLK_AUD_CPU_ACLK 15 +#define CLK_DOUT_CLK_AUD_CPU_PCLKDBG 16 +#define CLK_DOUT_CLK_AUD_DSIF 17 +#define CLK_DOUT_CLK_AUD_FM 18 +#define CLK_DOUT_CLK_AUD_FM_SPDY 19 +#define CLK_DOUT_CLK_AUD_UAIF0 20 +#define CLK_DOUT_CLK_AUD_UAIF1 21 +#define CLK_DOUT_CLK_AUD_UAIF2 22 +#define CLK_DOUT_CLK_DISPAUD_BUSP 23 + +/* CMU_DISPAUD gates */ +#define CLK_GOUT_CLK_DISPAUD_ABOX_BCLK_UAIF0 24 +#define CLK_GOUT_CLK_DISPAUD_ABOX_BCLK_UAIF1 25 +#define CLK_GOUT_CLK_DISPAUD_ABOX_BCLK_UAIF2 26 +#define CLK_GOUT_CLK_DISPAUD_CMU_PCLK 27 +#define CLK_GOUT_CLK_DISPAUD_CLK_AUD_UAIF0_CLK 28 +#define CLK_GOUT_CLK_DISPAUD_CLK_AUD_UAIF1_CLK 29 +#define CLK_GOUT_CLK_DISPAUD_CLK_AUD_UAIF2_CLK 30 +#define CLK_GOUT_CLK_DISPAUD_OSCCLK_CLK 31 +#define CLK_GOUT_DISPAUD_ABOX_ACLK 32 +#define CLK_GOUT_DISPAUD_ABOX_BCLK_DSIF 33 +#define CLK_GOUT_DISPAUD_ABOX_BCLK_SPDY 34 +#define CLK_GOUT_DISPAUD_ABOX_CCLK_ASB 35 +#define CLK_GOUT_DISPAUD_ABOX_CCLK_CA7 36 +#define CLK_GOUT_DISPAUD_ABOX_CCLK_DBG 37 +#define CLK_GOUT_DISPAUD_ABOX_OSC_SPDY 38 +#define CLK_GOUT_DISPAUD_AXI_US_32TO128_ACLK 39 +#define CLK_GOUT_DISPAUD_CLK_DISPAUD_AUD 40 +#define CLK_GOUT_DISPAUD_CLK_DISPAUD_DISP 41 +#define CLK_GOUT_DISPAUD_BTM_ABOX_ACLK 42 +#define CLK_GOUT_DISPAUD_BTM_ABOX_PCLK 43 +#define CLK_GOUT_DISPAUD_BTM_DPU_ACLK 44 +#define CLK_GOUT_DISPAUD_BTM_DPU_PCLK 45 +#define CLK_GOUT_DISPAUD_DFTMUX_AUD_CODEC_MCLK 46 +#define CLK_GOUT_DISPAUD_DPU_ACLK_DECON 47 +#define CLK_GOUT_DISPAUD_DPU_ACLK_DMA 48 +#define CLK_GOUT_DISPAUD_DPU_ACLK_DPP 49 +#define CLK_GOUT_DISPAUD_GPIO_DISPAUD_PCLK 50 +#define CLK_GOUT_DISPAUD_LHM_AXI_P_DISPAUD_CLK 51 +#define CLK_GOUT_DISPAUD_LHS_ACEL_D_DPU_CLK 52 +#define CLK_GOUT_DISPAUD_LHS_AXI_D_ABOX_CLK 53 +#define CLK_GOUT_DISPAUD_PERI_AXI_ASB_ACLKM 54 +#define CLK_GOUT_DISPAUD_PERI_AXI_ASB_PCLK 55 +#define CLK_GOUT_DISPAUD_PPMU_ABOX_ACLK 56 +#define CLK_GOUT_DISPAUD_PPMU_ABOX_PCLK 57 +#define CLK_GOUT_DISPAUD_PPMU_DPU_ACLK 58 +#define CLK_GOUT_DISPAUD_PPMU_DPU_PCLK 59 +#define CLK_GOUT_DISPAUD_CLK_AUD_CPU_ACLK_CLK 60 +#define CLK_GOUT_DISPAUD_CLK_AUD_CPU_CLKIN_CLK 61 +#define CLK_GOUT_DISPAUD_CLK_AUD_CPU_PCLKDBG_CLK 62 +#define CLK_GOUT_DISPAUD_CLK_AUD_DSIF_CLK 63 +#define CLK_GOUT_DISPAUD_CLK_AUD_CLK 64 +#define CLK_GOUT_DISPAUD_CLK_BUSP_CLK 65 +#define CLK_GOUT_DISPAUD_CLK_DISP_CLK 66 +#define CLK_GOUT_DISPAUD_SMMU_ABOX_CLK 67 +#define CLK_GOUT_DISPAUD_SMMU_DPU_CLK 68 +#define CLK_GOUT_DISPAUD_SYSREG_PCLK 69 +#define CLK_GOUT_DISPAUD_WDT_AUD_PCLK 70 + +/* CMU_FSYS muxes */ +#define CLK_MOUT_PLL_FSYS_BUS_USER 1 +#define CLK_MOUT_PLL_FSYS_MMC_CARD_USER 2 +#define CLK_MOUT_PLL_FSYS_MMC_EMBD_USER 3 +#define CLK_MOUT_PLL_FSYS_UFS_EMBD_USER 4 + +/* CMU_FSYS gates */ +#define CLK_GOUT_FSYS_CMU_PCLK 5 +#define CLK_GOUT_FSYS_OSCCLK_CLK 6 +#define CLK_GOUT_FSYS_ADM_AHB_SSS_HCLKM 7 +#define CLK_GOUT_FSYS_BTM_ACLK 8 +#define CLK_GOUT_FSYS_BTM_PCLK 9 +#define CLK_GOUT_FSYS_GPIO_PCLK 10 +#define CLK_GOUT_FSYS_LHM_AXI_P_CLK 11 +#define CLK_GOUT_FSYS_LHS_ACEL_D_CLK 12 +#define CLK_GOUT_FSYS_MMC_CARD_ACLK 13 +#define CLK_GOUT_FSYS_MMC_CARD_SDCLKIN 14 +#define CLK_GOUT_FSYS_MMC_EMBD_ACLK 15 +#define CLK_GOUT_FSYS_MMC_EMBD_SDCLKIN 16 +#define CLK_GOUT_FSYS_PGEN_LITE_CLK 17 +#define CLK_GOUT_FSYS_PPMU_ACLK 18 +#define CLK_GOUT_FSYS_PPMU_PCLK 19 +#define CLK_GOUT_FSYS_BUS_CLK 20 +#define CLK_GOUT_FSYS_SYSREG_PCLK 21 +#define CLK_GOUT_FSYS_UFS_EMBD_ACLK 22 +#define CLK_GOUT_FSYS_UFS_EMBD_CLK_UNIPRO 23 +#define CLK_GOUT_FSYS_UFS_EMBD_FMP_CLK 24 +#define CLK_GOUT_FSYS_XIU_D_ACLK 25 + +/* CMU_G2D muxes */ +#define CLK_MOUT_PLL_G2D_G2D_USER 1 +#define CLK_MOUT_PLL_G2D_MSCL_USER 2 + +/* CMU_G2D dividers */ +#define CLK_DOUT_CLK_G2D_BUSP 3 + +/* CMU_G2D gates */ +#define CLK_GOUT_CLK_G2D_CMU_PCLK 4 +#define CLK_GOUT_CLK_G2D_OSCCLK_CLK 5 +#define CLK_GOUT_G2D_AS_AXI_JPEG_ACLKM 6 +#define CLK_GOUT_G2D_AS_AXI_JPEG_ACLKS 7 +#define CLK_GOUT_G2D_AS_AXI_MSCL_ACLKM 8 +#define CLK_GOUT_G2D_AS_AXI_MSCL_ACLKS 9 +#define CLK_GOUT_G2D_CLK_G2D_G2D 10 +#define CLK_GOUT_G2D_CLK_G2D_MSCL 11 +#define CLK_GOUT_G2D_BTM_G2D_ACLK 12 +#define CLK_GOUT_G2D_BTM_G2D_PCLK 13 +#define CLK_GOUT_G2D_G2D_ACLK 14 +#define CLK_GOUT_G2D_JPEG_FIMP_CLK 15 +#define CLK_GOUT_G2D_LHM_AXI_P_CLK 16 +#define CLK_GOUT_G2D_LHS_ACEL_D_CLK 17 +#define CLK_GOUT_G2D_MSCL_ACLK 18 +#define CLK_GOUT_G2D_PGEN100_LITE_CLK 19 +#define CLK_GOUT_G2D_PPMU_ACLK 20 +#define CLK_GOUT_G2D_PPMU_PCLK 21 +#define CLK_GOUT_G2D_BUSP_CLK 22 +#define CLK_GOUT_G2D_SYSMMU_CLK 23 +#define CLK_GOUT_G2D_SYSREG_PCLK 24 +#define CLK_GOUT_G2D_XIU_D_MSCL_ACLK 25 + +/* CMU_G3D PLLs */ +#define CLK_FOUT_G3D_PLL 1 + +/* CMU_G3D muxes */ +#define CLK_MOUT_G3D_SWITCH_USER 2 +#define CLK_MOUT_CLK_G3D_BUSD 3 + +/* CMU_G3D dividers */ +#define CLK_DOUT_CLK_G3D_BUSD 4 +#define CLK_DOUT_CLK_G3D_BUSP 5 + +/* CMU_G3D gates */ +#define CLK_GOUT_CLK_G3D_CMU_PCLK 6 +#define CLK_GOUT_CLK_G3D_G3D_CLK 7 +#define CLK_GOUT_CLK_G3D_HPM_TARGETCLK_C 8 +#define CLK_GOUT_CLK_G3D_OSCCLK_CLK 9 +#define CLK_GOUT_G3D_BTM_G3D_ACLK 10 +#define CLK_GOUT_G3D_BTM_G3D_PCLK 11 +#define CLK_GOUT_G3D_BUSIF_HPMG3D_PCLK 12 +#define CLK_GOUT_G3D_GRAY2BIN_G3D_CLK 13 +#define CLK_GOUT_G3D_LHM_AXI_G3DSFR_CLK 14 +#define CLK_GOUT_G3D_LHM_AXI_P_G3D_CLK 15 +#define CLK_GOUT_G3D_LHS_AXI_D_G3D_CLK 16 +#define CLK_GOUT_G3D_LHS_AXI_G3DSFR_CLK 17 +#define CLK_GOUT_G3D_PGEN_LITE_G3D_CLK 18 +#define CLK_GOUT_G3D_BUSD_CLK 19 +#define CLK_GOUT_G3D_BUSP_CLK 20 +#define CLK_GOUT_G3D_SYSREG_PCLK 21 + +/* CMU_PERI muxes */ +#define CLK_MOUT_PLL_PERI_BUS_USER 1 +#define CLK_MOUT_PLL_PERI_IP_USER 2 +#define CLK_MOUT_PLL_PERI_UART_USER 3 + +/* CMU_PERI dividers */ +#define CLK_DOUT_CLK_PERI_I2C 4 +#define CLK_DOUT_CLK_PERI_SPI0 5 +#define CLK_DOUT_CLK_PERI_SPI1 6 +#define CLK_DOUT_CLK_PERI_SPI2 7 +#define CLK_DOUT_CLK_PERI_USI_I2C 8 +#define CLK_DOUT_CLK_PERI_USI_USI 9 + +/* CMU_PERI gates */ +#define CLK_GOUT_CLK_PERI_I2C 10 +#define CLK_GOUT_CLK_PERI_SPI0 11 +#define CLK_GOUT_CLK_PERI_SPI1 12 +#define CLK_GOUT_CLK_PERI_SPI2 13 +#define CLK_GOUT_CLK_PERI_USI_I2C 14 +#define CLK_GOUT_CLK_PERI_USI_USI 15 +#define CLK_GOUT_PERI_AXI2AHB_MSD32_ACLK 16 +#define CLK_GOUT_PERI_BUSIF_TMU_PCLK 17 +#define CLK_GOUT_PERI_CAMI2C_0_IPCLK 18 +#define CLK_GOUT_PERI_CAMI2C_0_PCLK 19 +#define CLK_GOUT_PERI_CAMI2C_1_IPCLK 20 +#define CLK_GOUT_PERI_CAMI2C_1_PCLK 21 +#define CLK_GOUT_PERI_CAMI2C_2_IPCLK 22 +#define CLK_GOUT_PERI_CAMI2C_2_PCLK 23 +#define CLK_GOUT_PERI_CAMI2C_3_IPCLK 24 +#define CLK_GOUT_PERI_CAMI2C_3_PCLK 25 +#define CLK_GOUT_PERI_I2C_0_PCLK 26 +#define CLK_GOUT_PERI_I2C_1_PCLK 27 +#define CLK_GOUT_PERI_I2C_2_PCLK 28 +#define CLK_GOUT_PERI_I2C_3_PCLK 29 +#define CLK_GOUT_PERI_I2C_4_PCLK 30 +#define CLK_GOUT_PERI_I2C_5_PCLK 31 +#define CLK_GOUT_PERI_I2C_6_PCLK 32 +#define CLK_GOUT_PERI_GPIO_PCLK 33 +#define CLK_GOUT_PERI_LHM_AXI_P_PERI_CLK 34 +#define CLK_GOUT_PERI_MCT_PCLK 35 +#define CLK_GOUT_PERI_OTP_CON_TOP_PCLK 36 +#define CLK_GOUT_PERI_PWM_MOTOR_PCLK_S0 37 +#define CLK_GOUT_PERI_BUS_CLK 38 +#define CLK_GOUT_PERI_I2C_CLK 39 +#define CLK_GOUT_PERI_SPI_0_CLK 40 +#define CLK_GOUT_PERI_SPI_1_CLK 41 +#define CLK_GOUT_PERI_SPI_2_CLK 42 +#define CLK_GOUT_PERI_UART_CLK 43 +#define CLK_GOUT_PERI_USI00_I2C_CLK 44 +#define CLK_GOUT_PERI_USI00_USI_CLK 45 +#define CLK_GOUT_PERI_SPI_0_PCLK 46 +#define CLK_GOUT_PERI_SPI_0_IPCLK 47 +#define CLK_GOUT_PERI_SPI_1_PCLK 48 +#define CLK_GOUT_PERI_SPI_1_IPCLK 49 +#define CLK_GOUT_PERI_SPI_2_PCLK 50 +#define CLK_GOUT_PERI_SPI_2_IPCLK 51 +#define CLK_GOUT_PERI_SYSREG_PCLK 52 +#define CLK_GOUT_PERI_UART_IPCLK 53 +#define CLK_GOUT_PERI_UART_PCLK 54 +#define CLK_GOUT_PERI_USI00_I2C_IPCLK 55 +#define CLK_GOUT_PERI_USI00_I2C_PCLK 56 +#define CLK_GOUT_PERI_USI00_USI_IPCLK 57 +#define CLK_GOUT_PERI_USI00_USI_PCLK 58 +#define CLK_GOUT_PERI_WDT_CLUSTER0_PCLK 59 +#define CLK_GOUT_PERI_WDT_CLUSTER1_PCLK 60 --=20 2.47.3 From nobody Thu Oct 2 16:35:37 2025 Received: from mail-24422.protonmail.ch (mail-24422.protonmail.ch [109.224.244.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 477722E62CB; Sun, 14 Sep 2025 21:19:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.224.244.22 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757884781; cv=none; b=hG7PTMYojGomLHmQMQAQ7vc/qLBlLNz2FRzxOl7sS/U3pdoCSu6Z7zU7Dp4ZgIKJOpEPgbR02Dycfj1/5Qa+uInwxUAofgkTpiQz7UKHEg0pTWcwPa4zRM3XJnrnGNjlMK/ZU82o1PTQFQ29luz+TmW5AioBl4fxqSr0PDO9zc4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757884781; c=relaxed/simple; bh=8+/ClMG+St9z3suvo/tgfd92vbMs5WQGeMQbpIM/M6o=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jjdIQzncvipOgdigr4U/kkPyCdZUocDa+sgOHt6dcf2eGf3wC8ZZNiRBUW88quINhClMlFhPfTi+/WqXDRx8pIAjXOoJcskbqFsK7thD1KitrdP9dm5xFaJUYTssVQTxpgy1ZfGgoz90hdBcKAFNwIFoUxlWki/2gHoF3kSg/Mk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=chimac.ro; spf=pass smtp.mailfrom=chimac.ro; dkim=pass (2048-bit key) header.d=chimac.ro header.i=@chimac.ro header.b=UBGsRiN2; arc=none smtp.client-ip=109.224.244.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=chimac.ro Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chimac.ro Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=chimac.ro header.i=@chimac.ro header.b="UBGsRiN2" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chimac.ro; s=protonmail; t=1757884777; x=1758143977; bh=PZnRAM4NTUz6a26lNJhwUr/8t1nxItg9+fBTr6Z/4EU=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=UBGsRiN2nzuLcOyns1Y86gZJXqGKtNegR3F0Hach2xDu+G70kN9Fhr5yVKuJ+XBev nK9lX7kwJ0wsgotJ5G4mNcWtw97njHO8sARr1fPAqv5mw8gQeRW3fKfg3W688no0WB iNKal8o/SJ0sSxjXLEgJD/fwSttSXKnqPDHdAlmaPubt6IB4cKDsxloj0qvmc+g8qY 5K/jHL6UVikosb38KiukKZCioxhwihDJoYHXiiZloedznpR8vk3t74059p1UKUn5ye K/iqvwGnO9yGFqNxdzTVQcBmyn3T0KCrIASfJD8hTJPN2LJwWsp0+h4y31/XWxqHVN tN1wsm2E1TMQg== Date: Sun, 14 Sep 2025 21:19:32 +0000 To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Alexandru Chimac , Krzysztof Kozlowski From: Alexandru Chimac Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Alexandru Chimac Subject: [PATCH 2/8] clk: samsung: clk-pll: Add support for pll_1061x Message-ID: <20250915-exynos9610-clocks-v1-2-3f615022b178@chimac.ro> In-Reply-To: <20250915-exynos9610-clocks-v1-0-3f615022b178@chimac.ro> References: <20250915-exynos9610-clocks-v1-0-3f615022b178@chimac.ro> Feedback-ID: 139133584:user:proton X-Pm-Message-ID: a7b2c46f0923d45efb9cf8f71e4a6d359616d4be Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" These PLLs are found in the Exynos9610 and Exynos9810 SoCs, and are similar to pll_1460x, so the code for that can handle this PLL with a few small adaptations. Signed-off-by: Alexandru Chimac --- drivers/clk/samsung/clk-pll.c | 29 ++++++++++++++++++++++------- drivers/clk/samsung/clk-pll.h | 1 + 2 files changed, 23 insertions(+), 7 deletions(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 7bea7be1d7e45c32f0b303ffa55ce9cde4a4f71d..5fa553eab8e4b53a8854848737f= 619ef6a9c645a 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -785,15 +785,20 @@ static unsigned long samsung_pll46xx_recalc_rate(stru= ct clk_hw *hw, u64 fvco =3D parent_rate; =20 pll_con0 =3D readl_relaxed(pll->con_reg); - pll_con1 =3D readl_relaxed(pll->con_reg + 4); - mdiv =3D (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type =3D=3D pll_1460x)= ? + if (pll->type =3D=3D pll_1061x) + pll_con1 =3D readl_relaxed(pll->con_reg + 12); + else + pll_con1 =3D readl_relaxed(pll->con_reg + 4); + mdiv =3D (pll_con0 >> PLL46XX_MDIV_SHIFT) & (((pll->type =3D=3D pll_1460x) + || (pll->type =3D=3D pll_1061x)) ? PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK); pdiv =3D (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK; sdiv =3D (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK; kdiv =3D pll->type =3D=3D pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK : pll_con1 & PLL46XX_KDIV_MASK; =20 - shift =3D ((pll->type =3D=3D pll_4600) || (pll->type =3D=3D pll_1460x)) ?= 16 : 10; + shift =3D ((pll->type =3D=3D pll_4600) || (pll->type =3D=3D pll_1460x) + || (pll->type =3D=3D pll_1061x)) ? 16 : 10; =20 fvco *=3D (mdiv << shift) + kdiv; do_div(fvco, (pdiv << sdiv)); @@ -831,7 +836,10 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw,= unsigned long drate, } =20 con0 =3D readl_relaxed(pll->con_reg); - con1 =3D readl_relaxed(pll->con_reg + 0x4); + if (pll->type =3D=3D pll_1061x) + con1 =3D readl_relaxed(pll->con_reg + 0xc); + else + con1 =3D readl_relaxed(pll->con_reg + 0x4); =20 if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) { /* If only s change, change just s value only*/ @@ -849,7 +857,7 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, = unsigned long drate, lock =3D 0xffff; =20 /* Set PLL PMS and VSEL values. */ - if (pll->type =3D=3D pll_1460x) { + if ((pll->type =3D=3D pll_1460x) || (pll->type =3D=3D pll_1061x)) { con0 &=3D ~((PLL1460X_MDIV_MASK << PLL46XX_MDIV_SHIFT) | (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) | (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT)); @@ -866,7 +874,10 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw,= unsigned long drate, (rate->sdiv << PLL46XX_SDIV_SHIFT); =20 /* Set PLL K, MFR and MRR values. */ - con1 =3D readl_relaxed(pll->con_reg + 0x4); + if (pll->type =3D=3D pll_1061x) + con1 =3D readl_relaxed(pll->con_reg + 0xc); + else + con1 =3D readl_relaxed(pll->con_reg + 0x4); con1 &=3D ~((PLL46XX_KDIV_MASK << PLL46XX_KDIV_SHIFT) | (PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT) | (PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT)); @@ -877,7 +888,10 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw,= unsigned long drate, /* Write configuration to PLL */ writel_relaxed(lock, pll->lock_reg); writel_relaxed(con0, pll->con_reg); - writel_relaxed(con1, pll->con_reg + 0x4); + if (pll->type =3D=3D pll_1061x) + writel_relaxed(con1, pll->con_reg + 0xc); + else + writel_relaxed(con1, pll->con_reg + 0x4); =20 /* Wait for PLL lock */ return samsung_pll_lock_wait(pll, PLL46XX_LOCKED); @@ -1563,6 +1577,7 @@ static void __init _samsung_clk_register_pll(struct s= amsung_clk_provider *ctx, case pll_4650: case pll_4650c: case pll_1460x: + case pll_1061x: if (!pll->rate_table) init.ops =3D &samsung_pll46xx_clk_min_ops; else diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index 6c8bb7f26da5436dfccae89a95d1b0025f7f3e0b..7f36d1d03dcf5888027ce9b6f75= ccc9a7a135be2 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -45,6 +45,7 @@ enum samsung_pll_type { pll_531x, pll_1051x, pll_1052x, + pll_1061x, pll_0717x, pll_0718x, pll_0732x, --=20 2.47.3 From nobody Thu Oct 2 16:35:37 2025 Received: from mail-24422.protonmail.ch (mail-24422.protonmail.ch [109.224.244.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBB1A2E6CD6; Sun, 14 Sep 2025 21:19:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.224.244.22 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757884801; cv=none; b=c01fojgv8E+far/XvIi0t5ykwGf72Q7AMxxc7gP3mr9EabRgcjmWyJPITcKK+XEpQNLEurFfV/ORFq4JemKUKpeXt6rrykxoK48NkBqyBwoR9clKxb3SNOHzyYZ/wgpZblJaI4t1Cc5rjm+vuMHXVJ94i4wn+KNtP9revCH05oc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757884801; c=relaxed/simple; bh=kCp1jexKQekPbdZCBSC1Iiv0b4wjfXOzqDr8I/plKQw=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=GLS332SxkmuCYETUxULbYD39DsZhU/LDwiGVkaNR4hnblr/E81kqSkTJ0c3tkvvBtesGBuzldVQnDsIX8+sZ9L/y8w7hUoMPQlNGzOx+Qz3REwAfWHcgZcePEYNECrU1Vbo9boHGrbXyST3HpOXUEl2Pez3LsoHmC/eogU/GXXs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=chimac.ro; spf=pass smtp.mailfrom=chimac.ro; dkim=pass (2048-bit key) header.d=chimac.ro header.i=@chimac.ro header.b=NJQ/nM4w; arc=none smtp.client-ip=109.224.244.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=chimac.ro Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chimac.ro Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=chimac.ro header.i=@chimac.ro header.b="NJQ/nM4w" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chimac.ro; s=protonmail; t=1757884790; x=1758143990; bh=//QYeo4QFAh6KpfWxWsMkuoRuLgv9YqHLbs8vwoikmc=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=NJQ/nM4wf1tspAdQ3T+LoOMD92GZ6FZ5IRw7IIc8pptD54VVfXDsMmdc9Sxot6W1B 4udHZ4+Nf1joZV0tYRLuLAJFKpPP1Kn5rJC7M1EKQUeYkV3RE+Dz+w98h+JvevdSCx Vc5VZalaDKm+rMNQqxH8PCfoBsZonqAt/h8v2C8i0s/L0sQstoNgOx3mojtEBdqv0J h/RWvIid7ssXG38O/hq9eKeixXYWMZ/mJHp6dnlhCjZ0/pUuZ2sOv/tOH/0kUVJKZU mK3NMvDRNwOQVf+HJnUDwmVQRPTVTCPDu8tL9pHbpsrBpmac8ZE2zflRBKyVx9V8Ci PGOXtCv9AILmg== Date: Sun, 14 Sep 2025 21:19:44 +0000 To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Alexandru Chimac , Krzysztof Kozlowski From: Alexandru Chimac Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Alexandru Chimac Subject: [PATCH 3/8] clk: samsung: Introduce Exynos9610 clock controller driver Message-ID: <20250915-exynos9610-clocks-v1-3-3f615022b178@chimac.ro> In-Reply-To: <20250915-exynos9610-clocks-v1-0-3f615022b178@chimac.ro> References: <20250915-exynos9610-clocks-v1-0-3f615022b178@chimac.ro> Feedback-ID: 139133584:user:proton X-Pm-Message-ID: cb4470e6a6601082a7601f3084bd2c2564521a13 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The current implementation contains support for: - CMU_TOP - which generates clocks for other blocks - CMU_APM - which generates clocks for APM and CMU_CMGP - CMU_CAM - CMU_CMGP - CMU_CORE - CMU_CPUCL0/1 - CMU_DISPAUD - which generates clocks for display and ABOX - CMU_FSYS - which generates clocks for MMC/UFS - CMU_G2D, G3D - CMU_PERI - which generates clocks for peripherals Signed-off-by: Alexandru Chimac --- drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos9610.c | 3652 ++++++++++++++++++++++++++++++= ++++ 2 files changed, 3653 insertions(+) diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index ef464f434740f96623f9df62f94e2903e14e2226..2605bdecb5fff6b5a8f73cad50e= 8c1a618cfba63 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) +=3D clk-exynos7870= .o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) +=3D clk-exynos7885.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) +=3D clk-exynos850.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) +=3D clk-exynos8895.o +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) +=3D clk-exynos9610.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) +=3D clk-exynos990.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) +=3D clk-exynosautov9.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) +=3D clk-exynosautov920.o diff --git a/drivers/clk/samsung/clk-exynos9610.c b/drivers/clk/samsung/clk= -exynos9610.c new file mode 100644 index 0000000000000000000000000000000000000000..637daae1e4969dba15518f73da7= 4648981351dcb --- /dev/null +++ b/drivers/clk/samsung/clk-exynos9610.c @@ -0,0 +1,3652 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common clock framework for Exynos9610 + * + * Copyright (c) 2025, Alexandru Chimac + */ + +#include +#include +#include +#include + +#include + +#include "clk.h" +#include "clk-exynos-arm64.h" +#include "clk-pll.h" + +#define CLKS_NR_TOP (CLK_GOUT_CMU_VIPX2_BUS + 1) +#define CLKS_NR_APM (CLK_GOUT_APM_XIU_DP_ACLK + 1) +#define CLKS_NR_CAM (CLK_GOUT_CAM_SYSREG_PCLK + 1) +#define CLKS_NR_CMGP (CLK_GOUT_CMGP_USI_CMGP04_PCLK + 1) +#define CLKS_NR_CORE (CLK_GOUT_CORE_XIU_D_ACLK + 1) +#define CLKS_NR_CPUCL0 (CLK_GOUT_CPUCL0_SYSREG_PCLK + 1) +#define CLKS_NR_CPUCL1 (CLK_GOUT_CPUCL1_SYSREG_PCLK + 1) +#define CLKS_NR_DISPAUD (CLK_GOUT_DISPAUD_WDT_AUD_PCLK + 1) +#define CLKS_NR_FSYS (CLK_GOUT_FSYS_XIU_D_ACLK + 1) +#define CLKS_NR_G2D (CLK_GOUT_G2D_XIU_D_MSCL_ACLK + 1) +#define CLKS_NR_G3D (CLK_GOUT_G3D_SYSREG_PCLK + 1) +#define CLKS_NR_PERI (CLK_GOUT_PERI_WDT_CLUSTER1_PCLK + 1) + +/* TOP (0x12100000) */ +#define PLL_LOCKTIME_PLL_MMC 0x0000 +#define PLL_LOCKTIME_PLL_SHARED0 0x0004 +#define PLL_LOCKTIME_PLL_SHARED1 0x0008 +#define PLL_CON0_PLL_MMC 0x0100 +#define PLL_CON3_PLL_MMC 0x010c +#define PLL_CON0_PLL_SHARED0 0x0120 +#define PLL_CON0_PLL_SHARED1 0x0140 +#define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1000 +#define CLK_CON_MUX_MUX_CLKCMU_CAM_BUS 0x1004 +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0 0x1008 +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1 0x100c +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2 0x1010 +#define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3 0x1014 +#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1018 +#define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x101c +#define CLK_CON_MUX_MUX_CLKCMU_CORE_G3D 0x1020 +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x1024 +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x1028 +#define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x102c +#define CLK_CON_MUX_MUX_CLKCMU_DISPAUD_AUD 0x1030 +#define CLK_CON_MUX_MUX_CLKCMU_DISPAUD_CPU 0x1034 +#define CLK_CON_MUX_MUX_CLKCMU_DISPAUD_DISP 0x1038 +#define CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS 0x103c +#define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD 0x1040 +#define CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD 0x1044 +#define CLK_CON_MUX_MUX_CLKCMU_FSYS_UFS_EMBD 0x1048 +#define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x104c +#define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1050 +#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1054 +#define CLK_CON_MUX_MUX_CLKCMU_HPM 0x1058 +#define CLK_CON_MUX_MUX_CLKCMU_ISP_BUS 0x105c +#define CLK_CON_MUX_MUX_CLKCMU_ISP_GDC 0x1060 +#define CLK_CON_MUX_MUX_CLKCMU_ISP_VRA 0x1064 +#define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x1068 +#define CLK_CON_MUX_MUX_CLKCMU_MFC_WFD 0x106c +#define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x1070 +#define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x1074 +#define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1078 +#define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x107c +#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1080 +#define CLK_CON_MUX_MUX_CLKCMU_USB_BUS 0x1084 +#define CLK_CON_MUX_MUX_CLKCMU_USB_DPGTC 0x1088 +#define CLK_CON_MUX_MUX_CLKCMU_USB_USB30DRD 0x108c +#define CLK_CON_MUX_MUX_CLKCMU_VIPX1_BUS 0x1090 +#define CLK_CON_MUX_MUX_CLKCMU_VIPX2_BUS 0x1094 +#define CLK_CON_MUX_MUX_CLK_CMU_CMUREF 0x1098 +#define CLK_CON_MUX_MUX_CMU_CMUREF 0x109c +#define CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK 0x1800 +#define CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK 0x1804 +#define CLK_CON_DIV_CLKCMU_APM_BUS 0x1808 +#define CLK_CON_DIV_CLKCMU_CAM_BUS 0x180c +#define CLK_CON_DIV_CLKCMU_CIS_CLK0 0x1810 +#define CLK_CON_DIV_CLKCMU_CIS_CLK1 0x1814 +#define CLK_CON_DIV_CLKCMU_CIS_CLK2 0x1818 +#define CLK_CON_DIV_CLKCMU_CIS_CLK3 0x181c +#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820 +#define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824 +#define CLK_CON_DIV_CLKCMU_CORE_G3D 0x1828 +#define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x182c +#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1830 +#define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x1834 +#define CLK_CON_DIV_CLKCMU_DISPAUD_AUD 0x1838 +#define CLK_CON_DIV_CLKCMU_DISPAUD_CPU 0x183c +#define CLK_CON_DIV_CLKCMU_DISPAUD_DISP 0x1840 +#define CLK_CON_DIV_CLKCMU_FSYS_BUS 0x1844 +#define CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD 0x1848 +#define CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD 0x184c +#define CLK_CON_DIV_CLKCMU_FSYS_UFS_EMBD 0x1850 +#define CLK_CON_DIV_CLKCMU_G2D_G2D 0x1854 +#define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x1858 +#define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x185c +#define CLK_CON_DIV_CLKCMU_HPM 0x1860 +#define CLK_CON_DIV_CLKCMU_ISP_BUS 0x1864 +#define CLK_CON_DIV_CLKCMU_ISP_GDC 0x1868 +#define CLK_CON_DIV_CLKCMU_ISP_VRA 0x186c +#define CLK_CON_DIV_CLKCMU_MFC_MFC 0x1870 +#define CLK_CON_DIV_CLKCMU_MFC_WFD 0x1874 +#define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x1878 +#define CLK_CON_DIV_CLKCMU_OTP 0x187c +#define CLK_CON_DIV_CLKCMU_PERI_BUS 0x1880 +#define CLK_CON_DIV_CLKCMU_PERI_IP 0x1884 +#define CLK_CON_DIV_CLKCMU_PERI_UART 0x1888 +#define CLK_CON_DIV_CLKCMU_USB_BUS 0x188c +#define CLK_CON_DIV_CLKCMU_USB_DPGTC 0x1890 +#define CLK_CON_DIV_CLKCMU_USB_USB30DRD 0x1894 +#define CLK_CON_DIV_CLKCMU_VIPX1_BUS 0x1898 +#define CLK_CON_DIV_CLKCMU_VIPX2_BUS 0x189c +#define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x18a0 +#define CLK_CON_DIV_PLL_MMC_DIV2 0x18a4 +#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x18a8 +#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18ac +#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x18b0 +#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x18b4 +#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x18b8 +#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18bc +#define CLK_CON_GAT_CLKCMU_MIF_SWITCH 0x2000 +#define CLK_CON_GAT_CLK_CMU_OTP_CLK 0x2004 +#define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2008 +#define CLK_CON_GAT_GATE_CLKCMU_CAM_BUS 0x200c +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0 0x2010 +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1 0x2014 +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2 0x2018 +#define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3 0x201c +#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x2020 +#define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2024 +#define CLK_CON_GAT_GATE_CLKCMU_CORE_G3D 0x2028 +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG 0x202c +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2030 +#define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2034 +#define CLK_CON_GAT_GATE_CLKCMU_DISPAUD_AUD 0x2038 +#define CLK_CON_GAT_GATE_CLKCMU_DISPAUD_CPU 0x203c +#define CLK_CON_GAT_GATE_CLKCMU_DISPAUD_DISP 0x2040 +#define CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS 0x2044 +#define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD 0x2048 +#define CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD 0x204c +#define CLK_CON_GAT_GATE_CLKCMU_FSYS_UFS_EMBD 0x2050 +#define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x2054 +#define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x2058 +#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x205c +#define CLK_CON_GAT_GATE_CLKCMU_HPM 0x2060 +#define CLK_CON_GAT_GATE_CLKCMU_ISP_BUS 0x2064 +#define CLK_CON_GAT_GATE_CLKCMU_ISP_GDC 0x2068 +#define CLK_CON_GAT_GATE_CLKCMU_ISP_VRA 0x206c +#define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC 0x2070 +#define CLK_CON_GAT_GATE_CLKCMU_MFC_WFD 0x2074 +#define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x2078 +#define CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0 0x207c +#define CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1 0x2080 +#define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2084 +#define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2088 +#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x208c +#define CLK_CON_GAT_GATE_CLKCMU_USB_BUS 0x2090 +#define CLK_CON_GAT_GATE_CLKCMU_USB_DPGTC 0x2094 +#define CLK_CON_GAT_GATE_CLKCMU_USB_USB30DRD 0x2098 +#define CLK_CON_GAT_GATE_CLKCMU_VIPX1_BUS 0x209c +#define CLK_CON_GAT_GATE_CLKCMU_VIPX2_BUS 0x20a0 + +static const unsigned long top_clk_regs[] __initconst =3D { + PLL_LOCKTIME_PLL_MMC, + PLL_LOCKTIME_PLL_SHARED0, + PLL_LOCKTIME_PLL_SHARED1, + PLL_CON0_PLL_MMC, + PLL_CON3_PLL_MMC, + PLL_CON0_PLL_SHARED0, + PLL_CON0_PLL_SHARED1, + CLK_CON_MUX_MUX_CLKCMU_APM_BUS, + CLK_CON_MUX_MUX_CLKCMU_CAM_BUS, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, + CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, + CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, + CLK_CON_MUX_MUX_CLKCMU_CORE_G3D, + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG, + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, + CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, + CLK_CON_MUX_MUX_CLKCMU_DISPAUD_AUD, + CLK_CON_MUX_MUX_CLKCMU_DISPAUD_CPU, + CLK_CON_MUX_MUX_CLKCMU_DISPAUD_DISP, + CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS, + CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD, + CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD, + CLK_CON_MUX_MUX_CLKCMU_FSYS_UFS_EMBD, + CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, + CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, + CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, + CLK_CON_MUX_MUX_CLKCMU_HPM, + CLK_CON_MUX_MUX_CLKCMU_ISP_BUS, + CLK_CON_MUX_MUX_CLKCMU_ISP_GDC, + CLK_CON_MUX_MUX_CLKCMU_ISP_VRA, + CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, + CLK_CON_MUX_MUX_CLKCMU_MFC_WFD, + CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, + CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, + CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, + CLK_CON_MUX_MUX_CLKCMU_PERI_IP, + CLK_CON_MUX_MUX_CLKCMU_PERI_UART, + CLK_CON_MUX_MUX_CLKCMU_USB_BUS, + CLK_CON_MUX_MUX_CLKCMU_USB_DPGTC, + CLK_CON_MUX_MUX_CLKCMU_USB_USB30DRD, + CLK_CON_MUX_MUX_CLKCMU_VIPX1_BUS, + CLK_CON_MUX_MUX_CLKCMU_VIPX2_BUS, + CLK_CON_MUX_MUX_CLK_CMU_CMUREF, + CLK_CON_MUX_MUX_CMU_CMUREF, + CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK, + CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK, + CLK_CON_DIV_CLKCMU_APM_BUS, + CLK_CON_DIV_CLKCMU_CAM_BUS, + CLK_CON_DIV_CLKCMU_CORE_BUS, + CLK_CON_DIV_CLKCMU_CORE_CCI, + CLK_CON_DIV_CLKCMU_CORE_G3D, + CLK_CON_DIV_CLKCMU_CPUCL0_DBG, + CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, + CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, + CLK_CON_DIV_CLKCMU_DISPAUD_AUD, + CLK_CON_DIV_CLKCMU_DISPAUD_CPU, + CLK_CON_DIV_CLKCMU_DISPAUD_DISP, + CLK_CON_DIV_CLKCMU_FSYS_BUS, + CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD, + CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD, + CLK_CON_DIV_CLKCMU_FSYS_UFS_EMBD, + CLK_CON_DIV_CLKCMU_G2D_G2D, + CLK_CON_DIV_CLKCMU_G2D_MSCL, + CLK_CON_DIV_CLKCMU_G3D_SWITCH, + CLK_CON_DIV_CLKCMU_HPM, + CLK_CON_DIV_CLKCMU_ISP_BUS, + CLK_CON_DIV_CLKCMU_ISP_GDC, + CLK_CON_DIV_CLKCMU_ISP_VRA, + CLK_CON_DIV_CLKCMU_MFC_MFC, + CLK_CON_DIV_CLKCMU_MFC_WFD, + CLK_CON_DIV_CLKCMU_MIF_BUSP, + CLK_CON_DIV_CLKCMU_OTP, + CLK_CON_DIV_CLKCMU_PERI_BUS, + CLK_CON_DIV_CLKCMU_PERI_IP, + CLK_CON_DIV_CLKCMU_PERI_UART, + CLK_CON_DIV_CLKCMU_USB_BUS, + CLK_CON_DIV_CLKCMU_USB_DPGTC, + CLK_CON_DIV_CLKCMU_USB_USB30DRD, + CLK_CON_DIV_CLKCMU_VIPX1_BUS, + CLK_CON_DIV_CLKCMU_VIPX2_BUS, + CLK_CON_DIV_DIV_CLK_CMU_CMUREF, + CLK_CON_DIV_PLL_SHARED0_DIV2, + CLK_CON_DIV_PLL_SHARED0_DIV3, + CLK_CON_DIV_PLL_SHARED0_DIV4, + CLK_CON_DIV_PLL_SHARED1_DIV2, + CLK_CON_DIV_PLL_SHARED1_DIV3, + CLK_CON_DIV_PLL_SHARED1_DIV4, + CLK_CON_GAT_CLKCMU_MIF_SWITCH, + CLK_CON_GAT_CLK_CMU_OTP_CLK, + CLK_CON_GAT_GATE_CLKCMU_APM_BUS, + CLK_CON_GAT_GATE_CLKCMU_CAM_BUS, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, + CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, + CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, + CLK_CON_GAT_GATE_CLKCMU_CORE_G3D, + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG, + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, + CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, + CLK_CON_GAT_GATE_CLKCMU_DISPAUD_AUD, + CLK_CON_GAT_GATE_CLKCMU_DISPAUD_CPU, + CLK_CON_GAT_GATE_CLKCMU_DISPAUD_DISP, + CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS, + CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD, + CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD, + CLK_CON_GAT_GATE_CLKCMU_FSYS_UFS_EMBD, + CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, + CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, + CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, + CLK_CON_GAT_GATE_CLKCMU_HPM, + CLK_CON_GAT_GATE_CLKCMU_ISP_BUS, + CLK_CON_GAT_GATE_CLKCMU_ISP_GDC, + CLK_CON_GAT_GATE_CLKCMU_ISP_VRA, + CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, + CLK_CON_GAT_GATE_CLKCMU_MFC_WFD, + CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, + CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0, + CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1, + CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, + CLK_CON_GAT_GATE_CLKCMU_PERI_IP, + CLK_CON_GAT_GATE_CLKCMU_PERI_UART, + CLK_CON_GAT_GATE_CLKCMU_USB_BUS, + CLK_CON_GAT_GATE_CLKCMU_USB_DPGTC, + CLK_CON_GAT_GATE_CLKCMU_USB_USB30DRD, + CLK_CON_GAT_GATE_CLKCMU_VIPX1_BUS, + CLK_CON_GAT_GATE_CLKCMU_VIPX2_BUS, +}; + +static const struct samsung_pll_rate_table pll_shared0_rate_table[] __init= const =3D { + PLL_35XX_RATE(26 * MHZ, 1599000000U, 246, 4, 0), +}; + +static const struct samsung_pll_rate_table pll_shared1_rate_table[] __init= const =3D { + PLL_35XX_RATE(26 * MHZ, 1332500000U, 205, 4, 0), +}; + +static const struct samsung_pll_rate_table pll_mmc_rate_table[] __initcons= t =3D { + PLL_36XX_RATE(26 * MHZ, 799999877, 31, 1, 0, -15124), +}; + +static const struct samsung_pll_clock top_pll_clks[] __initconst =3D { + PLL(pll_1051x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", + PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0, pll_shared0_rate_tabl= e), + PLL(pll_1051x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk", + PLL_LOCKTIME_PLL_SHARED1, PLL_CON0_PLL_SHARED1, pll_shared1_rate_tabl= e), + PLL(pll_1061x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk", + PLL_LOCKTIME_PLL_MMC, PLL_CON0_PLL_MMC, pll_mmc_rate_table), +}; + +/* Parent clock list for TOP muxes */ +PNAME(mout_pll_shared0_p) =3D { "oscclk", "fout_shared0_pll" }; +PNAME(mout_pll_shared1_p) =3D { "oscclk", "fout_shared1_pll" }; +PNAME(mout_pll_mmc_p) =3D { "oscclk", "fout_mmc_pll" }; +PNAME(mout_cmu_apm_bus_p) =3D { "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4" }; +PNAME(mout_cmu_cam_bus_p) =3D { "dout_cmu_shared1_div2", + "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4" }; +PNAME(mout_cmu_cis_clk0_p) =3D { "oscclk", + "dout_cmu_shared0_div4" }; +PNAME(mout_cmu_cis_clk1_p) =3D { "oscclk", + "dout_cmu_shared0_div4" }; +PNAME(mout_cmu_cis_clk2_p) =3D { "oscclk", + "dout_cmu_shared0_div4" }; +PNAME(mout_cmu_cis_clk3_p) =3D { "oscclk", + "dout_cmu_shared0_div4" }; +PNAME(mout_cmu_core_bus_p) =3D { "dout_cmu_shared1_div2", + "dout_cmu_shared0_div3", + "dout_cmu_shared0_div4", + "dout_cmu_mmc_div2" }; +PNAME(mout_cmu_core_cci_p) =3D { "dout_cmu_shared0_div2", + "dout_cmu_shared1_div2", + "dout_cmu_shared0_div3", + "dout_cmu_mmc_div2" }; +PNAME(mout_cmu_core_g3d_p) =3D { "dout_cmu_shared0_div2", + "dout_cmu_shared1_div2", + "dout_cmu_shared0_div3", + "dout_cmu_mmc_div2" }; +PNAME(mout_cmu_cpucl0_dbg_p) =3D { "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4" }; +PNAME(mout_cmu_cpucl0_switch_p) =3D { "dout_cmu_shared0_div2", + "dout_cmu_shared1_div2", + "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3" }; +PNAME(mout_cmu_cpucl1_switch_p) =3D { "dout_cmu_shared0_div2", + "dout_cmu_shared1_div2", + "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3" }; +PNAME(mout_cmu_dispaud_aud_p) =3D { "dout_cmu_shared1_div2", + "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4" }; +PNAME(mout_cmu_dispaud_cpu_p) =3D { "fout_shared1_pll", + "dout_cmu_shared0_div2", + "dout_cmu_shared1_div2", + "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3", + "fout_mmc_pll", + "oscclk", "oscclk" }; +PNAME(mout_cmu_dispaud_disp_p) =3D { "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", + "dout_cmu_shared0_div4" }; +PNAME(mout_cmu_fsys_bus_p) =3D { "dout_cmu_shared0_div2", + "dout_cmu_shared1_div2" }; +PNAME(mout_cmu_fsys_mmc_card_p) =3D { "oscclk", + "dout_cmu_shared0_div2", + "dout_cmu_shared1_div2", + "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3", + "fout_mmc_pll", + "oscclk", "oscclk" }; +PNAME(mout_cmu_fsys_mmc_embd_p) =3D { "oscclk", + "dout_cmu_shared0_div2", + "dout_cmu_shared1_div2", + "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3", + "fout_mmc_pll", + "oscclk", "oscclk" }; +PNAME(mout_cmu_fsys_ufs_embd_p) =3D { "oscclk", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "oscclk" }; +PNAME(mout_cmu_g2d_g2d_p) =3D { "dout_cmu_shared1_div2", + "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4" }; +PNAME(mout_cmu_g2d_mscl_p) =3D { "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4" }; +PNAME(mout_cmu_g3d_switch_p) =3D { "dout_cmu_shared0_div2", + "dout_cmu_shared1_div2", + "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3" }; +PNAME(mout_cmu_hpm_p) =3D { "oscclk", + "dout_cmu_shared0_div2", + "dout_cmu_shared1_div2", + "dout_cmu_shared0_div3", + "dout_cmu_mmc_div2", + "oscclk", "oscclk", "oscclk" }; +PNAME(mout_cmu_isp_bus_p) =3D { "dout_cmu_shared1_div2", + "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4" }; +PNAME(mout_cmu_isp_gdc_p) =3D { "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4" }; +PNAME(mout_cmu_isp_vra_p) =3D { "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4" }; +PNAME(mout_cmu_mfc_mfc_p) =3D { "dout_cmu_shared1_div2", + "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4" }; +PNAME(mout_cmu_mfc_wfd_p) =3D { "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4" }; +PNAME(mout_cmu_mif_busp_p) =3D { "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_mmc_div2", + "oscclk" }; +PNAME(mout_cmu_mif_switch_p) =3D { "fout_shared0_pll", + "fout_shared1_pll", + "dout_cmu_shared0_div2", + "fout_mmc_pll", + "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4" }; +PNAME(mout_cmu_peri_bus_p) =3D { "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4" }; +PNAME(mout_cmu_peri_ip_p) =3D { "oscclk", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "oscclk" }; +PNAME(mout_cmu_peri_uart_p) =3D { "oscclk", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "oscclk" }; +PNAME(mout_cmu_usb_bus_p) =3D { "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4" }; +PNAME(mout_cmu_usb_dpgtc_p) =3D { "oscclk", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "oscclk" }; +PNAME(mout_cmu_usb_usb30drd_p) =3D { "oscclk", + "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "oscclk" }; +PNAME(mout_cmu_vipx1_bus_p) =3D { "dout_cmu_shared1_div2", + "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4" }; +PNAME(mout_cmu_vipx2_bus_p) =3D { "dout_cmu_shared1_div2", + "dout_cmu_shared0_div3", + "dout_cmu_shared1_div3", + "dout_cmu_shared0_div4" }; +PNAME(mout_clk_cmu_cmuref_p) =3D { "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4" }; +PNAME(mout_cmu_cmuref_p) =3D { "oscclk", + "dout_clk_cmu_cmuref" }; + +/* + * Register name to clock name mangling strategy used in this file + * + * Replace PLL_CON{0,3}_PLL with CLK_MOUT_PLL and mout_pll + * Replace CLK_CON_MUX_MUX_CLKCMU with CLK_MOUT_CMU and mout_cmu + * Replace CLK_CON_DIV_CLKCMU with CLK_DOUT_CMU_CMU and dout_cmu_cmu + * Replace CLK_CON_DIV_DIV_CLKCMU with CLK_DOUT_CMU_CMU and dout_cmu_cmu + * Replace CLK_CON_DIV_PLL_CLKCMU with CLK_DOUT_CMU_CMU and dout_cmu_cmu + * Replace CLK_CON_GAT_CLKCMU with CLK_GOUT_CMU and gout_cmu + * Replace CLK_CON_GAT_GATE_CLKCMU with CLK_GOUT_CMU and gout_cmu + * + * For gates remove _UID _BLK _IPCLKPORT, _I and _RSTNSYNC + */ + +static const struct samsung_mux_clock top_mux_clks[] __initconst =3D { + MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p, + PLL_CON0_PLL_SHARED0, 4, 1), + MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p, + PLL_CON0_PLL_SHARED1, 4, 1), + MUX(CLK_MOUT_PLL_MMC, "mout_pll_mmc", mout_pll_mmc_p, + PLL_CON0_PLL_MMC, 4, 1), + + MUX(CLK_MOUT_CMU_APM_BUS, "mout_cmu_apm_bus", mout_cmu_apm_bus_p, + CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1), + MUX(CLK_MOUT_CMU_CAM_BUS, "mout_cmu_cam_bus", mout_cmu_cam_bus_p, + CLK_CON_MUX_MUX_CLKCMU_CAM_BUS, 0, 2), + MUX(CLK_MOUT_CMU_CIS_CLK0, "mout_cmu_cis_clk0", mout_cmu_cis_clk0_p, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0, 1), + MUX(CLK_MOUT_CMU_CIS_CLK1, "mout_cmu_cis_clk1", mout_cmu_cis_clk1_p, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0, 1), + MUX(CLK_MOUT_CMU_CIS_CLK2, "mout_cmu_cis_clk2", mout_cmu_cis_clk2_p, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0, 1), + MUX(CLK_MOUT_CMU_CIS_CLK3, "mout_cmu_cis_clk3", mout_cmu_cis_clk2_p, + CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0, 1), + MUX(CLK_MOUT_CMU_CORE_BUS, "mout_cmu_core_bus", mout_cmu_core_bus_p, + CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2), + MUX(CLK_MOUT_CMU_CORE_CCI, "mout_cmu_core_cci", mout_cmu_core_cci_p, + CLK_CON_MUX_MUX_CLKCMU_CORE_CCI, 0, 2), + MUX(CLK_MOUT_CMU_CORE_G3D, "mout_cmu_core_g3d", mout_cmu_core_g3d_p, + CLK_CON_MUX_MUX_CLKCMU_CORE_G3D, 0, 2), + MUX(CLK_MOUT_CMU_CPUCL0_DBG, "mout_cmu_cpucl0_dbg", mout_cmu_cpucl0_dbg_p, + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG, 0, 1), + MUX(CLK_MOUT_CMU_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch", mout_cmu_cpucl0= _switch_p, + CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0, 1), + MUX(CLK_MOUT_CMU_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch", mout_cmu_cpucl1= _switch_p, + CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 0, 2), + MUX(CLK_MOUT_CMU_DISPAUD_AUD, "mout_cmu_dispaud_aud", mout_cmu_dispaud_au= d_p, + CLK_CON_MUX_MUX_CLKCMU_DISPAUD_AUD, 0, 2), + MUX(CLK_MOUT_CMU_DISPAUD_CPU, "mout_cmu_dispaud_cpu", mout_cmu_dispaud_cp= u_p, + CLK_CON_MUX_MUX_CLKCMU_DISPAUD_CPU, 0, 3), + MUX(CLK_MOUT_CMU_DISPAUD_DISP, "mout_cmu_dispaud_disp", mout_cmu_dispaud_= disp_p, + CLK_CON_MUX_MUX_CLKCMU_DISPAUD_DISP, 0, 2), + MUX(CLK_MOUT_CMU_FSYS_BUS, "mout_cmu_fsys_bus", mout_cmu_fsys_bus_p, + CLK_CON_MUX_MUX_CLKCMU_FSYS_BUS, 0, 1), + MUX(CLK_MOUT_CMU_FSYS_MMC_CARD, "mout_cmu_fsys_mmc_card", mout_cmu_fsys_m= mc_card_p, + CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_CARD, 0, 3), + MUX(CLK_MOUT_CMU_FSYS_MMC_EMBD, "mout_cmu_fsys_mmc_embd", mout_cmu_fsys_m= mc_embd_p, + CLK_CON_MUX_MUX_CLKCMU_FSYS_MMC_EMBD, 0, 3), + MUX(CLK_MOUT_CMU_FSYS_UFS_EMBD, "mout_cmu_fsys_ufs_embd", mout_cmu_fsys_u= fs_embd_p, + CLK_CON_MUX_MUX_CLKCMU_FSYS_UFS_EMBD, 0, 2), + MUX(CLK_MOUT_CMU_G2D_G2D, "mout_cmu_g2d_g2d", mout_cmu_g2d_g2d_p, + CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 2), + MUX(CLK_MOUT_CMU_G2D_MSCL, "mout_cmu_g2d_mscl", mout_cmu_g2d_mscl_p, + CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 2), + MUX(CLK_MOUT_CMU_G3D_SWITCH, "mout_cmu_g3d_SWITCH", mout_cmu_g3d_switch_p, + CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2), + MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm", mout_cmu_hpm_p, + CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 3), + MUX(CLK_MOUT_CMU_ISP_BUS, "mout_cmu_isp_bus", mout_cmu_isp_bus_p, + CLK_CON_MUX_MUX_CLKCMU_ISP_BUS, 0, 2), + MUX(CLK_MOUT_CMU_ISP_GDC, "mout_cmu_isp_gdc", mout_cmu_isp_gdc_p, + CLK_CON_MUX_MUX_CLKCMU_ISP_GDC, 0, 2), + MUX(CLK_MOUT_CMU_ISP_VRA, "mout_cmu_isp_vra", mout_cmu_isp_vra_p, + CLK_CON_MUX_MUX_CLKCMU_ISP_VRA, 0, 2), + MUX(CLK_MOUT_CMU_MFC_MFC, "mout_cmu_mfc_mfc", mout_cmu_mfc_mfc_p, + CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 2), + MUX(CLK_MOUT_CMU_MFC_WFD, "mout_cmu_mfc_wfd", mout_cmu_mfc_wfd_p, + CLK_CON_MUX_MUX_CLKCMU_MFC_WFD, 0, 2), + MUX(CLK_MOUT_CMU_MIF_BUSP, "mout_cmu_mif_busp", mout_cmu_mif_busp_p, + CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2), + MUX(CLK_MOUT_CMU_MIF_SWITCH, "mout_cmu_mif_switch", mout_cmu_mif_switch_p, + CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3), + MUX(CLK_MOUT_CMU_PERI_BUS, "mout_cmu_peri_bus", mout_cmu_peri_bus_p, + CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1), + MUX(CLK_MOUT_CMU_PERI_IP, "mout_cmu_peri_ip", mout_cmu_peri_ip_p, + CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2), + MUX(CLK_MOUT_CMU_PERI_UART, "mout_cmu_peri_uart", mout_cmu_peri_uart_p, + CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2), + MUX(CLK_MOUT_CMU_USB_BUS, "mout_cmu_usb_bus", mout_cmu_usb_bus_p, + CLK_CON_MUX_MUX_CLKCMU_USB_BUS, 0, 2), + MUX(CLK_MOUT_CMU_USB_DPGTC, "mout_cmu_usb_dpgtc", mout_cmu_usb_dpgtc_p, + CLK_CON_MUX_MUX_CLKCMU_USB_DPGTC, 0, 2), + MUX(CLK_MOUT_CMU_USB_USB30DRD, "mout_cmu_usb_usb30drd", mout_cmu_usb_usb3= 0drd_p, + CLK_CON_MUX_MUX_CLKCMU_USB_USB30DRD, 0, 2), + MUX(CLK_MOUT_CMU_VIPX1_BUS, "mout_cmu_vipx1_bus", mout_cmu_vipx1_bus_p, + CLK_CON_MUX_MUX_CLKCMU_VIPX1_BUS, 0, 2), + MUX(CLK_MOUT_CMU_VIPX2_BUS, "mout_cmu_vipx2_bus", mout_cmu_vipx2_bus_p, + CLK_CON_MUX_MUX_CLKCMU_VIPX2_BUS, 0, 2), + MUX(CLK_MOUT_CLK_CMU_CMUREF, "mout_clk_cmu_cmuref", mout_clk_cmu_cmuref_p, + CLK_CON_MUX_MUX_CLK_CMU_CMUREF, 0, 1), + MUX(CLK_MOUT_CMU_CMUREF, "mout_cmu_cmuref", mout_cmu_cmuref_p, + CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1), +}; + +static const struct samsung_div_clock top_div_clks[] __initconst =3D { + /* shared0 */ + DIV(CLK_DOUT_CMU_SHARED0_DIV2, "dout_cmu_shared0_div2", "mout_pll_shared0= ", + CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), + DIV(CLK_DOUT_CMU_SHARED0_DIV3, "dout_cmu_shared0_div3", "mout_pll_shared0= ", + CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), + DIV(CLK_DOUT_CMU_SHARED0_DIV4, "dout_cmu_shared0_div4", "dout_cmu_shared0= _div2", + CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), + + /* shared1 */ + DIV(CLK_DOUT_CMU_SHARED1_DIV2, "dout_cmu_shared1_div2", "mout_pll_shared1= ", + CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), + DIV(CLK_DOUT_CMU_SHARED1_DIV3, "dout_cmu_shared1_div3", "mout_pll_shared1= ", + CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), + DIV(CLK_DOUT_CMU_SHARED1_DIV4, "dout_cmu_shared1_div4", "dout_cmu_shared1= _div2", + CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), + + /* mmc */ + DIV(CLK_DOUT_CMU_MMC_DIV2, "dout_cmu_mmc_div2", "mout_pll_mmc", + CLK_CON_DIV_PLL_MMC_DIV2, 0, 1), + + DIV(CLK_DOUT_AP2CP_SHARED0_PLL_CLK, "dout_ap2cp_shared0_pll_clk", + "gout_cmu_modem_shared0", CLK_CON_DIV_AP2CP_SHARED0_PLL_CLK, + 0, 4), + DIV(CLK_DOUT_AP2CP_SHARED1_PLL_CLK, "dout_ap2cp_shared1_pll_clk", + "gout_cmu_modem_shared1", CLK_CON_DIV_AP2CP_SHARED1_PLL_CLK, + 0, 4), + DIV(CLK_DOUT_CMU_APM_BUS, "dout_cmu_apm_bus", "gout_cmu_apm_bus", + CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3), + DIV(CLK_DOUT_CMU_CAM_BUS, "dout_cmu_cam_bus", "gout_cmu_cam_bus", + CLK_CON_DIV_CLKCMU_CAM_BUS, 0, 4), + DIV(CLK_DOUT_CMU_CIS_CLK0, "dout_cmu_cis_clk0", "gout_cmu_cis_clk0", + CLK_CON_DIV_CLKCMU_CIS_CLK0, 0, 5), + DIV(CLK_DOUT_CMU_CIS_CLK1, "dout_cmu_cis_clk1", "gout_cmu_cis_clk1", + CLK_CON_DIV_CLKCMU_CIS_CLK1, 0, 5), + DIV(CLK_DOUT_CMU_CIS_CLK2, "dout_cmu_cis_clk2", "gout_cmu_cis_clk2", + CLK_CON_DIV_CLKCMU_CIS_CLK2, 0, 5), + DIV(CLK_DOUT_CMU_CIS_CLK3, "dout_cmu_cis_clk3", "gout_cmu_cis_clk3", + CLK_CON_DIV_CLKCMU_CIS_CLK3, 0, 5), + DIV(CLK_DOUT_CMU_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus", + CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4), + DIV(CLK_DOUT_CMU_CORE_CCI, "dout_cmu_core_cci", "gout_cmu_core_cci", + CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4), + DIV(CLK_DOUT_CMU_CORE_G3D, "dout_cmu_core_g3d", "gout_cmu_core_g3d", + CLK_CON_DIV_CLKCMU_CORE_G3D, 0, 4), + DIV(CLK_DOUT_CMU_CPUCL0_DBG, "dout_cmu_cpucl0_dbg", "gout_cmu_cpucl0_dbg", + CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 3), + DIV(CLK_DOUT_CMU_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch", "gout_cmu_cpucl= 1_switch", + CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3), + DIV(CLK_DOUT_CMU_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch", "gout_cmu_cpucl= 1_switch", + CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3), + DIV(CLK_DOUT_CMU_DISPAUD_AUD, "dout_cmu_dispaud_aud", "gout_cmu_dispaud_a= ud", + CLK_CON_DIV_CLKCMU_DISPAUD_AUD, 0, 4), + DIV(CLK_DOUT_CMU_DISPAUD_CPU, "dout_cmu_dispaud_cpu", "gout_cmu_dispaud_c= pu", + CLK_CON_DIV_CLKCMU_DISPAUD_CPU, 0, 4), + DIV(CLK_DOUT_CMU_DISPAUD_DISP, "dout_cmu_dispaud_disp", "gout_cmu_dispaud= _disp", + CLK_CON_DIV_CLKCMU_DISPAUD_DISP, 0, 4), + DIV(CLK_DOUT_CMU_FSYS_BUS, "dout_cmu_fsys_bus", "gout_cmu_fsys_bus", + CLK_CON_DIV_CLKCMU_FSYS_BUS, 0, 4), + DIV(CLK_DOUT_CMU_FSYS_MMC_CARD, "dout_cmu_fsys_mmc_card", "gout_cmu_fsys_= mmc_card", + CLK_CON_DIV_CLKCMU_FSYS_MMC_CARD, 0, 9), + DIV(CLK_DOUT_CMU_FSYS_MMC_EMBD, "dout_cmu_fsys_mmc_embd", "gout_cmu_fsys_= mmc_embd", + CLK_CON_DIV_CLKCMU_FSYS_MMC_EMBD, 0, 9), + DIV(CLK_DOUT_CMU_G2D_G2D, "dout_cmu_g2d_g2d", "gout_cmu_g2d_g2d", + CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4), + DIV(CLK_DOUT_CMU_G2D_MSCL, "dout_cmu_g2d_mscl", "gout_cmu_g2d_mscl", + CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4), + DIV(CLK_DOUT_CMU_G3D_SWITCH, "dout_cmu_g3d_switch", "gout_cmu_g3d_switch", + CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3), + DIV(CLK_DOUT_CMU_HPM, "dout_cmu_hpm", "gout_cmu_hpm", + CLK_CON_DIV_CLKCMU_HPM, 0, 2), + DIV(CLK_DOUT_CMU_ISP_BUS, "dout_cmu_isp_bus", "gout_cmu_isp_bus", + CLK_CON_DIV_CLKCMU_ISP_BUS, 0, 4), + DIV(CLK_DOUT_CMU_ISP_GDC, "dout_cmu_isp_gdc", "gout_cmu_isp_gdc", + CLK_CON_DIV_CLKCMU_ISP_GDC, 0, 4), + DIV(CLK_DOUT_CMU_ISP_VRA, "dout_cmu_isp_vra", "gout_cmu_isp_vra", + CLK_CON_DIV_CLKCMU_ISP_VRA, 0, 4), + DIV(CLK_DOUT_CMU_MFD_MFC, "dout_cmu_mfc_mfc", "gout_cmu_mfc_mfc", + CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4), + DIV(CLK_DOUT_CMU_MFD_WFD, "dout_cmu_mfc_wfd", "gout_cmu_mfc_wfd", + CLK_CON_DIV_CLKCMU_MFC_WFD, 0, 4), + DIV(CLK_DOUT_CMU_MIF_BUSP, "dout_cmu_mif_busp", "gout_cmu_mif_busp", + CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 3), + DIV(CLK_DOUT_CMU_PERI_BUS, "dout_cmu_peri_bus", "gout_cmu_peri_bus", + CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4), + DIV(CLK_DOUT_CMU_PERI_IP, "dout_cmu_peri_ip", "gout_cmu_peri_ip", + CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4), + DIV(CLK_DOUT_CMU_PERI_UART, "dout_cmu_peri_uart", "gout_cmu_peri_uart", + CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4), + DIV(CLK_DOUT_CMU_USB_BUS, "dout_cmu_usb_bus", "gout_cmu_usb_bus", + CLK_CON_DIV_CLKCMU_USB_BUS, 0, 4), + DIV(CLK_DOUT_CMU_USB_DPGTC, "dout_cmu_usb_dpgtc", "gout_cmu_usb_dpgtc", + CLK_CON_DIV_CLKCMU_USB_DPGTC, 0, 4), + DIV(CLK_DOUT_CMU_USB_BUS, "dout_cmu_usb_usb30drd", "gout_cmu_usb_usb30drd= ", + CLK_CON_DIV_CLKCMU_USB_USB30DRD, 0, 4), + DIV(CLK_DOUT_CMU_VIPX1_BUS, "dout_cmu_vipx1_bus", "gout_cmu_vipx1_bus", + CLK_CON_DIV_CLKCMU_VIPX1_BUS, 0, 4), + DIV(CLK_DOUT_CMU_VIPX2_BUS, "dout_cmu_vipx2_bus", "gout_cmu_vipx2_bus", + CLK_CON_DIV_CLKCMU_VIPX2_BUS, 0, 4), + DIV(CLK_DOUT_CLK_CMU_CMUREF, "dout_clk_cmu_cmuref", "mout_clk_cmu_cmuref", + CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0, 2), +}; + +static const struct samsung_fixed_factor_clock top_ffactor_clks[] __initco= nst =3D { + FFACTOR(CLK_DOUT_CMU_OTP, "dout_cmu_otp", "oscclk", 1, 7, 0), +}; + +static const struct samsung_gate_clock top_gate_clks[] __initconst =3D { + GATE(CLK_GOUT_CMU_MIF_SWITCH, "gout_cmu_mif_switch", + "mux_cmu_mif_switch", CLK_CON_GAT_CLKCMU_MIF_SWITCH, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CLK_CMU_OTP_CLK, "gout_clk_cmu_otp_clk", "dout_cmu_otp", + CLK_CON_GAT_CLK_CMU_OTP_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMU_APM_BUS, "gout_cmu_apm_bus", "mout_cmu_apm_bus", + CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, 0, 0), + GATE(CLK_GOUT_CMU_CAM_BUS, "gout_cmu_cam_bus", "mout_cmu_cam_bus", + CLK_CON_GAT_GATE_CLKCMU_CAM_BUS, 21, 0, 0), + GATE(CLK_GOUT_CMU_CIS_CLK0, "gout_cmu_cis_clk0", "mout_cmu_cis_clk0", + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 21, 0, 0), + GATE(CLK_GOUT_CMU_CIS_CLK1, "gout_cmu_cis_clk1", "mout_cmu_cis_clk1", + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 21, 0, 0), + GATE(CLK_GOUT_CMU_CIS_CLK2, "gout_cmu_cis_clk2", "mout_cmu_cis_clk2", + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 21, 0, 0), + GATE(CLK_GOUT_CMU_CIS_CLK3, "gout_cmu_cis_clk3", "mout_cmu_cis_clk3", + CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 21, 0, 0), + GATE(CLK_GOUT_CMU_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus", + CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_CMU_CORE_CCI, "gout_cmu_core_cci", "mout_cmu_core_cci", + CLK_CON_GAT_GATE_CLKCMU_CORE_CCI, 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_CMU_CORE_G3D, "gout_cmu_core_g3d", "mout_cmu_core_g3d", + CLK_CON_GAT_GATE_CLKCMU_CORE_G3D, 21, CLK_IS_CRITICAL, 0), + GATE(CLK_GOUT_CMU_CPUCL0_DBG, "gout_cmu_cpucl0_dbg", "mout_cmu_cpucl0_dbg= ", + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG, 21, 0, 0), + GATE(CLK_GOUT_CMU_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch", "mout_cmu_cpuc= l0_switch", + CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, 0, 0), + GATE(CLK_GOUT_CMU_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch", "mout_cmu_cpuc= l1_switch", + CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, 0, 0), + GATE(CLK_GOUT_CMU_DISPAUD_AUD, "gout_cmu_dispaud_aud", "mout_cmu_dispaud_= aud", + CLK_CON_GAT_GATE_CLKCMU_DISPAUD_AUD, 21, 0, 0), + GATE(CLK_GOUT_CMU_DISPAUD_CPU, "gout_cmu_dispaud_cpu", "mout_cmu_dispaud_= cpu", + CLK_CON_GAT_GATE_CLKCMU_DISPAUD_CPU, 21, 0, 0), + GATE(CLK_GOUT_CMU_DISPAUD_DISP, "gout_cmu_dispaud_disp", "mout_cmu_dispau= d_disp", + CLK_CON_GAT_GATE_CLKCMU_DISPAUD_DISP, 21, 0, 0), + GATE(CLK_GOUT_CMU_FSYS_BUS, "gout_cmu_fsys_bus", "mout_cmu_fsys_bus", + CLK_CON_GAT_GATE_CLKCMU_FSYS_BUS, 21, 0, 0), + GATE(CLK_GOUT_CMU_FSYS_MMC_CARD, "gout_cmu_fsys_mmc_card", "mout_cmu_fsys= _mmc_card", + CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_CARD, 21, 0, 0), + GATE(CLK_GOUT_CMU_FSYS_MMC_EMBD, "gout_cmu_fsys_mmc_embd", "mout_cmu_fsys= _mmc_embd", + CLK_CON_GAT_GATE_CLKCMU_FSYS_MMC_EMBD, 21, 0, 0), + GATE(CLK_GOUT_CMU_FSYS_UFS_EMBD, "gout_cmu_fsys_ufs_embd", "mout_cmu_fsys= _ufs_embd", + CLK_CON_GAT_GATE_CLKCMU_FSYS_UFS_EMBD, 21, 0, 0), + GATE(CLK_GOUT_CMU_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d", + CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0), + GATE(CLK_GOUT_CMU_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl", + CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0), + GATE(CLK_GOUT_CMU_G3D_SWITCH, "gout_cmu_g3d_switch", "mout_cmu_g3d_switch= ", + CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0), + GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm", + CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0), + GATE(CLK_GOUT_CMU_ISP_BUS, "gout_cmu_isp_bus", "mout_cmu_isp_bus", + CLK_CON_GAT_GATE_CLKCMU_ISP_BUS, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMU_ISP_GDC, "gout_cmu_isp_gdc", "mout_cmu_isp_gdc", + CLK_CON_GAT_GATE_CLKCMU_ISP_GDC, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMU_ISP_VRA, "gout_cmu_isp_vra", "mout_cmu_isp_vra", + CLK_CON_GAT_GATE_CLKCMU_ISP_VRA, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMU_MFC_MFC, "gout_cmu_mfc_mfc", "mout_cmu_mfc_mfc", + CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMU_MFC_WFD, "gout_cmu_mfc_wfd", "mout_cmu_mfc_wfd", + CLK_CON_GAT_GATE_CLKCMU_MFC_WFD, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMU_MIF_BUSP, "gout_cmu_mif_busp", "mout_cmu_mif_busp", + CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMU_MODEM_SHARED0, "gout_cmu_modem_shared0", "dout_cmu_shar= ed0_div2", + CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMU_MODEM_SHARED1, "gout_cmu_modem_shared1", "dout_cmu_shar= ed1_div2", + CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMU_PERI_BUS, "gout_cmu_peri_bus", "mout_cmu_peri_bus", + CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0), + GATE(CLK_GOUT_CMU_PERI_IP, "gout_cmu_peri_ip", "mout_cmu_peri_ip", + CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0), + GATE(CLK_GOUT_CMU_PERI_UART, "gout_cmu_peri_uart", "mout_cmu_peri_uart", + CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 21, 0, 0), + GATE(CLK_GOUT_CMU_USB_BUS, "gout_cmu_usb_bus", "mout_cmu_usb_bus", + CLK_CON_GAT_GATE_CLKCMU_USB_BUS, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMU_USB_DPGTC, "gout_cmu_usb_dpgtc", "mout_cmu_usb_dpgtc", + CLK_CON_GAT_GATE_CLKCMU_USB_DPGTC, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMU_USB_USB30DRD, "gout_cmu_usb_usb30drd", "mout_cmu_usb_us= b30drd", + CLK_CON_GAT_GATE_CLKCMU_USB_USB30DRD, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMU_VIPX1_BUS, "gout_cmu_vipx1_bus", "mout_cmu_vipx1_bus", + CLK_CON_GAT_GATE_CLKCMU_VIPX1_BUS, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMU_VIPX2_BUS, "gout_cmu_vipx2_bus", "mout_cmu_vipx2_bus", + CLK_CON_GAT_GATE_CLKCMU_VIPX2_BUS, 21, CLK_IGNORE_UNUSED, 0), +}; + +static const struct samsung_cmu_info top_cmu_info __initconst =3D { + .pll_clks =3D top_pll_clks, + .nr_pll_clks =3D ARRAY_SIZE(top_pll_clks), + .mux_clks =3D top_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(top_mux_clks), + .div_clks =3D top_div_clks, + .nr_div_clks =3D ARRAY_SIZE(top_div_clks), + .fixed_factor_clks =3D top_ffactor_clks, + .nr_fixed_factor_clks =3D ARRAY_SIZE(top_ffactor_clks), + .gate_clks =3D top_gate_clks, + .nr_gate_clks =3D ARRAY_SIZE(top_gate_clks), + .nr_clk_ids =3D CLKS_NR_TOP, + .clk_regs =3D top_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(top_clk_regs), +}; + +static void __init exynos9610_cmu_top_init(struct device_node *np) +{ + exynos_arm64_register_cmu(NULL, np, &top_cmu_info); +} + +/* Register CMU_TOP early, as it's a dependency for other early domains */ +CLK_OF_DECLARE(exynos9610_cmu_top, "samsung,exynos9610-cmu-top", + exynos9610_cmu_top_init); + +/* CMU_CPUCL0 */ +#define PLL_LOCKTIME_PLL_CPUCL0 0x0000 +#define PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER 0x0100 +#define PLL_CON2_MUX_CLKCMU_CPUCL0_DBG_USER 0x0108 +#define PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER 0x0120 +#define PLL_CON2_MUX_CLKCMU_CPUCL0_SWITCH_USER 0x0128 +#define PLL_CON0_PLL_CPUCL0 0x0140 +#define CLK_CON_MUX_MUX_CLK_CPUCL0_PLL 0x1000 +#define CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK 0x1800 +#define CLK_CON_DIV_DIV_CLK_CLUSTER0_CNTCLK 0x1804 +#define CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG 0x1808 +#define CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF 0x180c +#define CLK_CON_DIV_DIV_CLK_CPUCL0_CPU 0x1810 +#define CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK 0x1814 +#define CLK_CON_GAT_CLK_CPUCL0_CMU_PCLK 0x2000 +#define CLK_CON_GAT_CLK_CPUCL0_HPM_TARGETCLK_C 0x2004 +#define CLK_CON_GAT_CLK_CPUCL0_OSCCLK_CLK 0x2008 +#define CLK_CON_GAT_GATE_CLK_CLUSTER0_CPU 0x2010 +#define CLK_CON_GAT_GOUT_CPUCL0_ADM_APB_G_CSSYS_CORE_PCLKM 0x2014 +#define CLK_CON_GAT_GOUT_CPUCL0_ADS_AHB_G_CSSYS_FSYS_HCLKS 0x2018 +#define CLK_CON_GAT_GOUT_CPUCL0_ADS_APB_G_CSSYS_CPUCL1_PCLKS 0x201c +#define CLK_CON_GAT_GOUT_CPUCL0_ADS_APB_G_P8Q_PCLKS 0x2020 +#define CLK_CON_GAT_GOUT_CPUCL0_AD_APB_P_DUMP_PC_CPUCL0_PCLKM 0x2024 +#define CLK_CON_GAT_GOUT_CPUCL0_AD_APB_P_DUMP_PC_CPUCL1_PCLKM 0x2028 +#define CLK_CON_GAT_GOUT_CPUCL0_BUSIF_HPMCPUCL0_PCLK 0x202c +#define CLK_CON_GAT_GOUT_CPUCL0_CSSYS_DBG_PCLKDBG 0x2030 +#define CLK_CON_GAT_GOUT_CPUCL0_DUMP_PC_CPUCL0_PCLK 0x2034 +#define CLK_CON_GAT_GOUT_CPUCL0_DUMP_PC_CPUCL1_PCLK 0x2038 +#define CLK_CON_GAT_GOUT_CPUCL0_LHM_AXI_P_CPUCL0_CLK 0x203c +#define CLK_CON_GAT_GOUT_CPUCL0_LHS_AXI_D_CSSYS_CLK 0x2040 +#define CLK_CON_GAT_GOUT_CPUCL0_DBG_CLK 0x2044 +#define CLK_CON_GAT_GOUT_CPUCL0_PCLK_CLK 0x2048 +#define CLK_CON_GAT_GOUT_CPUCL0_SECJTAG_CLK 0x204c +#define CLK_CON_GAT_GOUT_CPUCL0_SYSREG_PCLK 0x2050 + +static const unsigned long cpucl0_clk_regs[] __initconst =3D { + PLL_LOCKTIME_PLL_CPUCL0, + PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER, + PLL_CON2_MUX_CLKCMU_CPUCL0_DBG_USER, + PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER, + PLL_CON2_MUX_CLKCMU_CPUCL0_SWITCH_USER, + PLL_CON0_PLL_CPUCL0, + CLK_CON_MUX_MUX_CLK_CPUCL0_PLL, + CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK, + CLK_CON_DIV_DIV_CLK_CLUSTER0_CNTCLK, + CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG, + CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF, + CLK_CON_DIV_DIV_CLK_CPUCL0_CPU, + CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK, + CLK_CON_GAT_CLK_CPUCL0_CMU_PCLK, + CLK_CON_GAT_CLK_CPUCL0_HPM_TARGETCLK_C, + CLK_CON_GAT_CLK_CPUCL0_OSCCLK_CLK, + CLK_CON_GAT_GATE_CLK_CLUSTER0_CPU, + CLK_CON_GAT_GOUT_CPUCL0_ADM_APB_G_CSSYS_CORE_PCLKM, + CLK_CON_GAT_GOUT_CPUCL0_ADS_AHB_G_CSSYS_FSYS_HCLKS, + CLK_CON_GAT_GOUT_CPUCL0_ADS_APB_G_CSSYS_CPUCL1_PCLKS, + CLK_CON_GAT_GOUT_CPUCL0_ADS_APB_G_P8Q_PCLKS, + CLK_CON_GAT_GOUT_CPUCL0_AD_APB_P_DUMP_PC_CPUCL0_PCLKM, + CLK_CON_GAT_GOUT_CPUCL0_AD_APB_P_DUMP_PC_CPUCL1_PCLKM, + CLK_CON_GAT_GOUT_CPUCL0_BUSIF_HPMCPUCL0_PCLK, + CLK_CON_GAT_GOUT_CPUCL0_CSSYS_DBG_PCLKDBG, + CLK_CON_GAT_GOUT_CPUCL0_DUMP_PC_CPUCL0_PCLK, + CLK_CON_GAT_GOUT_CPUCL0_DUMP_PC_CPUCL1_PCLK, + CLK_CON_GAT_GOUT_CPUCL0_LHM_AXI_P_CPUCL0_CLK, + CLK_CON_GAT_GOUT_CPUCL0_LHS_AXI_D_CSSYS_CLK, + CLK_CON_GAT_GOUT_CPUCL0_DBG_CLK, + CLK_CON_GAT_GOUT_CPUCL0_PCLK_CLK, + CLK_CON_GAT_GOUT_CPUCL0_SECJTAG_CLK, + CLK_CON_GAT_GOUT_CPUCL0_SYSREG_PCLK, +}; + +static const struct samsung_pll_rate_table pll_cpucl0_rate_table[] __initc= onst =3D { + PLL_35XX_RATE(26 * MHZ, 1049750000U, 323, 4, 1), + PLL_35XX_RATE(26 * MHZ, 1449500000U, 223, 4, 0), + PLL_35XX_RATE(26 * MHZ, 1850333333U, 427, 6, 0), + PLL_35XX_RATE(26 * MHZ, 300083333U, 277, 6, 2), + PLL_35XX_RATE(26 * MHZ, 600166666U, 277, 6, 1), +}; + +static const struct samsung_pll_clock cpucl0_pll_clks[] __initconst =3D { + PLL(pll_1051x, CLK_FOUT_CPUCL0_PLL, "fout_cpucl0_pll", "oscclk", + PLL_LOCKTIME_PLL_CPUCL0, PLL_CON0_PLL_CPUCL0, pll_cpucl0_rate_table), +}; + +PNAME(mout_pll_cpucl0_dbg_user_p) =3D { "oscclk", + "dout_cmu_cpucl0_dbg" }; +PNAME(mout_pll_cpucl0_switch_user_p) =3D { "oscclk", + "dout_cmu_cpucl0_switch" }; +PNAME(mout_clk_cpucl0_pll_p) =3D { "fout_cpucl0_pll", + "mout_pll_cpucl0_switch_user" }; + +static const struct samsung_mux_clock cpucl0_mux_clks[] __initconst =3D { + MUX(CLK_MOUT_PLL_CPUCL0_DBG_USER, "mout_pll_cpucl0_dbg_user", mout_pll_cp= ucl0_dbg_user_p, + PLL_CON0_MUX_CLKCMU_CPUCL0_DBG_USER, 4, 1), + MUX(CLK_MOUT_PLL_CPUCL0_SWITCH_USER, "mout_pll_cpucl0_switch_user", + mout_pll_cpucl0_switch_user_p, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER= , 4, 1), + MUX(CLK_MOUT_CLK_CPUCL0_PLL, "mout_clk_cpucl0_pll", mout_clk_cpucl0_pll_p, + CLK_CON_MUX_MUX_CLK_CPUCL0_PLL, 0, 1), +}; + +static const struct samsung_div_clock cpucl0_div_clks[] __initconst =3D { + DIV(CLK_DOUT_CLK_CLUSTER0_ACLK, "dout_clk_cluster0_aclk", "gout_clk_clust= er0_cpu", + CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK, 0, 4), + DIV(CLK_DOUT_CLK_CLUSTER0_CNTCLK, "dout_clk_cluster0_cntclk", "gout_clk_c= luster0_cpu", + CLK_CON_DIV_DIV_CLK_CLUSTER0_CNTCLK, 0, 4), + DIV(CLK_DOUT_CLK_CLUSTER0_PCLKDBG, "dout_clk_cluster0_pclkdbg", "gout_clk= _cluster0_cpu", + CLK_CON_DIV_DIV_CLK_CLUSTER0_PCLKDBG, 0, 4), + DIV(CLK_DOUT_CLK_CPUCL0_CMUREF, "dout_clk_cpucl0_cmuref", "dout_clk_cpucl= 0_cpu", + CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF, 0, 3), + DIV(CLK_DOUT_CLK_CPUCL0_CPU, "dout_clk_cpucl0_cpu", "mout_clk_cpucl0_pll", + CLK_CON_DIV_DIV_CLK_CPUCL0_CPU, 0, 0), + DIV(CLK_DOUT_CLK_CPUCL0_PCLK, "dout_clk_cpucl0_pclk", "dout_clk_cpucl0_cp= u", + CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK, 0, 4), +}; + +static const struct samsung_gate_clock cpucl0_gate_clks[] __initconst =3D { + GATE(CLK_GOUT_CLK_CPUCL0_CMU_PCLK, "gout_clk_cpucl0_cmu_pclk", + "dout_clk_cpucl0_pclk", CLK_CON_GAT_CLK_CPUCL0_CMU_PCLK, 21, CLK_IGN= ORE_UNUSED, 0), + GATE(CLK_GOUT_CLK_CPUCL0_HPM_TARGETCLK_C, "gout_clk_cpucl0_hpm_targetclk_= c", + "dout_cmu_hpm", CLK_CON_GAT_CLK_CPUCL0_HPM_TARGETCLK_C, 21, CLK_IGNO= RE_UNUSED, 0), + GATE(CLK_GOUT_CLK_CPUCL0_OSCCLK_CLK, "gout_clk_cpucl0_oscclk_clk", + "oscclk", CLK_CON_GAT_CLK_CPUCL0_OSCCLK_CLK, 21, CLK_IGNORE_UNUSED, = 0), + GATE(CLK_GOUT_CLK_CLUSTER0_CPU, "gout_clk_cluster0_cpu", + "dout_clk_cpucl0_cpu", CLK_CON_GAT_GATE_CLK_CLUSTER0_CPU, 21, CLK_IG= NORE_UNUSED, 0), + GATE(CLK_GOUT_CPUCL0_ADM_APB_G_CSSYS_CORE_PCLKM, "gout_cpucl0_adm_apb_g_c= ssys_core_pclkm", + "mout_pll_cpucl0_dbg_user", CLK_CON_GAT_GOUT_CPUCL0_ADM_APB_G_CSSYS_= CORE_PCLKM, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CPUCL0_ADS_AHB_G_CSSYS_FSYS_HCLKS, "gout_cpucl0_ads_ahb_g_c= ssys_fsys_hclks", + "mout_pll_cpucl0_dbg_user", CLK_CON_GAT_GOUT_CPUCL0_ADS_AHB_G_CSSYS_= FSYS_HCLKS, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CPUCL0_ADS_APB_G_CSSYS_CPUCL1_PCLKS, + "gout_cpucl0_ads_apb_g_cssys_cpucl1_pclks", "mout_pll_cpucl0_dbg_use= r", + CLK_CON_GAT_GOUT_CPUCL0_ADS_APB_G_CSSYS_CPUCL1_PCLKS, 21, CLK_IGNORE= _UNUSED, 0), + GATE(CLK_GOUT_CPUCL0_ADS_APB_G_P8Q_PCLKS, "gout_cpucl0_ads_apb_g_p8q_pclk= s", + "mout_pll_cpucl0_dbg_user", CLK_CON_GAT_GOUT_CPUCL0_ADS_APB_G_P8Q_PC= LKS, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CPUCL0_AD_APB_P_DUMP_PC_CPUCL0_PCLKM, + "gout_cpucl0_ad_apb_p_dump_pc_cpucl0_pclkm", "mout_pll_cpucl0_dbg_us= er", + CLK_CON_GAT_GOUT_CPUCL0_AD_APB_P_DUMP_PC_CPUCL0_PCLKM, 21, CLK_IGNOR= E_UNUSED, 0), + GATE(CLK_GOUT_CPUCL0_AD_APB_P_DUMP_PC_CPUCL1_PCLKM, + "gout_cpucl0_ad_apb_p_dump_pc_cpucl1_pclkm", "mout_pll_cpucl0_dbg_us= er", + CLK_CON_GAT_GOUT_CPUCL0_AD_APB_P_DUMP_PC_CPUCL1_PCLKM, 21, CLK_IGNOR= E_UNUSED, 0), + GATE(CLK_GOUT_CPUCL0_BUSIF_HPMCPUCL0_PCLK, "gout_cpucl0_busif_hpmcpucl0_p= clk", + "dout_clk_cpucl0_pclk", CLK_CON_GAT_GOUT_CPUCL0_BUSIF_HPMCPUCL0_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CPUCL0_CSSYS_DBG_PCLKDBG, "gout_cpucl0_cssys_dbg_pclkdbg", + "mout_pll_cpucl0_dbg_user", CLK_CON_GAT_GOUT_CPUCL0_CSSYS_DBG_PCLKDB= G, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CPUCL0_DUMP_PC_CPUCL0_PCLK, "gout_cpucl0_dump_pc_cpucl0_pcl= k", + "mout_pll_cpucl0_dbg_user", CLK_CON_GAT_GOUT_CPUCL0_DUMP_PC_CPUCL0_P= CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CPUCL0_DUMP_PC_CPUCL1_PCLK, "gout_cpucl0_dump_pc_cpucl1_pcl= k", + "mout_pll_cpucl0_dbg_user", CLK_CON_GAT_GOUT_CPUCL0_DUMP_PC_CPUCL1_P= CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CPUCL0_LHM_AXI_P_CPUCL0_CLK, "gout_cpucl0_lhm_axi_p_cpucl0_= clk", + "dout_clk_cpucl0_pclk", CLK_CON_GAT_GOUT_CPUCL0_LHM_AXI_P_CPUCL0_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CPUCL0_LHS_AXI_D_CSSYS_CLK, "gout_cpucl0_lhs_axi_d_cssys_cl= k", + "mout_pll_cpucl0_dbg_user", CLK_CON_GAT_GOUT_CPUCL0_LHS_AXI_D_CSSYS_= CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CPUCL0_DBG_CLK, "gout_cpucl0_dbg_clk", + "mout_pll_cpucl0_dbg_user", CLK_CON_GAT_GOUT_CPUCL0_DBG_CLK, 21, CLK= _IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CPUCL0_PCLK_CLK, "gout_cpucl0_pclk_clk", + "dout_clk_cpucl0_pclk", CLK_CON_GAT_GOUT_CPUCL0_PCLK_CLK, 21, CLK_IG= NORE_UNUSED, 0), + GATE(CLK_GOUT_CPUCL0_SECJTAG_CLK, "gout_cpucl0_secjtag_clk", "mout_pll_cp= ucl0_dbg_user", + CLK_CON_GAT_GOUT_CPUCL0_SECJTAG_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CPUCL0_SYSREG_PCLK, "gout_cpucl0_sysreg_pclk", + "dout_clk_cpucl0_pclk", CLK_CON_GAT_GOUT_CPUCL0_SYSREG_PCLK, 21, 0, = 0), +}; + +static const struct samsung_cmu_info cpucl0_cmu_info __initconst =3D { + .pll_clks =3D cpucl0_pll_clks, + .nr_pll_clks =3D ARRAY_SIZE(cpucl0_pll_clks), + .mux_clks =3D cpucl0_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(cpucl0_mux_clks), + .div_clks =3D cpucl0_div_clks, + .nr_div_clks =3D ARRAY_SIZE(cpucl0_div_clks), + .gate_clks =3D cpucl0_gate_clks, + .nr_gate_clks =3D ARRAY_SIZE(cpucl0_gate_clks), + .nr_clk_ids =3D CLKS_NR_CPUCL0, + .clk_regs =3D cpucl0_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(cpucl0_clk_regs), +}; + +static void __init exynos9610_cmu_cpucl0_init(struct device_node *np) +{ + exynos_arm64_register_cmu(NULL, np, &cpucl0_cmu_info); +} + +CLK_OF_DECLARE(exynos9610_cmu_cpucl0, "samsung,exynos9610-cmu-cpucl0", + exynos9610_cmu_cpucl0_init); + +/* CMU_CPUCL1 */ +#define PLL_LOCKTIME_PLL_CPUCL1 0x0000 +#define PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER 0x0100 +#define PLL_CON2_MUX_CLKCMU_CPUCL1_SWITCH_USER 0x0108 +#define PLL_CON0_PLL_CPUCL1 0x0120 +#define CLK_CON_MUX_MUX_CLK_CPUCL1_PLL 0x1000 +#define CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK 0x1800 +#define CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK 0x1804 +#define CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF 0x180c +#define CLK_CON_DIV_DIV_CLK_CPUCL1_CPU 0x1810 +#define CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK 0x1814 +#define CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG 0x1818 +#define CLK_CON_GAT_CLK_CPUCL1_CMU_PCLK 0x2000 +#define CLK_CON_GAT_CLK_CPUCL1_HPM_TARGETCLK_C 0x2004 +#define CLK_CON_GAT_CLK_CPUCL1_OSCCLK_CLK 0x2008 +#define CLK_CON_GAT_GATE_CLK_CLUSTER1_CPU 0x2010 +#define CLK_CON_GAT_GOUT_CPUCL1_ADM_APB_G_CSSYS_CPUCL1_PCLKM 0x2014 +#define CLK_CON_GAT_GOUT_CPUCL1_BUSIF_HPMCPUCL1_PCLK 0x2018 +#define CLK_CON_GAT_GOUT_CPUCL1_LHM_AXI_P_CPUCL1_CLK 0x201c +#define CLK_CON_GAT_GOUT_CPUCL1_LHS_ACE_D_CLK 0x2020 +#define CLK_CON_GAT_GOUT_CPUCL1_ACLK_CLK 0x2024 +#define CLK_CON_GAT_GOUT_CPUCL1_PCLKDBG_CLK 0x2028 +#define CLK_CON_GAT_GOUT_CPUCL1_PCLK_CLK 0x202c +#define CLK_CON_GAT_GOUT_CPUCL1_SYSREG_PCLK 0x2030 + +static const unsigned long cpucl1_clk_regs[] __initconst =3D { + PLL_LOCKTIME_PLL_CPUCL1, + PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, + PLL_CON2_MUX_CLKCMU_CPUCL1_SWITCH_USER, + PLL_CON0_PLL_CPUCL1, + CLK_CON_MUX_MUX_CLK_CPUCL1_PLL, + CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK, + CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK, + CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF, + CLK_CON_DIV_DIV_CLK_CPUCL1_CPU, + CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK, + CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG, + CLK_CON_GAT_CLK_CPUCL1_CMU_PCLK, + CLK_CON_GAT_CLK_CPUCL1_HPM_TARGETCLK_C, + CLK_CON_GAT_CLK_CPUCL1_OSCCLK_CLK, + CLK_CON_GAT_GATE_CLK_CLUSTER1_CPU, + CLK_CON_GAT_GOUT_CPUCL1_ADM_APB_G_CSSYS_CPUCL1_PCLKM, + CLK_CON_GAT_GOUT_CPUCL1_BUSIF_HPMCPUCL1_PCLK, + CLK_CON_GAT_GOUT_CPUCL1_LHM_AXI_P_CPUCL1_CLK, + CLK_CON_GAT_GOUT_CPUCL1_LHS_ACE_D_CLK, + CLK_CON_GAT_GOUT_CPUCL1_ACLK_CLK, + CLK_CON_GAT_GOUT_CPUCL1_PCLKDBG_CLK, + CLK_CON_GAT_GOUT_CPUCL1_PCLK_CLK, + CLK_CON_GAT_GOUT_CPUCL1_SYSREG_PCLK, +}; + +static const struct samsung_pll_rate_table pll_cpucl1_rate_table[] __initc= onst =3D { + PLL_35XX_RATE(26 * MHZ, 1499333333U, 346, 3, 1), + PLL_35XX_RATE(26 * MHZ, 1898000000U, 292, 4, 0), + PLL_35XX_RATE(26 * MHZ, 2400666666U, 277, 3, 0), + PLL_35XX_RATE(26 * MHZ, 549900000U, 423, 5, 2), + PLL_35XX_RATE(26 * MHZ, 850200000U, 327, 5, 1), +}; + +static const struct samsung_pll_clock cpucl1_pll_clks[] __initconst =3D { + PLL(pll_1051x, CLK_FOUT_CPUCL1_PLL, "fout_cpucl1_pll", "oscclk", + PLL_LOCKTIME_PLL_CPUCL1, PLL_CON0_PLL_CPUCL1, pll_cpucl1_rate_table), +}; + +PNAME(mout_pll_cpucl1_switch_user_p) =3D { "oscclk", + "dout_cmu_cpucl1_switch" }; +PNAME(mout_clk_cpucl1_pll_p) =3D { "fout_cpucl1_pll", + "mout_pll_cpucl1_switch_user" }; + +static const struct samsung_mux_clock cpucl1_mux_clks[] __initconst =3D { + MUX(CLK_MOUT_PLL_CPUCL1_SWITCH_USER, "mout_pll_cpucl1_switch_user", + mout_pll_cpucl1_switch_user_p, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, + 4, 1), + MUX(CLK_MOUT_CLK_CPUCL1_PLL, "mout_clk_cpucl1_pll", mout_clk_cpucl1_pll_p, + CLK_CON_MUX_MUX_CLK_CPUCL1_PLL, 0, 1), +}; + +static const struct samsung_div_clock cpucl1_div_clks[] __initconst =3D { + DIV(CLK_DOUT_CLK_CLUSTER1_ACLK, "dout_clk_cluster1_aclk", "gout_clk_clust= er1_cpu", + CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK, 0, 4), + DIV(CLK_DOUT_CLK_CLUSTER1_CNTCLK, "dout_clk_cluster1_cntclk", "gout_clk_c= luster1_cpu", + CLK_CON_DIV_DIV_CLK_CLUSTER0_CNTCLK, 0, 4), + DIV(CLK_DOUT_CLK_CPUCL1_CMUREF, "dout_clk_cpucl1_cmuref", "dout_clk_cpucl= 1_cpu", + CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF, 0, 4), + DIV(CLK_DOUT_CLK_CPUCL1_CPU, "dout_clk_cpucl1_cpu", "mout_clk_cpucl1_pll", + CLK_CON_DIV_DIV_CLK_CPUCL0_CPU, 0, 0), + DIV(CLK_DOUT_CLK_CPUCL1_PCLK, "dout_clk_cpucl1_pclk", "dout_clk_cpucl1_cp= u", + CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK, 0, 4), + DIV(CLK_DOUT_CLK_CPUCL1_PCLKDBG, "dout_clk_cpucl1_pclkdbg", "dout_clk_cpu= cl1_cpu", + CLK_CON_DIV_DIV_CLK_CPUCL1_PCLKDBG, 0, 4), +}; + +static const struct samsung_gate_clock cpucl1_gate_clks[] __initconst =3D { + GATE(CLK_GOUT_CLK_CPUCL1_CMU_PCLK, "gout_clk_cpucl1_cmu_pclk", + "dout_clk_cpucl1_pclk", CLK_CON_GAT_CLK_CPUCL0_CMU_PCLK, 21, CLK_IGN= ORE_UNUSED, 0), + GATE(CLK_GOUT_CLK_CPUCL1_HPM_TARGETCLK_C, "gout_clk_cpucl1_hpm_targetclk_= c", + "dout_cmu_hpm", CLK_CON_GAT_CLK_CPUCL1_HPM_TARGETCLK_C, 21, CLK_IGNO= RE_UNUSED, 0), + GATE(CLK_GOUT_CLK_CPUCL1_OSCCLK_CLK, "gout_clk_cpucl1_oscclk_clk", + "oscclk", CLK_CON_GAT_CLK_CPUCL1_OSCCLK_CLK, 21, CLK_IGNORE_UNUSED, = 0), + GATE(CLK_GOUT_CLK_CLUSTER1_CPU, "gout_clk_cluster1_cpu", + "dout_clk_cpucl1_cpu", CLK_CON_GAT_GATE_CLK_CLUSTER1_CPU, 21, CLK_IG= NORE_UNUSED, 0), + GATE(CLK_GOUT_CPUCL1_ADM_APB_G_CSSYS_CPUCL1_PCLKM, + "gout_cpucl1_adm_apb_g_cssys_cpucl1_pclkm", "dout_clk_cpucl1_pclkdbg= ", + CLK_CON_GAT_GOUT_CPUCL1_ADM_APB_G_CSSYS_CPUCL1_PCLKM, 21, CLK_IGNORE= _UNUSED, 0), + GATE(CLK_GOUT_CPUCL1_BUSIF_HPMCPUCL1_PCLK, "gout_cpucl0_busif_hpmcpucl1_p= clk", + "dout_clk_cpucl1_pclk", CLK_CON_GAT_GOUT_CPUCL1_BUSIF_HPMCPUCL1_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CPUCL1_LHM_AXI_P_CPUCL1_CLK, "gout_cpucl1_lhm_axi_p_cpucl1_= clk", + "dout_clk_cpucl1_pclk", CLK_CON_GAT_GOUT_CPUCL1_LHM_AXI_P_CPUCL1_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CPUCL1_LHS_ACE_D_CLK, "gout_cpucl1_lhs_ace_d_clk", + "dout_clk_cluster1_aclk", CLK_CON_GAT_GOUT_CPUCL1_LHS_ACE_D_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CPUCL1_ACLK_CLK, "gout_cpucl1_aclk_clk", + "dout_clk_cluster1_aclk", CLK_CON_GAT_GOUT_CPUCL1_ACLK_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CPUCL1_PCLKDBG_CLK, "gout_cpucl1_pclkdbg_clk", + "dout_clk_cpucl1_pclkdbg", CLK_CON_GAT_GOUT_CPUCL1_PCLKDBG_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CPUCL1_PCLK_CLK, "gout_cpucl1_pclk_clk", + "dout_clk_cpucl1_pclk", CLK_CON_GAT_GOUT_CPUCL1_PCLK_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CPUCL1_SYSREG_PCLK, "gout_cpucl1_sysreg_pclk", + "dout_clk_cpucl1_pclk", CLK_CON_GAT_GOUT_CPUCL1_SYSREG_PCLK, + 21, 0, 0), +}; + +static const struct samsung_cmu_info cpucl1_cmu_info __initconst =3D { + .pll_clks =3D cpucl1_pll_clks, + .nr_pll_clks =3D ARRAY_SIZE(cpucl1_pll_clks), + .mux_clks =3D cpucl1_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(cpucl1_mux_clks), + .div_clks =3D cpucl1_div_clks, + .nr_div_clks =3D ARRAY_SIZE(cpucl1_div_clks), + .gate_clks =3D cpucl1_gate_clks, + .nr_gate_clks =3D ARRAY_SIZE(cpucl1_gate_clks), + .nr_clk_ids =3D CLKS_NR_CPUCL1, + .clk_regs =3D cpucl1_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(cpucl1_clk_regs), +}; + +static void __init exynos9610_cmu_cpucl1_init(struct device_node *np) +{ + exynos_arm64_register_cmu(NULL, np, &cpucl1_cmu_info); +} + +CLK_OF_DECLARE(exynos9610_cmu_cpucl1, "samsung,exynos9610-cmu-cpucl1", + exynos9610_cmu_cpucl1_init); + +/* CMU_PERI */ +#define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0100 // old +#define PLL_CON2_MUX_CLKCMU_PERI_BUS_USER 0x0108 +#define PLL_CON0_MUX_CLKCMU_PERI_IP_USER 0x0120 // old +#define PLL_CON2_MUX_CLKCMU_PERI_IP_USER 0x0128 +#define PLL_CON0_MUX_CLKCMU_PERI_UART_USER 0x0140 +#define PLL_CON2_MUX_CLKCMU_PERI_UART_USER 0x0148 +#define CLK_CON_DIV_DIV_CLK_PERI_I2C 0x1800 +#define CLK_CON_DIV_DIV_CLK_PERI_SPI0 0x1804 // old +#define CLK_CON_DIV_DIV_CLK_PERI_SPI1 0x1808 // old +#define CLK_CON_DIV_DIV_CLK_PERI_SPI2 0x180c // old +#define CLK_CON_DIV_DIV_CLK_PERI_USI_I2C 0x1814 +#define CLK_CON_DIV_DIV_CLK_PERI_USI_USI 0x1818 +#define CLK_CON_GAT_CLK_PERI_CMU_PCLK 0x2000 +#define CLK_CON_GAT_CLK_PERI_OSCCLK_CLK 0x2004 +#define CLK_CON_GAT_GATE_CLK_PERI_I2C 0x2008 +#define CLK_CON_GAT_GATE_CLK_PERI_SPI0 0x200c // old +#define CLK_CON_GAT_GATE_CLK_PERI_SPI1 0x2010 // old +#define CLK_CON_GAT_GATE_CLK_PERI_SPI2 0x2014 // old +#define CLK_CON_GAT_GATE_CLK_PERI_USI_I2C 0x2018 +#define CLK_CON_GAT_GATE_CLK_PERI_USI_USI 0x201c +#define CLK_CON_GAT_GOUT_PERI_AXI2AHB_MSD32_ACLK 0x2020 +#define CLK_CON_GAT_GOUT_PERI_BUSIF_TMU_PCLK 0x2024 +#define CLK_CON_GAT_GOUT_PERI_CAMI2C_0_IPCLK 0x2028 +#define CLK_CON_GAT_GOUT_PERI_CAMI2C_0_PCLK 0x202c +#define CLK_CON_GAT_GOUT_PERI_CAMI2C_1_IPCLK 0x2030 +#define CLK_CON_GAT_GOUT_PERI_CAMI2C_1_PCLK 0x2034 +#define CLK_CON_GAT_GOUT_PERI_CAMI2C_2_IPCLK 0x2038 +#define CLK_CON_GAT_GOUT_PERI_CAMI2C_2_PCLK 0x203c +#define CLK_CON_GAT_GOUT_PERI_CAMI2C_3_IPCLK 0x2040 +#define CLK_CON_GAT_GOUT_PERI_CAMI2C_3_PCLK 0x2044 +#define CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK 0x204c +#define CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK 0x2050 +#define CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK 0x2054 +#define CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK 0x2058 +#define CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK 0x205c +#define CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK 0x2060 +#define CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK 0x2064 +#define CLK_CON_GAT_GOUT_PERI_GPIO_PCLK 0x2048 +#define CLK_CON_GAT_GOUT_PERI_LHM_AXI_P_PERI_CLK 0x2068 +#define CLK_CON_GAT_GOUT_PERI_MCT_PCLK 0x206c // old +#define CLK_CON_GAT_GOUT_PERI_OTP_CON_TOP_PCLK 0x2070 +#define CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK_S0 0x2074 +#define CLK_CON_GAT_GOUT_PERI_BUS_CLK 0x2078 +#define CLK_CON_GAT_GOUT_PERI_I2C_CLK 0x207c +#define CLK_CON_GAT_GOUT_PERI_SPI_0_CLK 0x2080 +#define CLK_CON_GAT_GOUT_PERI_SPI_1_CLK 0x2084 +#define CLK_CON_GAT_GOUT_PERI_SPI_2_CLK 0x2088 +#define CLK_CON_GAT_GOUT_PERI_UART_CLK 0x208c +#define CLK_CON_GAT_GOUT_PERI_USI00_I2C_CLK 0x2090 +#define CLK_CON_GAT_GOUT_PERI_USI00_USI_CLK 0x2094 +#define CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK 0x2098 // old +#define CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK 0x209c // old +#define CLK_CON_GAT_GOUT_PERI_SPI_1_IPCLK 0x20a0 // old +#define CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK 0x20a4 // old +#define CLK_CON_GAT_GOUT_PERI_SPI_2_IPCLK 0x20a8 // old +#define CLK_CON_GAT_GOUT_PERI_SPI_2_PCLK 0x20ac // old +#define CLK_CON_GAT_GOUT_PERI_SYSREG_PCLK 0x20b0 +#define CLK_CON_GAT_GOUT_PERI_UART_IPCLK 0x20b4 +#define CLK_CON_GAT_GOUT_PERI_UART_PCLK 0x20b8 +#define CLK_CON_GAT_GOUT_PERI_USI00_I2C_IPCLK 0x20bc +#define CLK_CON_GAT_GOUT_PERI_USI00_I2C_PCLK 0x20c0 +#define CLK_CON_GAT_GOUT_PERI_USI00_USI_IPCLK 0x20c4 +#define CLK_CON_GAT_GOUT_PERI_USI00_USI_PCLK 0x20c8 +#define CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK 0x20cc +#define CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK 0x20d0 + +static const unsigned long peri_clk_regs[] __initconst =3D { + PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, + PLL_CON2_MUX_CLKCMU_PERI_BUS_USER, + PLL_CON0_MUX_CLKCMU_PERI_IP_USER, + PLL_CON2_MUX_CLKCMU_PERI_IP_USER, + PLL_CON0_MUX_CLKCMU_PERI_UART_USER, + PLL_CON2_MUX_CLKCMU_PERI_UART_USER, + CLK_CON_DIV_DIV_CLK_PERI_I2C, + CLK_CON_DIV_DIV_CLK_PERI_SPI0, + CLK_CON_DIV_DIV_CLK_PERI_SPI1, + CLK_CON_DIV_DIV_CLK_PERI_SPI2, + CLK_CON_DIV_DIV_CLK_PERI_USI_I2C, + CLK_CON_DIV_DIV_CLK_PERI_USI_USI, + CLK_CON_GAT_CLK_PERI_CMU_PCLK, + CLK_CON_GAT_CLK_PERI_OSCCLK_CLK, + CLK_CON_GAT_GATE_CLK_PERI_I2C, + CLK_CON_GAT_GATE_CLK_PERI_SPI0, + CLK_CON_GAT_GATE_CLK_PERI_SPI1, + CLK_CON_GAT_GATE_CLK_PERI_SPI2, + CLK_CON_GAT_GATE_CLK_PERI_USI_I2C, + CLK_CON_GAT_GATE_CLK_PERI_USI_USI, + CLK_CON_GAT_GOUT_PERI_AXI2AHB_MSD32_ACLK, + CLK_CON_GAT_GOUT_PERI_BUSIF_TMU_PCLK, + CLK_CON_GAT_GOUT_PERI_CAMI2C_0_IPCLK, + CLK_CON_GAT_GOUT_PERI_CAMI2C_0_PCLK, + CLK_CON_GAT_GOUT_PERI_CAMI2C_1_IPCLK, + CLK_CON_GAT_GOUT_PERI_CAMI2C_1_PCLK, + CLK_CON_GAT_GOUT_PERI_CAMI2C_2_IPCLK, + CLK_CON_GAT_GOUT_PERI_CAMI2C_2_PCLK, + CLK_CON_GAT_GOUT_PERI_CAMI2C_3_IPCLK, + CLK_CON_GAT_GOUT_PERI_CAMI2C_3_PCLK, + CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, + CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, + CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, + CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, + CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, + CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, + CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, + CLK_CON_GAT_GOUT_PERI_GPIO_PCLK, + CLK_CON_GAT_GOUT_PERI_LHM_AXI_P_PERI_CLK, + CLK_CON_GAT_GOUT_PERI_MCT_PCLK, + CLK_CON_GAT_GOUT_PERI_OTP_CON_TOP_PCLK, + CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK_S0, + CLK_CON_GAT_GOUT_PERI_BUS_CLK, + CLK_CON_GAT_GOUT_PERI_I2C_CLK, + CLK_CON_GAT_GOUT_PERI_SPI_0_CLK, + CLK_CON_GAT_GOUT_PERI_SPI_1_CLK, + CLK_CON_GAT_GOUT_PERI_SPI_2_CLK, + CLK_CON_GAT_GOUT_PERI_UART_CLK, + CLK_CON_GAT_GOUT_PERI_USI00_I2C_CLK, + CLK_CON_GAT_GOUT_PERI_USI00_USI_CLK, + CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, + CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, + CLK_CON_GAT_GOUT_PERI_SPI_1_IPCLK, + CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK, + CLK_CON_GAT_GOUT_PERI_SPI_2_IPCLK, + CLK_CON_GAT_GOUT_PERI_SPI_2_PCLK, + CLK_CON_GAT_GOUT_PERI_SYSREG_PCLK, + CLK_CON_GAT_GOUT_PERI_UART_IPCLK, + CLK_CON_GAT_GOUT_PERI_UART_PCLK, + CLK_CON_GAT_GOUT_PERI_USI00_I2C_IPCLK, + CLK_CON_GAT_GOUT_PERI_USI00_I2C_PCLK, + CLK_CON_GAT_GOUT_PERI_USI00_USI_IPCLK, + CLK_CON_GAT_GOUT_PERI_USI00_USI_PCLK, + CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK, + CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK, +}; + +PNAME(mout_pll_peri_bus_user_p) =3D { "oscclk", "dout_cmu_peri_bus" }; +PNAME(mout_pll_peri_ip_user_p) =3D { "oscclk", "dout_cmu_peri_ip" }; +PNAME(mout_pll_peri_uart_user_p) =3D { "oscclk", "dout_cmu_peri_uart" }; + +static const struct samsung_mux_clock peri_mux_clks[] __initconst =3D { + MUX(CLK_MOUT_PLL_PERI_BUS_USER, "mout_pll_peri_bus_user", mout_pll_peri_b= us_user_p, + PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1), + MUX(CLK_MOUT_PLL_PERI_IP_USER, "mout_pll_peri_ip_user", mout_pll_peri_ip_= user_p, + PLL_CON0_MUX_CLKCMU_PERI_IP_USER, 4, 1), + MUX(CLK_MOUT_PLL_PERI_UART_USER, "mout_pll_peri_uart_user", mout_pll_peri= _uart_user_p, + PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 4, 1), +}; + +static const struct samsung_div_clock peri_div_clks[] __initconst =3D { + DIV(CLK_DOUT_CLK_PERI_I2C, "dout_clk_peri_i2c", "gout_clk_peri_i2c", + CLK_CON_DIV_DIV_CLK_PERI_I2C, 0, 8), + DIV(CLK_DOUT_CLK_PERI_SPI0, "dout_clk_peri_spi0", "gout_clk_peri_spi0", + CLK_CON_DIV_DIV_CLK_PERI_SPI0, 0, 8), + DIV(CLK_DOUT_CLK_PERI_SPI1, "dout_clk_peri_spi1", "gout_clk_peri_spi1", + CLK_CON_DIV_DIV_CLK_PERI_SPI1, 0, 8), + DIV(CLK_DOUT_CLK_PERI_SPI2, "dout_clk_peri_spi2", "gout_clk_peri_spi2", + CLK_CON_DIV_DIV_CLK_PERI_SPI2, 0, 8), + DIV(CLK_DOUT_CLK_PERI_USI_I2C, "dout_clk_peri_usi_i2c", "gout_clk_peri_us= i_i2c", + CLK_CON_DIV_DIV_CLK_PERI_USI_I2C, 0, 4), + DIV(CLK_DOUT_CLK_PERI_USI_USI, "dout_clk_peri_usi_usi", "gout_clk_peri_us= i_usi", + CLK_CON_DIV_DIV_CLK_PERI_USI_USI, 0, 8), +}; + +static const struct samsung_gate_clock peri_gate_clks[] __initconst =3D { + GATE(CLK_GOUT_CLK_PERI_I2C, "gout_clk_peri_i2c", "mout_pll_peri_ip_user", + CLK_CON_GAT_GATE_CLK_PERI_I2C, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CLK_PERI_SPI0, "gout_clk_peri_spi0", "mout_pll_peri_ip_user= ", + CLK_CON_GAT_GATE_CLK_PERI_SPI0, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CLK_PERI_SPI1, "gout_clk_peri_spi1", "mout_pll_peri_ip_user= ", + CLK_CON_GAT_GATE_CLK_PERI_SPI1, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CLK_PERI_SPI2, "gout_clk_peri_spi2", "mout_pll_peri_ip_user= ", + CLK_CON_GAT_GATE_CLK_PERI_SPI2, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CLK_PERI_USI_I2C, "gout_clk_peri_usi_i2c", "mout_pll_peri_i= p_user", + CLK_CON_GAT_GATE_CLK_PERI_USI_I2C, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CLK_PERI_USI_USI, "gout_clk_peri_usi_usi", "mout_pll_peri_i= p_user", + CLK_CON_GAT_GATE_CLK_PERI_USI_USI, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_AXI2AHB_MSD32_ACLK, "gout_peri_axi2ahb_msd32_aclk", + "mout_pll_peri_bus_user", CLK_CON_GAT_GOUT_PERI_AXI2AHB_MSD32_ACLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_BUSIF_TMU_PCLK, "gout_peri_busif_tmu_pclk", + "mout_pll_peri_bus_user", CLK_CON_GAT_GOUT_PERI_BUSIF_TMU_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_CAMI2C_0_IPCLK, "gout_peri_cami2c_0_ipclk", + "dout_clk_peri_i2c", CLK_CON_GAT_GOUT_PERI_CAMI2C_0_IPCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_CAMI2C_0_PCLK, "gout_peri_cami2c_0_pclk", + "mout_pll_peri_bus_user", CLK_CON_GAT_GOUT_PERI_CAMI2C_0_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_CAMI2C_1_IPCLK, "gout_peri_cami2c_1_ipclk", + "dout_clk_peri_i2c", CLK_CON_GAT_GOUT_PERI_CAMI2C_1_IPCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_CAMI2C_1_PCLK, "gout_peri_cami2c_1_pclk", + "mout_pll_peri_bus_user", CLK_CON_GAT_GOUT_PERI_CAMI2C_1_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_CAMI2C_2_IPCLK, "gout_peri_cami2c_2_ipclk", + "dout_clk_peri_i2c", CLK_CON_GAT_GOUT_PERI_CAMI2C_2_IPCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_CAMI2C_2_PCLK, "gout_peri_cami2c_2_pclk", + "mout_pll_peri_bus_user", CLK_CON_GAT_GOUT_PERI_CAMI2C_2_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_CAMI2C_3_IPCLK, "gout_peri_cami2c_3_ipclk", + "dout_clk_peri_i2c", CLK_CON_GAT_GOUT_PERI_CAMI2C_3_IPCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_CAMI2C_3_PCLK, "gout_peri_cami2c_3_pclk", + "mout_pll_peri_bus_user", CLK_CON_GAT_GOUT_PERI_CAMI2C_3_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_I2C_0_PCLK, "gout_peri_i2c_0_pclk", "mout_pll_peri_bus= _user", + CLK_CON_GAT_GOUT_PERI_I2C_0_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_I2C_1_PCLK, "gout_peri_i2c_1_pclk", "mout_pll_peri_bus= _user", + CLK_CON_GAT_GOUT_PERI_I2C_1_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_I2C_2_PCLK, "gout_peri_i2c_2_pclk", "mout_pll_peri_bus= _user", + CLK_CON_GAT_GOUT_PERI_I2C_2_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_I2C_3_PCLK, "gout_peri_i2c_3_pclk", "mout_pll_peri_bus= _user", + CLK_CON_GAT_GOUT_PERI_I2C_3_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_I2C_4_PCLK, "gout_peri_i2c_4_pclk", "mout_pll_peri_bus= _user", + CLK_CON_GAT_GOUT_PERI_I2C_4_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_I2C_5_PCLK, "gout_peri_i2c_5_pclk", "mout_pll_peri_bus= _user", + CLK_CON_GAT_GOUT_PERI_I2C_5_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_I2C_6_PCLK, "gout_peri_i2c_6_pclk", "mout_pll_peri_bus= _user", + CLK_CON_GAT_GOUT_PERI_I2C_6_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_GPIO_PCLK, "gout_peri_gpio_pclk", "mout_pll_peri_bus_u= ser", + CLK_CON_GAT_GOUT_PERI_GPIO_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_LHM_AXI_P_PERI_CLK, "gout_peri_lhm_axi_p_peri_clk", + "mout_pll_peri_bus_user", CLK_CON_GAT_GOUT_PERI_LHM_AXI_P_PERI_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_MCT_PCLK, "gout_peri_mct_pclk", "mout_pll_peri_bus_use= r", + CLK_CON_GAT_GOUT_PERI_MCT_PCLK, 21, 0, 0), + GATE(CLK_GOUT_PERI_OTP_CON_TOP_PCLK, "gout_peri_otp_con_top_pclk", + "mout_pll_peri_bus_user", CLK_CON_GAT_GOUT_PERI_OTP_CON_TOP_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_PWM_MOTOR_PCLK_S0, "gout_peri_pwm_motor_pclk_s0", + "mout_pll_peri_bus_user", CLK_CON_GAT_GOUT_PERI_PWM_MOTOR_PCLK_S0, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_BUS_CLK, "gout_peri_bus_clk", "mout_pll_peri_bus_user", + CLK_CON_GAT_GOUT_PERI_BUS_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_I2C_CLK, "gout_peri_i2c_clk", "dout_clk_peri_i2c", + CLK_CON_GAT_GOUT_PERI_I2C_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_SPI_0_CLK, "gout_peri_spi_0_clk", "dout_clk_peri_spi0", + CLK_CON_GAT_GOUT_PERI_SPI_0_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_SPI_1_CLK, "gout_peri_spi_1_clk", "dout_clk_peri_spi1", + CLK_CON_GAT_GOUT_PERI_SPI_1_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_SPI_2_CLK, "gout_peri_spi_2_clk", "dout_clk_peri_spi2", + CLK_CON_GAT_GOUT_PERI_SPI_2_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_UART_CLK, "gout_peri_uart_clk", "mout_pll_peri_uart_us= er", + CLK_CON_GAT_GOUT_PERI_UART_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_USI00_I2C_CLK, "gout_peri_usi00_i2c_clk", + "dout_clk_peri_usi_i2c", CLK_CON_GAT_GOUT_PERI_USI00_I2C_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_USI00_USI_CLK, "gout_peri_usi00_usi_clk", + "dout_clk_peri_usi_usi", CLK_CON_GAT_GOUT_PERI_USI00_USI_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_SPI_0_PCLK, "gout_peri_spi_0_pclk", "mout_pll_peri_bus= _user", + CLK_CON_GAT_GOUT_PERI_SPI_0_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_SPI_0_IPCLK, "gout_peri_spi_0_ipclk", "dout_cmu_peri_s= pi0", + CLK_CON_GAT_GOUT_PERI_SPI_0_IPCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_SPI_1_PCLK, "gout_peri_spi_1_pclk", "mout_pll_peri_bus= _user", + CLK_CON_GAT_GOUT_PERI_SPI_1_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_SPI_1_IPCLK, "gout_peri_spi_1_ipclk", "dout_cmu_peri_s= pi1", + CLK_CON_GAT_GOUT_PERI_SPI_1_IPCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_SPI_2_PCLK, "gout_peri_spi_2_pclk", "mout_pll_peri_bus= _user", + CLK_CON_GAT_GOUT_PERI_SPI_2_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_SPI_2_IPCLK, "gout_peri_spi_2_ipclk", "dout_cmu_peri_s= pi1", + CLK_CON_GAT_GOUT_PERI_SPI_2_IPCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_SYSREG_PCLK, "gout_peri_sysreg_pclk", "mout_pll_peri_b= us_user", + CLK_CON_GAT_GOUT_PERI_SYSREG_PCLK, 21, 0, 0), + GATE(CLK_GOUT_PERI_UART_IPCLK, "gout_peri_uart_ipclk", "mout_pll_peri_uar= t_user", + CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_UART_PCLK, "gout_peri_uart_pclk", "mout_pll_peri_bus_u= ser", + CLK_CON_GAT_GOUT_PERI_UART_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_USI00_I2C_IPCLK, "gout_peri_usi00_i2c_ipclk", + "dout_clk_peri_usi_i2c_user", CLK_CON_GAT_GOUT_PERI_USI00_I2C_IPCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_USI00_I2C_PCLK, "gout_peri_usi00_i2c_pclk", + "mout_pll_peri_bus_user", CLK_CON_GAT_GOUT_PERI_USI00_I2C_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_USI00_USI_IPCLK, "gout_peri_usi00_usi_ipclk", + "dout_clk_peri_usi_usi_user", CLK_CON_GAT_GOUT_PERI_USI00_USI_IPCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_USI00_USI_PCLK, "gout_peri_usi00_usi_pclk", + "mout_pll_peri_bus_user", CLK_CON_GAT_GOUT_PERI_USI00_USI_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_WDT_CLUSTER0_PCLK, "gout_peri_wdt_cluster0_pclk", + "mout_pll_peri_bus_user", CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER0_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_PERI_WDT_CLUSTER1_PCLK, "gout_peri_wdt_cluster1_pclk", + "mout_pll_peri_bus_user", CLK_CON_GAT_GOUT_PERI_WDT_CLUSTER1_PCLK, + 21, CLK_IGNORE_UNUSED, 0), +}; + +static const struct samsung_cmu_info peri_cmu_info __initconst =3D { + .mux_clks =3D peri_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(peri_mux_clks), + .div_clks =3D peri_div_clks, + .nr_div_clks =3D ARRAY_SIZE(peri_div_clks), + .gate_clks =3D peri_gate_clks, + .nr_gate_clks =3D ARRAY_SIZE(peri_gate_clks), + .clk_regs =3D peri_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(peri_clk_regs), + .nr_clk_ids =3D CLKS_NR_PERI, +}; + +static void __init exynos9610_cmu_peri_init(struct device_node *np) +{ + exynos_arm64_register_cmu(NULL, np, &peri_cmu_info); +} + +CLK_OF_DECLARE(exynos9610_cmu_peri, "samsung,exynos9610-cmu-peri", + exynos9610_cmu_peri_init); + +/* CMU_APM */ +#define PLL_CON0_MUX_CLKCMU_APM_BUS_USER 0x0100 +#define PLL_CON2_MUX_CLKCMU_APM_BUS_USER 0x0108 +#define PLL_CON0_MUX_DLL_USER 0x0120 +#define PLL_CON2_MUX_DLL_USER 0x0128 +#define CLK_CON_MUX_CLKCMU_SHUB_BUS 0x1000 +#define CLK_CON_MUX_CLK_APM_BUS 0x1004 +#define CLK_CON_DIV_CLKCMU_SHUB_BUS 0x1800 +#define CLK_CON_DIV_CLK_APM_BUS 0x1804 +#define CLK_CON_GAT_CLKCMU_CMGP_BUS 0x2000 +#define CLK_CON_GAT_CLK_APM_CMU_PCLK 0x2004 +#define CLK_CON_GAT_CLK_APM_OSCCLK_CLK 0x2008 +#define CLK_CON_GAT_CLK_APM_OSCCLK_RCO_CLK 0x200c +#define CLK_CON_GAT_GATE_CLKCMU_SHUB_BUS 0x2010 +#define CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 0x2014 +#define CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK 0x2018 +#define CLK_CON_GAT_GOUT_APM_APBIF_RTC_ALIVE_PCLK 0x201c +#define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_ALIVE_PCLK 0x2020 +#define CLK_CON_GAT_GOUT_APM_GREBEINTEGRATION_HCLK 0x2024 +#define CLK_CON_GAT_GOUT_APM_INTMEM_ACLK 0x2028 +#define CLK_CON_GAT_GOUT_APM_INTMEM_PCLK 0x202c +#define CLK_CON_GAT_GOUT_APM_LHM_AXI_P_GNSS_CLK 0x2030 +#define CLK_CON_GAT_GOUT_APM_LHM_AXI_P_CLK 0x2034 +#define CLK_CON_GAT_GOUT_APM_LHM_AXI_P_MODEM_CLK 0x2038 +#define CLK_CON_GAT_GOUT_APM_LHM_AXI_P_SHUB_CLK 0x203c +#define CLK_CON_GAT_GOUT_APM_LHM_AXI_P_WLBT_CLK 0x2040 +#define CLK_CON_GAT_GOUT_APM_LHS_AXI_D_CLK 0x2044 +#define CLK_CON_GAT_GOUT_APM_LHS_AXI_LP_SHUB_CLK 0x2048 +#define CLK_CON_GAT_GOUT_APM_MAILBOX_AP2CP_PCLK 0x204c +#define CLK_CON_GAT_GOUT_APM_MAILBOX_AP2CP_S_PCLK 0x2050 +#define CLK_CON_GAT_GOUT_APM_MAILBOX_AP2GNSS_PCLK 0x2054 +#define CLK_CON_GAT_GOUT_APM_MAILBOX_AP2SHUB_PCLK 0x2058 +#define CLK_CON_GAT_GOUT_APM_MAILBOX_AP2WLBT_PCLK 0x205c +#define CLK_CON_GAT_GOUT_APM_MAILBOX_APM2AP_PCLK 0x2060 +#define CLK_CON_GAT_GOUT_APM_MAILBOX_APM2CP_PCLK 0x2064 +#define CLK_CON_GAT_GOUT_APM_MAILBOX_APM2GNSS_PCLK 0x2068 +#define CLK_CON_GAT_GOUT_APM_MAILBOX_APM2SHUB_PCLK 0x206c +#define CLK_CON_GAT_GOUT_APM_MAILBOX_APM2WLBT_PCLK 0x2070 +#define CLK_CON_GAT_GOUT_APM_MAILBOX_CP2GNSS_PCLK 0x2074 +#define CLK_CON_GAT_GOUT_APM_MAILBOX_CP2SHUB_PCLK 0x2078 +#define CLK_CON_GAT_GOUT_APM_MAILBOX_CP2WLBT_PCLK 0x207c +#define CLK_CON_GAT_GOUT_APM_MAILBOX_SHUB2GNSS_PCLK 0x2080 +#define CLK_CON_GAT_GOUT_APM_MAILBOX_SHUB2WLBT_PCLK 0x2084 +#define CLK_CON_GAT_GOUT_APM_MAILBOX_WLBT2ABOX_PCLK 0x2088 +#define CLK_CON_GAT_GOUT_APM_MAILBOX_WLBT2GNSS_PCLK 0x208c +#define CLK_CON_GAT_GOUT_APM_PEM_CLK 0x2090 +#define CLK_CON_GAT_GOUT_APM_PGEN_LITE_CLK 0x2094 +#define CLK_CON_GAT_GOUT_APM_PMU_INTR_GEN_PCLK 0x2098 +#define CLK_CON_GAT_GOUT_APM_BUS_CLK 0x209c +#define CLK_CON_GAT_GOUT_APM_GREBE_CLK 0x20a0 +#define CLK_CON_GAT_GOUT_APM_SPEEDY_PCLK 0x20a4 +#define CLK_CON_GAT_GOUT_APM_SYSREG_PCLK 0x20a8 +#define CLK_CON_GAT_GOUT_APM_WDT_PCLK 0x20ac +#define CLK_CON_GAT_GOUT_APM_XIU_DP_ACLK 0x20b0 + +static const unsigned long apm_clk_regs[] __initconst =3D { + PLL_CON0_MUX_CLKCMU_APM_BUS_USER, + PLL_CON2_MUX_CLKCMU_APM_BUS_USER, + PLL_CON0_MUX_DLL_USER, + PLL_CON2_MUX_DLL_USER, + CLK_CON_MUX_CLKCMU_SHUB_BUS, + CLK_CON_MUX_CLK_APM_BUS, + CLK_CON_DIV_CLKCMU_SHUB_BUS, + CLK_CON_DIV_CLK_APM_BUS, + CLK_CON_GAT_CLKCMU_CMGP_BUS, + CLK_CON_GAT_CLK_APM_CMU_PCLK, + CLK_CON_GAT_CLK_APM_OSCCLK_CLK, + CLK_CON_GAT_CLK_APM_OSCCLK_RCO_CLK, + CLK_CON_GAT_GATE_CLKCMU_SHUB_BUS, + CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, + CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, + CLK_CON_GAT_GOUT_APM_APBIF_RTC_ALIVE_PCLK, + CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_ALIVE_PCLK, + CLK_CON_GAT_GOUT_APM_GREBEINTEGRATION_HCLK, + CLK_CON_GAT_GOUT_APM_INTMEM_ACLK, + CLK_CON_GAT_GOUT_APM_INTMEM_PCLK, + CLK_CON_GAT_GOUT_APM_LHM_AXI_P_GNSS_CLK, + CLK_CON_GAT_GOUT_APM_LHM_AXI_P_CLK, + CLK_CON_GAT_GOUT_APM_LHM_AXI_P_MODEM_CLK, + CLK_CON_GAT_GOUT_APM_LHM_AXI_P_SHUB_CLK, + CLK_CON_GAT_GOUT_APM_LHM_AXI_P_WLBT_CLK, + CLK_CON_GAT_GOUT_APM_LHS_AXI_D_CLK, + CLK_CON_GAT_GOUT_APM_LHS_AXI_LP_SHUB_CLK, + CLK_CON_GAT_GOUT_APM_MAILBOX_AP2CP_PCLK, + CLK_CON_GAT_GOUT_APM_MAILBOX_AP2CP_S_PCLK, + CLK_CON_GAT_GOUT_APM_MAILBOX_AP2GNSS_PCLK, + CLK_CON_GAT_GOUT_APM_MAILBOX_AP2SHUB_PCLK, + CLK_CON_GAT_GOUT_APM_MAILBOX_AP2WLBT_PCLK, + CLK_CON_GAT_GOUT_APM_MAILBOX_APM2AP_PCLK, + CLK_CON_GAT_GOUT_APM_MAILBOX_APM2CP_PCLK, + CLK_CON_GAT_GOUT_APM_MAILBOX_APM2GNSS_PCLK, + CLK_CON_GAT_GOUT_APM_MAILBOX_APM2SHUB_PCLK, + CLK_CON_GAT_GOUT_APM_MAILBOX_APM2WLBT_PCLK, + CLK_CON_GAT_GOUT_APM_MAILBOX_CP2GNSS_PCLK, + CLK_CON_GAT_GOUT_APM_MAILBOX_CP2SHUB_PCLK, + CLK_CON_GAT_GOUT_APM_MAILBOX_CP2WLBT_PCLK, + CLK_CON_GAT_GOUT_APM_MAILBOX_SHUB2GNSS_PCLK, + CLK_CON_GAT_GOUT_APM_MAILBOX_SHUB2WLBT_PCLK, + CLK_CON_GAT_GOUT_APM_MAILBOX_WLBT2ABOX_PCLK, + CLK_CON_GAT_GOUT_APM_MAILBOX_WLBT2GNSS_PCLK, + CLK_CON_GAT_GOUT_APM_PEM_CLK, + CLK_CON_GAT_GOUT_APM_PGEN_LITE_CLK, + CLK_CON_GAT_GOUT_APM_PMU_INTR_GEN_PCLK, + CLK_CON_GAT_GOUT_APM_BUS_CLK, + CLK_CON_GAT_GOUT_APM_GREBE_CLK, + CLK_CON_GAT_GOUT_APM_SPEEDY_PCLK, + CLK_CON_GAT_GOUT_APM_SYSREG_PCLK, + CLK_CON_GAT_GOUT_APM_WDT_PCLK, + CLK_CON_GAT_GOUT_APM_XIU_DP_ACLK, +}; + +PNAME(mout_pll_apm_bus_user_p) =3D { "oscclk", "dout_cmu_apm_bus" }; +PNAME(mout_pll_dll_user_p) =3D { "oscclk", "dll_dco" }; +PNAME(mout_cmu_shub_bus_p) =3D { "oscclk", "mout_pll_dll_user" }; +PNAME(mout_clk_apm_bus_p) =3D { "mout_pll_apm_bus_user", + "dll_dco" }; + +static const struct samsung_mux_clock apm_mux_clks[] __initconst =3D { + MUX(CLK_MOUT_PLL_APM_BUS_USER, "mout_pll_apm_bus_user", mout_pll_apm_bus_= user_p, + PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 4, 1), + MUX(CLK_MOUT_PLL_DLL_USER, "mout_pll_dll_user", mout_pll_dll_user_p, + PLL_CON0_MUX_DLL_USER, 4, 1), + MUX(CLK_MOUT_CMU_SHUB_BUS, "mout_cmu_shub_bus", mout_cmu_shub_bus_p, + CLK_CON_MUX_CLKCMU_SHUB_BUS, 0, 1), + MUX(CLK_MOUT_CLK_APM_BUS, "mout_clk_apm_bus", mout_clk_apm_bus_p, + CLK_CON_MUX_CLK_APM_BUS, 0, 1), +}; + +static const struct samsung_div_clock apm_div_clks[] __initconst =3D { + DIV(CLK_DOUT_CMU_SHUB_BUS, "dout_cmu_shub_bus", "gout_cmu_shub_bus", + CLK_CON_DIV_CLKCMU_SHUB_BUS, 0, 3), + DIV(CLK_DOUT_CLK_APM_BUS, "dout_clk_apm_bus", "mout_clk_apm_bus", + CLK_CON_DIV_CLK_APM_BUS, 0, 3), +}; + +static const struct samsung_gate_clock apm_gate_clks[] __initconst =3D { + GATE(CLK_GOUT_CMU_CMGP_BUS, "gout_cmu_cmgp_bus", "dout_clk_apm_bus", + CLK_CON_GAT_CLKCMU_CMGP_BUS, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CLK_APM_CMU_PCLK, "gout_clk_apm_cmu_pclk", "dout_clk_apm_bu= s", + CLK_CON_GAT_CLK_APM_CMU_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CLK_APM_OSCCLK_CLK, "gat_clk_apm_oscclk_clk", "oscclk", + CLK_CON_GAT_CLK_APM_OSCCLK_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CLK_APM_OSCCLK_RCO_CLK, "gat_clk_apm_oscclk_rco_clk", "oscc= lk", + CLK_CON_GAT_CLK_APM_OSCCLK_RCO_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, "gout_apm_apbif_gpio_alive_pclk", + "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_APBIF_PMU_ALIVE_PCLK, "gout_apm_apbif_pmu_alive_pclk", + "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_APBIF_RTC_ALIVE_PCLK, "gout_apm_apbif_rtc_alive_pclk", + "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_APBIF_RTC_ALIVE_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_APBIF_TOP_RTC_ALIVE_PCLK, "gout_apm_apbif_top_rtc_alive= _pclk", + "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_ALIVE_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_GREBEINTEGRATION_HCLK, "gout_apm_grebeintegration_hclk", + "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_GREBEINTEGRATION_HCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_INTMEM_ACLK, "gout_apm_intmem_aclk", "dout_clk_apm_bus", + CLK_CON_GAT_GOUT_APM_INTMEM_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_INTMEM_PCLK, "gout_apm_intmem_pclk", "dout_clk_apm_bus", + CLK_CON_GAT_GOUT_APM_INTMEM_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_LHM_AXI_P_GNSS_CLK, "gout_apm_lhm_axi_p_gnss_clk", + "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_LHM_AXI_P_GNSS_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_LHM_AXI_P_CLK, "gout_apm_lhm_axi_p_clk", + "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_LHM_AXI_P_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_LHM_AXI_P_MODEM_CLK, "gout_apm_lhm_axi_p_modem_clk", + "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_LHM_AXI_P_MODEM_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_LHM_AXI_P_SHUB_CLK, "gout_apm_lhm_axi_p_shub_clk", + "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_LHM_AXI_P_SHUB_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_LHM_AXI_P_WLBT_CLK, "gout_apm_lhm_axi_p_wlbt_clk", + "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_LHM_AXI_P_WLBT_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_LHS_AXI_D_CLK, "gout_apm_lhs_axi_d_clk", + "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_LHS_AXI_D_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_LHS_AXI_LP_SHUB_CLK, "gout_apm_lhs_axi_lp_shub_clk", + "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_LHS_AXI_LP_SHUB_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_MAILBOX_AP2CP_PCLK, "gout_apm_mailbox_ap2cp_pclk", + "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_AP2CP_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_MAILBOX_AP2CP_S_PCLK, "gout_apm_mailbox_ap2cp_s_pclk", + "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_AP2CP_S_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_MAILBOX_AP2GNSS_PCLK, "gout_apm_mailbox_ap2gnss_pclk", + "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_AP2GNSS_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_MAILBOX_AP2SHUB_PCLK, "gout_apm_mailbox_ap2shub_pclk", + "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_AP2SHUB_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_MAILBOX_AP2WLBT_PCLK, "gout_apm_mailbox_ap2wlbt_pclk", + "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_AP2WLBT_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_MAILBOX_APM2AP_PCLK, "gout_apm_mailbox_apm2ap_pclk", + "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_APM2AP_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_MAILBOX_APM2CP_PCLK, "gout_apm_mailbox_apm2cp_pclk", + "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_APM2CP_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_MAILBOX_APM2GNSS_PCLK, "gout_apm_mailbox_apm2gnss_pclk", + "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_APM2GNSS_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_MAILBOX_APM2SHUB_PCLK, "gout_apm_mailbox_apm2shub_pclk", + "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_APM2SHUB_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_MAILBOX_APM2WLBT_PCLK, "gout_apm_mailbox_apm2wlbt_pclk", + "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_APM2WLBT_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_MAILBOX_CP2GNSS_PCLK, "gout_apm_mailbox_cp2gnss_pclk", + "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_CP2GNSS_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_MAILBOX_CP2SHUB_PCLK, "gout_apm_mailbox_cp2shub_pclk", + "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_CP2SHUB_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_MAILBOX_CP2WLBT_PCLK, "gout_apm_mailbox_cp2wlbt_pclk", + "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_CP2WLBT_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_MAILBOX_SHUB2GNSS_PCLK, "gout_apm_mailbox_shub2gnss_pcl= k", + "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_SHUB2GNSS_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_MAILBOX_SHUB2WLBT_PCLK, "gout_apm_mailbox_shub2wlbt_pcl= k", + "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_SHUB2WLBT_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_MAILBOX_WLBT2ABOX_PCLK, "gout_apm_mailbox_wlbt2abox_pcl= k", + "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_WLBT2ABOX_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_MAILBOX_WLBT2GNSS_PCLK, "gout_apm_mailbox_wlbt2gnss_pcl= k", + "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_MAILBOX_WLBT2GNSS_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_PEM_CLK, "gout_apm_pem_clk", "dout_clk_apm_bus", + CLK_CON_GAT_GOUT_APM_PEM_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_PGEN_LITE_CLK, "gout_apm_pgen_lite_clk", "dout_clk_apm_= bus", + CLK_CON_GAT_GOUT_APM_PGEN_LITE_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_PMU_INTR_GEN_PCLK, "gout_apm_pmu_intr_gen_pclk", + "dout_clk_apm_bus", CLK_CON_GAT_GOUT_APM_PMU_INTR_GEN_PCLK, 21, CLK_= IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_BUS_CLK, "gout_apm_bus_clk", "dout_clk_apm_bus", + CLK_CON_GAT_GOUT_APM_BUS_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_GREBE_CLK, "gout_apm_grebe_clk", "dout_clk_apm_bus", + CLK_CON_GAT_GOUT_APM_GREBE_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_SPEEDY_PCLK, "gout_apm_speedy_pclk", "dout_clk_apm_bus", + CLK_CON_GAT_GOUT_APM_SPEEDY_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_SYSREG_PCLK, "gout_apm_sysreg_pclk", "dout_clk_apm_bus", + CLK_CON_GAT_GOUT_APM_SYSREG_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_WDT_PCLK, "gout_apm_wdt_pclk", "dout_clk_apm_bus", + CLK_CON_GAT_GOUT_APM_WDT_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_APM_XIU_DP_ACLK, "gout_apm_xiu_dp_aclk", "dout_clk_apm_bus", + CLK_CON_GAT_GOUT_APM_XIU_DP_ACLK, 21, CLK_IGNORE_UNUSED, 0), +}; + +static const struct samsung_cmu_info apm_cmu_info __initconst =3D { + .mux_clks =3D apm_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(apm_mux_clks), + .div_clks =3D apm_div_clks, + .nr_div_clks =3D ARRAY_SIZE(apm_div_clks), + .gate_clks =3D apm_gate_clks, + .nr_gate_clks =3D ARRAY_SIZE(apm_gate_clks), + .clk_regs =3D apm_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(apm_clk_regs), + .nr_clk_ids =3D CLKS_NR_APM, +}; + +static void __init exynos9610_cmu_apm_init(struct device_node *np) +{ + exynos_arm64_register_cmu(NULL, np, &apm_cmu_info); +} + +// Register APM early, as it's a dependency of CMU_CMGP +CLK_OF_DECLARE(exynos9610_cmu_apm, "samsung,exynos9610-cmu-apm", + exynos9610_cmu_apm_init); + +/* CMU_CAM */ +#define PLL_CON0_MUX_CLKCMU_CAM_BUS_USER 0x0100 +#define PLL_CON2_MUX_CLKCMU_CAM_BUS_USER 0x0108 +#define CLK_CON_DIV_DIV_CLK_CAM_BUSP 0x1800 +#define CLK_CON_GAT_CLK_CAM_CMU_PCLK 0x2000 +#define CLK_CON_GAT_CLK_CAM_OSCCLK_CLK 0x2004 +#define CLK_CON_GAT_GOUT_CAM_BUSD 0x2008 +#define CLK_CON_GAT_GOUT_CAM_BTM_ACLK 0x200c +#define CLK_CON_GAT_GOUT_CAM_BTM_PCLK 0x2010 +#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_3AA 0x2014 +#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_CSIS0 0x2018 +#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_CSIS1 0x201c +#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_CSIS2 0x2020 +#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_CSIS3 0x2024 +#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_DMA 0x2028 +#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS0 0x202c +#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS1 0x2030 +#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS2 0x2034 +#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS3 0x2038 +#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_PAFSTAT_CORE 0x203c +#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_PPMU_CAM 0x2040 +#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_RDMA 0x2044 +// #define CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_SMMU_CAM 0x2048 +#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_XIU_D_CAM 0x204c +#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_PCLK_PGEN_LITE_CAM0 0x2050 +#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_PCLK_PGEN_LITE_CAM1 0x2054 +#define CLK_CON_GAT_GOUT_CAM_IS6P10P0_PCLK_PPMU_CAM 0x2058 +#define CLK_CON_GAT_GOUT_CAM_LHM_AXI_P_CLK 0x205c +#define CLK_CON_GAT_GOUT_CAM_LHS_ACEL_D_CLK 0x2060 +#define CLK_CON_GAT_GOUT_CAM_LHS_ATB_CAMISP_CLK 0x2064 +#define CLK_CON_GAT_GOUT_CAM_BUSD_CLK 0x2068 +#define CLK_CON_GAT_GOUT_CAM_BUSP_CLK 0x206c +#define CLK_CON_GAT_GOUT_CAM_SYSREG_PCLK 0x2070 + +static const unsigned long cam_clk_regs[] __initconst =3D { + PLL_CON0_MUX_CLKCMU_CAM_BUS_USER, + PLL_CON2_MUX_CLKCMU_CAM_BUS_USER, + CLK_CON_DIV_DIV_CLK_CAM_BUSP, + CLK_CON_GAT_CLK_CAM_CMU_PCLK, + CLK_CON_GAT_CLK_CAM_OSCCLK_CLK, + CLK_CON_GAT_GOUT_CAM_BUSD, + CLK_CON_GAT_GOUT_CAM_BTM_ACLK, + CLK_CON_GAT_GOUT_CAM_BTM_PCLK, + CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_3AA, + CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_CSIS0, + CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_CSIS1, + CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_CSIS2, + CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_CSIS3, + CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_DMA, + CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS0, + CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS1, + CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS2, + CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS3, + CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_PAFSTAT_CORE, + CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_PPMU_CAM, + CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_RDMA, + // CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_SMMU_CAM, + CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_XIU_D_CAM, + CLK_CON_GAT_GOUT_CAM_IS6P10P0_PCLK_PGEN_LITE_CAM0, + CLK_CON_GAT_GOUT_CAM_IS6P10P0_PCLK_PPMU_CAM, + CLK_CON_GAT_GOUT_CAM_LHM_AXI_P_CLK, + CLK_CON_GAT_GOUT_CAM_LHS_ATB_CAMISP_CLK, + CLK_CON_GAT_GOUT_CAM_BUSD_CLK, + CLK_CON_GAT_GOUT_CAM_BUSP_CLK, + CLK_CON_GAT_GOUT_CAM_SYSREG_PCLK, +}; + +PNAME(mout_pll_cam_bus_user_p) =3D { "oscclk", "dout_cmu_cam_bus" }; + +static const struct samsung_mux_clock cam_mux_clks[] __initconst =3D { + MUX(CLK_MOUT_PLL_CAM_BUS_USER, "mout_pll_cam_bus_user", mout_pll_cam_bus_= user_p, + PLL_CON0_MUX_CLKCMU_CAM_BUS_USER, 4, 1), +}; + +static const struct samsung_div_clock cam_div_clks[] __initconst =3D { + DIV(CLK_DIV_CLK_CAM_BUSP, "dout_clk_cam_busp", "mout_pll_cam_bus_user", + CLK_CON_DIV_DIV_CLK_CAM_BUSP, 0, 2), +}; + +static const struct samsung_gate_clock cam_gate_clks[] __initconst =3D { + GATE(CLK_GAT_CLK_CAM_CMU_PCLK, "gat_clk_cam_cmu_pclk", "dout_clk_cam_busp= ", + CLK_CON_GAT_CLK_CAM_CMU_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GAT_CLK_CAM_OSCCLK_CLK, "gat_clk_cam_oscclk_clk", "oscclk", + CLK_CON_GAT_CLK_CAM_OSCCLK_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CAM_BUSD, "gout_cam_busd", "mout_pll_cam_bus_user", + CLK_CON_GAT_GOUT_CAM_BUSD, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CAM_BTM_ACLK, "gout_cam_btm_aclk", "mout_pll_cam_bus_user", + CLK_CON_GAT_GOUT_CAM_BTM_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CAM_BTM_PCLK, "gout_cam_btm_pclk", "dout_clk_cam_busp", + CLK_CON_GAT_GOUT_CAM_BTM_PCLK, 21, CLK_IGNORE_UNUSED, 0), + + GATE(CLK_GOUT_CAM_LHS_ATB_CAMISP_CLK, "gout_cam_lhs_atb_camisp_clk", + "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_LHS_ATB_CAMISP_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CAM_IS6P10P0_ACLK_3AA, "gout_cam_is6p10p0_aclk_3aa", + "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_3AA, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CAM_IS6P10P0_ACLK_CSIS0, "gout_cam_is6p10p0_aclk_csis0", + "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_CSIS0, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CAM_IS6P10P0_ACLK_CSIS1, "gout_cam_is6p10p0_aclk_csis1", + "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_CSIS1, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CAM_IS6P10P0_ACLK_CSIS2, "gout_cam_is6p10p0_aclk_csis2", + "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_CSIS2, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CAM_IS6P10P0_ACLK_CSIS3, "gout_cam_is6p10p0_aclk_csis3", + "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_CSIS3, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CAM_IS6P10P0_ACLK_RDMA, "gout_cam_is6p10p0_aclk_rdma", + "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_RDMA, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS0, "gout_cam_is6p10p0_aclk_glue_= csis0", + "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSI= S0, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS1, "gout_cam_is6p10p0_aclk_glue_= csis1", + "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSI= S1, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS2, "gout_cam_is6p10p0_aclk_glue_= csis2", + "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSI= S2, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSIS3, "gout_cam_is6p10p0_aclk_glue_= csis3", + "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_GLUE_CSI= S3, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CAM_IS6P10P0_ACLK_PAFSTAT_CORE, "gout_cam_is6p10p0_aclk_paf= stat_core", + "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_PAFSTAT_= CORE, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CAM_IS6P10P0_ACLK_PPMU_CAM, "gout_cam_is6p10p0_aclk_ppmu_ca= m", + "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_PPMU_CAM, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CAM_IS6P10P0_ACLK_DMA, "gout_cam_is6p10p0_aclk_dma", + "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_DMA, + 21, CLK_IGNORE_UNUSED, 0), + // GATE(CLK_GOUT_CAM_IS6P10P0_ACLK_SMMU_CAM, "gout_cam_is6p10p0_aclk_smmu= _cam", + // "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_SMMU_= CAM, + // 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CAM_IS6P10P0_ACLK_XIU_D_CAM, "gout_cam_is6p10p0_aclk_xiu_d_= cam", + "mout_pll_cam_bus_user", CLK_CON_GAT_GOUT_CAM_IS6P10P0_ACLK_XIU_D_CA= M, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CAM_IS6P10P0_PCLK_PGEN_LITE_CAM0, "gout_cam_is6p10p0_pclk_p= gen_lite_cam0", + "dout_clk_cam_busp", CLK_CON_GAT_GOUT_CAM_IS6P10P0_PCLK_PGEN_LITE_CA= M0, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CAM_IS6P10P0_PCLK_PGEN_LITE_CAM1, "gout_cam_is6p10p0_pclk_p= gen_lite_cam1", + "dout_clk_cam_busp", CLK_CON_GAT_GOUT_CAM_IS6P10P0_PCLK_PGEN_LITE_CA= M1, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CAM_IS6P10P0_PCLK_PPMU_CAM, "gout_cam_is6p10p0_pclk_ppmu_ca= m", + "dout_clk_cam_busp", CLK_CON_GAT_GOUT_CAM_IS6P10P0_PCLK_PPMU_CAM, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CAM_LHM_AXI_P_CLK, "gout_cam_lhm_axi_p_clk", "dout_clk_cam_= busp", + CLK_CON_GAT_GOUT_CAM_LHM_AXI_P_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CAM_LHS_ACEL_D_CLK, "gout_cam_lhs_acel_d_clk", "mout_pll_ca= m_bus_user", + CLK_CON_GAT_GOUT_CAM_LHS_ACEL_D_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CAM_BUSD_CLK, "gout_cam_busd_clk", "mout_pll_cam_bus_user", + CLK_CON_GAT_GOUT_CAM_BUSD_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CAM_BUSP_CLK, "gout_cam_busp_clk", "dout_clk_cam_busp", + CLK_CON_GAT_GOUT_CAM_BUSP_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CAM_SYSREG_PCLK, "gout_cam_sysreg_pclk", "dout_clk_cam_busp= ", + CLK_CON_GAT_GOUT_CAM_SYSREG_PCLK, 21, 0, 0), +}; + +static const struct samsung_cmu_info cam_cmu_info __initconst =3D { + .mux_clks =3D cam_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(cam_mux_clks), + .div_clks =3D cam_div_clks, + .nr_div_clks =3D ARRAY_SIZE(cam_div_clks), + .gate_clks =3D cam_gate_clks, + .nr_gate_clks =3D ARRAY_SIZE(cam_gate_clks), + .clk_regs =3D cam_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(cam_clk_regs), + .nr_clk_ids =3D CLKS_NR_CAM, +}; + +/* CMU_CMGP */ +#define CLK_CON_MUX_MUX_CLK_CMGP_ADC 0x1000 +#define CLK_CON_MUX_MUX_CLK_CMGP_I2C 0x1004 +#define CLK_CON_MUX_MUX_CLK_CMGP_USI00 0x1008 +#define CLK_CON_MUX_MUX_CLK_CMGP_USI01 0x100c +#define CLK_CON_MUX_MUX_CLK_CMGP_USI02 0x1010 +#define CLK_CON_MUX_MUX_CLK_CMGP_USI03 0x1014 +#define CLK_CON_MUX_MUX_CLK_CMGP_USI04 0x1018 +#define CLK_CON_DIV_DIV_CLK_CMGP_ADC 0x1800 +#define CLK_CON_DIV_DIV_CLK_CMGP_I2C 0x1804 +#define CLK_CON_DIV_DIV_CLK_CMGP_USI00 0x1808 +#define CLK_CON_DIV_DIV_CLK_CMGP_USI01 0x180c +#define CLK_CON_DIV_DIV_CLK_CMGP_USI02 0x1810 +#define CLK_CON_DIV_DIV_CLK_CMGP_USI03 0x1814 +#define CLK_CON_DIV_DIV_CLK_CMGP_USI04 0x1818 +#define CLK_CON_GAT_CMGP_CMU_PCLK 0x2004 +#define CLK_CON_GAT_CLK_CMGP_OSCCLK_RCO_CLK 0x2008 +#define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0 0x200c +#define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1 0x2010 +#define CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK 0x2014 +#define CLK_CON_GAT_GOUT_CMGP_I2C_CMGP00_IPCLK 0x2018 +#define CLK_CON_GAT_GOUT_CMGP_I2C_CMGP00_PCLK 0x201c +#define CLK_CON_GAT_GOUT_CMGP_I2C_CMGP01_IPCLK 0x2020 +#define CLK_CON_GAT_GOUT_CMGP_I2C_CMGP01_PCLK 0x2024 +#define CLK_CON_GAT_GOUT_CMGP_I2C_CMGP02_IPCLK 0x2028 +#define CLK_CON_GAT_GOUT_CMGP_I2C_CMGP02_PCLK 0x202c +#define CLK_CON_GAT_GOUT_CMGP_I2C_CMGP03_IPCLK 0x2030 +#define CLK_CON_GAT_GOUT_CMGP_I2C_CMGP03_PCLK 0x2034 +#define CLK_CON_GAT_GOUT_CMGP_I2C_CMGP04_IPCLK 0x2038 +#define CLK_CON_GAT_GOUT_CMGP_I2C_CMGP04_PCLK 0x203c +#define CLK_CON_GAT_GOUT_CMGP_BUS_CLK 0x2040 +#define CLK_CON_GAT_GOUT_CMGP_I2C_CLK 0x2044 +#define CLK_CON_GAT_GOUT_CMGP_USI00_CLK 0x2048 +#define CLK_CON_GAT_GOUT_CMGP_USI01_CLK 0x204c +#define CLK_CON_GAT_GOUT_CMGP_USI02_CLK 0x2050 +#define CLK_CON_GAT_GOUT_CMGP_USI03_CLK 0x2054 +#define CLK_CON_GAT_GOUT_CMGP_USI04_CLK 0x2058 +#define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2CP_PCLK 0x205c +#define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2GNSS_PCLK 0x2060 +#define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2PMU_AP_PCLK 0x2064 +#define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2PMU_SHUB_PCLK 0x2068 +#define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2SHUB_PCLK 0x206c +#define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2WLBT_PCLK 0x2070 +#define CLK_CON_GAT_GOUT_CMGP_SYSREG_PCLK 0x2074 +#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP00_IPCLK 0x2078 +#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP00_PCLK 0x207c +#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP01_IPCLK 0x2080 +#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP01_PCLK 0x2084 +#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP02_IPCLK 0x2088 +#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP02_PCLK 0x208c +#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP03_IPCLK 0x2090 +#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP03_PCLK 0x2094 +#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP04_IPCLK 0x2098 +#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP04_PCLK 0x209c + +static const unsigned long cmgp_clk_regs[] __initconst =3D { + CLK_CON_MUX_MUX_CLK_CMGP_ADC, + CLK_CON_MUX_MUX_CLK_CMGP_I2C, + CLK_CON_MUX_MUX_CLK_CMGP_USI00, + CLK_CON_MUX_MUX_CLK_CMGP_USI01, + CLK_CON_MUX_MUX_CLK_CMGP_USI02, + CLK_CON_MUX_MUX_CLK_CMGP_USI03, + CLK_CON_MUX_MUX_CLK_CMGP_USI04, + CLK_CON_DIV_DIV_CLK_CMGP_ADC, + CLK_CON_DIV_DIV_CLK_CMGP_I2C, + CLK_CON_DIV_DIV_CLK_CMGP_USI00, + CLK_CON_DIV_DIV_CLK_CMGP_USI01, + CLK_CON_DIV_DIV_CLK_CMGP_USI02, + CLK_CON_DIV_DIV_CLK_CMGP_USI03, + CLK_CON_DIV_DIV_CLK_CMGP_USI04, + CLK_CON_GAT_CMGP_CMU_PCLK, + CLK_CON_GAT_CLK_CMGP_OSCCLK_RCO_CLK, + CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, + CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, + CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, + CLK_CON_GAT_GOUT_CMGP_I2C_CMGP00_IPCLK, + CLK_CON_GAT_GOUT_CMGP_I2C_CMGP00_PCLK, + CLK_CON_GAT_GOUT_CMGP_I2C_CMGP01_IPCLK, + CLK_CON_GAT_GOUT_CMGP_I2C_CMGP01_PCLK, + CLK_CON_GAT_GOUT_CMGP_I2C_CMGP02_IPCLK, + CLK_CON_GAT_GOUT_CMGP_I2C_CMGP02_PCLK, + CLK_CON_GAT_GOUT_CMGP_I2C_CMGP03_IPCLK, + CLK_CON_GAT_GOUT_CMGP_I2C_CMGP03_PCLK, + CLK_CON_GAT_GOUT_CMGP_I2C_CMGP04_IPCLK, + CLK_CON_GAT_GOUT_CMGP_I2C_CMGP04_PCLK, + CLK_CON_GAT_GOUT_CMGP_BUS_CLK, + CLK_CON_GAT_GOUT_CMGP_I2C_CLK, + CLK_CON_GAT_GOUT_CMGP_USI00_CLK, + CLK_CON_GAT_GOUT_CMGP_USI01_CLK, + CLK_CON_GAT_GOUT_CMGP_USI02_CLK, + CLK_CON_GAT_GOUT_CMGP_USI03_CLK, + CLK_CON_GAT_GOUT_CMGP_USI04_CLK, + CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2CP_PCLK, + CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2GNSS_PCLK, + CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2PMU_AP_PCLK, + CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2PMU_SHUB_PCLK, + CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2SHUB_PCLK, + CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2WLBT_PCLK, + CLK_CON_GAT_GOUT_CMGP_SYSREG_PCLK, + CLK_CON_GAT_GOUT_CMGP_USI_CMGP00_IPCLK, + CLK_CON_GAT_GOUT_CMGP_USI_CMGP00_PCLK, + CLK_CON_GAT_GOUT_CMGP_USI_CMGP01_IPCLK, + CLK_CON_GAT_GOUT_CMGP_USI_CMGP01_PCLK, + CLK_CON_GAT_GOUT_CMGP_USI_CMGP02_IPCLK, + CLK_CON_GAT_GOUT_CMGP_USI_CMGP02_PCLK, + CLK_CON_GAT_GOUT_CMGP_USI_CMGP03_IPCLK, + CLK_CON_GAT_GOUT_CMGP_USI_CMGP03_PCLK, + CLK_CON_GAT_GOUT_CMGP_USI_CMGP04_IPCLK, + CLK_CON_GAT_GOUT_CMGP_USI_CMGP04_PCLK, +}; + +PNAME(mout_clk_cmgp_adc_p) =3D { "oscclk", "dout_clk_cmgp_adc" }; +PNAME(mout_clk_cmgp_i2c_p) =3D { "oscclk_rco", + "gout_cmu_cmgp_bus" }; +PNAME(mout_clk_cmgp_usi00_p) =3D { "oscclk_rco", + "gout_cmu_cmgp_bus" }; +PNAME(mout_clk_cmgp_usi01_p) =3D { "oscclk_rco", + "gout_cmu_cmgp_bus" }; +PNAME(mout_clk_cmgp_usi02_p) =3D { "oscclk_rco", + "gout_cmu_cmgp_bus" }; +PNAME(mout_clk_cmgp_usi03_p) =3D { "oscclk_rco", + "gout_cmu_cmgp_bus" }; +PNAME(mout_clk_cmgp_usi04_p) =3D { "oscclk_rco", + "gout_cmu_cmgp_bus" }; + +static const struct samsung_mux_clock cmgp_mux_clks[] __initconst =3D { + MUX(CLK_MOUT_CLK_CMGP_ADC, "mout_clk_cmgp_adc", mout_clk_cmgp_adc_p, + CLK_CON_MUX_MUX_CLK_CMGP_ADC, 0, 1), + MUX(CLK_MOUT_CLK_CMGP_I2C, "mout_clk_cmgp_i2c", mout_clk_cmgp_i2c_p, + CLK_CON_MUX_MUX_CLK_CMGP_I2C, 0, 1), + MUX(CLK_MOUT_CLK_CMGP_USI00, "mout_clk_cmgp_usi00", mout_clk_cmgp_usi00_p, + CLK_CON_MUX_MUX_CLK_CMGP_USI00, 0, 1), + MUX(CLK_MOUT_CLK_CMGP_USI01, "mout_clk_cmgp_usi01", mout_clk_cmgp_usi01_p, + CLK_CON_MUX_MUX_CLK_CMGP_USI01, 0, 1), + MUX(CLK_MOUT_CLK_CMGP_USI02, "mout_clk_cmgp_usi02", mout_clk_cmgp_usi02_p, + CLK_CON_MUX_MUX_CLK_CMGP_USI02, 0, 1), + MUX(CLK_MOUT_CLK_CMGP_USI03, "mout_clk_cmgp_usi03", mout_clk_cmgp_usi03_p, + CLK_CON_MUX_MUX_CLK_CMGP_USI03, 0, 1), + MUX(CLK_MOUT_CLK_CMGP_USI04, "mout_clk_cmgp_usi04", mout_clk_cmgp_usi04_p, + CLK_CON_MUX_MUX_CLK_CMGP_USI04, 0, 1), +}; + +static const struct samsung_div_clock cmgp_div_clks[] __initconst =3D { + DIV(CLK_DOUT_CLK_CMGP_ADC, "dout_clk_cmgp_adc", "gout_cmu_cmgp_bus", + CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0, 4), + DIV(CLK_DOUT_CLK_CMGP_I2C, "dout_clk_cmgp_i2c", "mout_clk_cmgp_i2c", + CLK_CON_DIV_DIV_CLK_CMGP_I2C, 0, 4), + DIV(CLK_DOUT_CLK_CMGP_USI00, "dout_clk_cmgp_usi00", "mout_clk_cmgp_usi00", + CLK_CON_DIV_DIV_CLK_CMGP_USI00, 0, 4), + DIV(CLK_DOUT_CLK_CMGP_USI01, "dout_clk_cmgp_usi01", "mout_clk_cmgp_usi01", + CLK_CON_DIV_DIV_CLK_CMGP_USI01, 0, 4), + DIV(CLK_DOUT_CLK_CMGP_USI02, "dout_clk_cmgp_usi02", "mout_clk_cmgp_usi02", + CLK_CON_DIV_DIV_CLK_CMGP_USI02, 0, 4), + DIV(CLK_DOUT_CLK_CMGP_USI03, "dout_clk_cmgp_usi03", "mout_clk_cmgp_usi03", + CLK_CON_DIV_DIV_CLK_CMGP_USI03, 0, 4), + DIV(CLK_DOUT_CLK_CMGP_USI04, "dout_clk_cmgp_usi04", "mout_clk_cmgp_usi04", + CLK_CON_DIV_DIV_CLK_CMGP_USI04, 0, 4), +}; + +static const struct samsung_gate_clock cmgp_gate_clks[] __initconst =3D { + GATE(CLK_GOUT_CMGP_CMU_PCLK, "gout_cmgp_cmu_pclk", "gout_cmu_cmgp_bus", + CLK_CON_GAT_CMGP_CMU_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CLK_CMGP_OSCCLK_RCO_CLK, "gout_clk_cmgp_oscclk_rco_clk", + "oscclk_rco", CLK_CON_GAT_CLK_CMGP_OSCCLK_RCO_CLK, 21, CLK_IGNORE_UN= USED, 0), + GATE(CLK_GOUT_CMGP_ADC_PCLK_S0, "gout_clk_cmgp_adc_pclk_s0", + "gout_cmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_ADC_PCLK_S1, "gout_clk_cmgp_adc_pclk_s1", + "gout_cmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_GPIO_PCLK, "gout_clk_cmgp_gpio_pclk", + "gout_cmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_I2C_CMGP00_IPCLK, "gout_clk_cmgp_i2c_cmgp00_ipclk", + "mout_clk_cmgp_i2c", CLK_CON_GAT_GOUT_CMGP_I2C_CMGP00_IPCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_I2C_CMGP00_PCLK, "gout_clk_cmgp_i2c_cmgp00_pclk", + "gout_cmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_I2C_CMGP00_IPCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_I2C_CMGP01_IPCLK, "gout_clk_cmgp_i2c_cmgp01_ipclk", + "mout_clk_cmgp_i2c", CLK_CON_GAT_GOUT_CMGP_I2C_CMGP01_IPCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_I2C_CMGP01_PCLK, "gout_clk_cmgp_i2c_cmgp01_pclk", + "gout_cmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_I2C_CMGP01_IPCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_I2C_CMGP02_IPCLK, "gout_clk_cmgp_i2c_cmgp02_ipclk", + "mout_clk_cmgp_i2c", CLK_CON_GAT_GOUT_CMGP_I2C_CMGP02_IPCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_I2C_CMGP02_PCLK, "gout_clk_cmgp_i2c_cmgp02_pclk", + "gout_cmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_I2C_CMGP02_IPCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_I2C_CMGP03_IPCLK, "gout_clk_cmgp_i2c_cmgp03_ipclk", + "mout_clk_cmgp_i2c", CLK_CON_GAT_GOUT_CMGP_I2C_CMGP03_IPCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_I2C_CMGP03_PCLK, "gout_clk_cmgp_i2c_cmgp03_pclk", + "gout_cmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_I2C_CMGP03_IPCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_I2C_CMGP04_IPCLK, "gout_clk_cmgp_i2c_cmgp04_ipclk", + "mout_clk_cmgp_i2c", CLK_CON_GAT_GOUT_CMGP_I2C_CMGP04_IPCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_I2C_CMGP04_PCLK, "gout_clk_cmgp_i2c_cmgp04_pclk", + "gout_cmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_I2C_CMGP04_IPCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_BUS_CLK, "gout_cmgp_bus_clk", + "gout_cmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_BUS_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_I2C_CLK, "gout_cmgp_i2c_clk", + "dout_clk_cmgp_i2c", CLK_CON_GAT_GOUT_CMGP_I2C_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_USI00_CLK, "gout_cmgp_usi00_clk", + "mout_clk_cmgp_usi00", CLK_CON_GAT_GOUT_CMGP_USI00_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_USI01_CLK, "gout_cmgp_usi01_clk", + "mout_clk_cmgp_usi01", CLK_CON_GAT_GOUT_CMGP_USI01_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_USI02_CLK, "gout_cmgp_usi02_clk", + "mout_clk_cmgp_usi02", CLK_CON_GAT_GOUT_CMGP_USI02_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_USI03_CLK, "gout_cmgp_usi03_clk", + "mout_clk_cmgp_usi03", CLK_CON_GAT_GOUT_CMGP_USI03_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_USI04_CLK, "gout_cmgp_usi04_clk", + "mout_clk_cmgp_usi04", CLK_CON_GAT_GOUT_CMGP_USI04_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_SYSREG_CMGP2CP_PCLK, + "gout_cmgp_sysreg_cmgp2cp_pclk", "gout_cmu_cmgp_bus", + CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2CP_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_SYSREG_CMGP2GNSS_PCLK, + "gout_cmgp_sysreg_cmgp2gnss_pclk", "gout_cmu_cmgp_bus", + CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2GNSS_PCLK, 21, CLK_IGNORE_UNUSED, = 0), + GATE(CLK_GOUT_CMGP_SYSREG_CMGP2PMU_AP_PCLK, + "gout_cmgp_sysreg_cmgp2pmu_ap_pclk", "gout_cmu_cmgp_bus", + CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2PMU_AP_PCLK, 21, CLK_IGNORE_UNUSED= , 0), + GATE(CLK_GOUT_CMGP_SYSREG_CMGP2PMU_SHUB_PCLK, + "gout_cmgp_sysreg_cmgp2pmu_shub_pclk", "gout_cmu_cmgp_bus", + CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2PMU_SHUB_PCLK, 21, CLK_IGNORE_UNUS= ED, 0), + GATE(CLK_GOUT_CMGP_SYSREG_CMGP2SHUB_PCLK, + "gout_cmgp_sysreg_cmgp2shub_pclk", "gout_cmu_cmgp_bus", + CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2SHUB_PCLK, 21, CLK_IGNORE_UNUSED, = 0), + GATE(CLK_GOUT_CMGP_SYSREG_CMGP2WLBT_PCLK, + "gout_cmgp_sysreg_cmgp2wlbt_pclk", "gout_cmu_cmgp_bus", + CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP2WLBT_PCLK, 21, CLK_IGNORE_UNUSED, = 0), + GATE(CLK_GOUT_CMGP_SYSREG_PCLK, "gout_cmgp_sysreg_pclk", + "gout_cmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_SYSREG_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_USI_CMGP00_IPCLK, "gout_clk_cmgp_usi_cmgp00_ipclk", + "mout_clk_cmgp_usi00", CLK_CON_GAT_GOUT_CMGP_USI_CMGP00_IPCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_USI_CMGP00_PCLK, "gout_clk_cmgp_usi_cmgp00_pclk", + "gout_cmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_USI_CMGP00_IPCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_USI_CMGP01_IPCLK, "gout_clk_cmgp_usi_cmgp01_ipclk", + "mout_clk_cmgp_usi01", CLK_CON_GAT_GOUT_CMGP_USI_CMGP01_IPCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_USI_CMGP01_PCLK, "gout_clk_cmgp_usi_cmgp01_pclk", + "gout_cmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_USI_CMGP01_IPCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_USI_CMGP02_IPCLK, "gout_clk_cmgp_usi_cmgp02_ipclk", + "mout_clk_cmgp_usi02", CLK_CON_GAT_GOUT_CMGP_USI_CMGP02_IPCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_USI_CMGP02_PCLK, "gout_clk_cmgp_usi_cmgp02_pclk", + "gout_cmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_USI_CMGP02_IPCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_USI_CMGP03_IPCLK, "gout_clk_cmgp_usi_cmgp03_ipclk", + "mout_clk_cmgp_usi03", CLK_CON_GAT_GOUT_CMGP_USI_CMGP03_IPCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_USI_CMGP03_PCLK, "gout_clk_cmgp_usi_cmgp03_pclk", + "gout_cmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_USI_CMGP03_IPCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_USI_CMGP04_IPCLK, "gout_clk_cmgp_usi_cmgp04_ipclk", + "mout_clk_cmgp_usi04", CLK_CON_GAT_GOUT_CMGP_USI_CMGP04_IPCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CMGP_USI_CMGP04_PCLK, "gout_clk_cmgp_usi_cmgp04_pclk", + "gout_cmu_cmgp_bus", CLK_CON_GAT_GOUT_CMGP_USI_CMGP04_IPCLK, + 21, CLK_IGNORE_UNUSED, 0), +}; + +static const struct samsung_cmu_info cmgp_cmu_info __initconst =3D { + .mux_clks =3D cmgp_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(cmgp_mux_clks), + .div_clks =3D cmgp_div_clks, + .nr_div_clks =3D ARRAY_SIZE(cmgp_div_clks), + .gate_clks =3D cmgp_gate_clks, + .nr_gate_clks =3D ARRAY_SIZE(cmgp_gate_clks), + .clk_regs =3D cmgp_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(cmgp_clk_regs), + .nr_clk_ids =3D CLKS_NR_CMGP, +}; + +/* CMU_CORE */ +#define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0100 +#define PLL_CON2_MUX_CLKCMU_CORE_BUS_USER 0x0108 +#define PLL_CON0_MUX_CLKCMU_CORE_CCI_USER 0x0120 +#define PLL_CON2_MUX_CLKCMU_CORE_CCI_USER 0x0128 +#define PLL_CON0_MUX_CLKCMU_CORE_G3D_USER 0x0140 +#define PLL_CON2_MUX_CLKCMU_CORE_G3D_USER 0x0148 +#define CLK_CON_MUX_MUX_CLK_CORE_GIC 0x1000 +#define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800 +#define CLK_CON_GAT_CLK_CORE_CMU_PCLK 0x2000 +#define CLK_CON_GAT_GOUT_CORE_AD_APB_CCI_550_PCLKM 0x2004 +#define CLK_CON_GAT_GOUT_CORE_AD_APB_DIT_PCLKM 0x2008 +#define CLK_CON_GAT_GOUT_CORE_AD_APB_PDMA0_PCLKM 0x200c +#define CLK_CON_GAT_GOUT_CORE_AD_APB_PGEN_PDMA_PCLKM 0x2010 +#define CLK_CON_GAT_GOUT_CORE_AD_APB_PPFW_MEM0_PCLKM 0x2014 +#define CLK_CON_GAT_GOUT_CORE_AD_APB_PPFW_MEM1_PCLKM 0x2018 +#define CLK_CON_GAT_GOUT_CORE_AD_APB_PPFW_PERI_PCLKM 0x201c +#define CLK_CON_GAT_GOUT_CORE_AD_APB_SPDMA_PCLKM 0x2020 +#define CLK_CON_GAT_GOUT_CORE_AD_AXI_GIC_ACLKM 0x2024 +#define CLK_CON_GAT_GOUT_CORE_ASYNCSFR_WR_DMC0_PCLK 0x2028 +#define CLK_CON_GAT_GOUT_CORE_ASYNCSFR_WR_DMC1_PCLK 0x202c +#define CLK_CON_GAT_GOUT_CORE_AXI_US_A40_64TO128_DIT_ACLK 0x2030 +#define CLK_CON_GAT_GOUT_CORE_BAAW_P_GNSS_PCLK 0x2034 +#define CLK_CON_GAT_GOUT_CORE_BAAW_P_MODEM_PCLK 0x2038 +#define CLK_CON_GAT_GOUT_CORE_BAAW_P_SHUB_PCLK 0x203c +#define CLK_CON_GAT_GOUT_CORE_BAAW_P_WLBT_PCLK 0x2040 +#define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2044 +#define CLK_CON_GAT_GOUT_CORE_DIT_ICLKL2A 0x2048 +#define CLK_CON_GAT_GOUT_CORE_GIC400_AIHWACG_CLK 0x204c +#define CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D0_ISP_CLK 0x2050 +#define CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D0_MFC_CLK 0x2054 +#define CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D1_ISP_CLK 0x2058 +#define CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D1_MFC_CLK 0x205c +#define CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_CAM_CLK 0x2060 +#define CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_DPU_CLK 0x2064 +#define CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_FSYS_CLK 0x2068 +#define CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_G2D_CLK 0x206c +#define CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_USB_CLK 0x2070 +#define CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_VIPX1_CLK 0x2074 +#define CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_VIPX2_CLK 0x2078 +#define CLK_CON_GAT_GOUT_CORE_LHM_ACE_D_CPUCL0_CLK 0x207c +#define CLK_CON_GAT_GOUT_CORE_LHM_ACE_D_CPUCL1_CLK 0x2080 +#define CLK_CON_GAT_GOUT_CORE_LHM_AXI_D0_MODEM_CLK 0x2084 +#define CLK_CON_GAT_GOUT_CORE_LHM_AXI_D1_MODEM_CLK 0x2088 +#define CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_ABOX_CLK 0x208c +#define CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_APM_CLK 0x2090 +#define CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_CSSYS_CLK 0x2094 +#define CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_G3D_CLK 0x2098 +#define CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_GNSS_CLK 0x209c +#define CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_SHUB_CLK 0x20a0 +#define CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_WLBT_CLK 0x20a4 +#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_D0_MIF_CPU_CLK 0x20a8 +#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_D0_MIF_CP_CLK 0x20ac +#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_D0_MIF_NRT_CLK 0x20b0 +#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_D0_MIF_RT_CLK 0x20b4 +#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_D1_MIF_CPU_CLK 0x20b8 +#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_D1_MIF_CP_CLK 0x20bc +#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_D1_MIF_NRT_CLK 0x20c0 +#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_D1_MIF_RT_CLK 0x20c4 +#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_APM_CLK 0x20c8 +#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_CAM_CLK 0x20cc +#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_CPUCL0_CLK 0x20d0 +#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_CPUCL1_CLK 0x20d4 +#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_DISPAUD_CLK 0x20d8 +#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_FSYS_CLK 0x20dc +#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_G2D_CLK 0x20e0 +#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_G3D_CLK 0x20e4 +#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_GNSS_CLK 0x20e8 +#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_ISP_CLK 0x20ec +#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_MFC_CLK 0x20f0 +#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_MIF0_CLK 0x20f4 +#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_MIF1_CLK 0x20f8 +#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_MODEM_CLK 0x20fc +#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_PERI_CLK 0x2100 +#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_SHUB_CLK 0x2104 +#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_USB_CLK 0x2108 +#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_VIPX1_CLK 0x210c +#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_VIPX2_CLK 0x2110 +#define CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_WLBT_CLK 0x2114 +#define CLK_CON_GAT_GOUT_CORE_PDMA_CORE_ACLK_PDMA0 0x2118 +#define CLK_CON_GAT_GOUT_CORE_PGEN_LITE_SIREX_CLK 0x211c +#define CLK_CON_GAT_GOUT_CORE_PGEN_PDMA_CLK 0x2120 +#define CLK_CON_GAT_GOUT_CORE_PPCFW_G3D_ACLK 0x2124 +#define CLK_CON_GAT_GOUT_CORE_PPCFW_G3D_PCLK 0x2128 +#define CLK_CON_GAT_GOUT_CORE_PPFW_CORE_MEM0_CLK 0x212c +#define CLK_CON_GAT_GOUT_CORE_PPFW_CORE_MEM1_CLK 0x2130 +#define CLK_CON_GAT_GOUT_CORE_PPFW_CORE_PERI_CLK 0x2134 +#define CLK_CON_GAT_GOUT_CORE_PPMU_ACE_CPUCL0_ACLK 0x2138 +#define CLK_CON_GAT_GOUT_CORE_PPMU_ACE_CPUCL0_PCLK 0x213c +#define CLK_CON_GAT_GOUT_CORE_PPMU_ACE_CPUCL1_ACLK 0x2140 +#define CLK_CON_GAT_GOUT_CORE_PPMU_ACE_CPUCL1_PCLK 0x2144 +#define CLK_CON_GAT_GOUT_CORE_BUSD_CLK 0x2148 +#define CLK_CON_GAT_GOUT_CORE_BUSP_G3D_OCC_CLK 0x214c +#define CLK_CON_GAT_GOUT_CORE_BUSP_CLK 0x2150 +#define CLK_CON_GAT_GOUT_CORE_BUSP_OCC_CLK 0x2154 +#define CLK_CON_GAT_GOUT_CORE_CCI_CLK 0x2158 +#define CLK_CON_GAT_GOUT_CORE_CCI_OCC_CLK 0x215c +#define CLK_CON_GAT_GOUT_CORE_G3D_CLK 0x2160 +#define CLK_CON_GAT_GOUT_CORE_G3D_OCC_CLK 0x2164 +#define CLK_CON_GAT_GOUT_CORE_GIC_CLK 0x2168 +#define CLK_CON_GAT_GOUT_CORE_OSCCLK_CLK 0x216c +#define CLK_CON_GAT_GOUT_CORE_SFR_APBIF_CMU_TOPC_PCLK 0x2170 +#define CLK_CON_GAT_GOUT_CORE_SIREX_ACLK 0x2174 +#define CLK_CON_GAT_GOUT_CORE_SIREX_PCLK 0x2178 +#define CLK_CON_GAT_GOUT_CORE_SPDMA_CORE_ACLK_PDMA1 0x217c +#define CLK_CON_GAT_GOUT_CORE_SYSREG_PCLK 0x2180 +#define CLK_CON_GAT_GOUT_CORE_TREX_D_ACLK 0x2184 +#define CLK_CON_GAT_GOUT_CORE_TREX_D_CCLK 0x2188 +#define CLK_CON_GAT_GOUT_CORE_TREX_D_GCLK 0x218c +#define CLK_CON_GAT_GOUT_CORE_TREX_D_PCLK 0x2190 +#define CLK_CON_GAT_GOUT_CORE_TREX_D_NRT_ACLK 0x2194 +#define CLK_CON_GAT_GOUT_CORE_TREX_D_NRT_PCLK 0x2198 +#define CLK_CON_GAT_GOUT_CORE_TREX_P_ACLK_P_CORE 0x219c +#define CLK_CON_GAT_GOUT_CORE_TREX_P_CCLK_P_CORE 0x21a0 +#define CLK_CON_GAT_GOUT_CORE_TREX_P_PCLK 0x21a4 +#define CLK_CON_GAT_GOUT_CORE_TREX_P_PCLK_P_CORE 0x21a8 +#define CLK_CON_GAT_GOUT_CORE_XIU_D_ACLK 0x21ac + +static const unsigned long core_clk_regs[] __initconst =3D { + PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, + PLL_CON2_MUX_CLKCMU_CORE_BUS_USER, + PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, + PLL_CON2_MUX_CLKCMU_CORE_CCI_USER, + PLL_CON0_MUX_CLKCMU_CORE_G3D_USER, + PLL_CON2_MUX_CLKCMU_CORE_G3D_USER, + CLK_CON_MUX_MUX_CLK_CORE_GIC, + CLK_CON_DIV_DIV_CLK_CORE_BUSP, + CLK_CON_GAT_CLK_CORE_CMU_PCLK, + CLK_CON_GAT_GOUT_CORE_AD_APB_CCI_550_PCLKM, + CLK_CON_GAT_GOUT_CORE_AD_APB_DIT_PCLKM, + CLK_CON_GAT_GOUT_CORE_AD_APB_PDMA0_PCLKM, + CLK_CON_GAT_GOUT_CORE_AD_APB_PGEN_PDMA_PCLKM, + CLK_CON_GAT_GOUT_CORE_AD_APB_PPFW_MEM0_PCLKM, + CLK_CON_GAT_GOUT_CORE_AD_APB_PPFW_MEM1_PCLKM, + CLK_CON_GAT_GOUT_CORE_AD_APB_PPFW_PERI_PCLKM, + CLK_CON_GAT_GOUT_CORE_AD_APB_SPDMA_PCLKM, + CLK_CON_GAT_GOUT_CORE_AD_AXI_GIC_ACLKM, + CLK_CON_GAT_GOUT_CORE_ASYNCSFR_WR_DMC0_PCLK, + CLK_CON_GAT_GOUT_CORE_ASYNCSFR_WR_DMC1_PCLK, + CLK_CON_GAT_GOUT_CORE_AXI_US_A40_64TO128_DIT_ACLK, + CLK_CON_GAT_GOUT_CORE_BAAW_P_GNSS_PCLK, + CLK_CON_GAT_GOUT_CORE_BAAW_P_MODEM_PCLK, + CLK_CON_GAT_GOUT_CORE_BAAW_P_SHUB_PCLK, + CLK_CON_GAT_GOUT_CORE_BAAW_P_WLBT_PCLK, + CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, + CLK_CON_GAT_GOUT_CORE_DIT_ICLKL2A, + CLK_CON_GAT_GOUT_CORE_GIC400_AIHWACG_CLK, + CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D0_ISP_CLK, + CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D0_MFC_CLK, + CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D1_ISP_CLK, + CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D1_MFC_CLK, + CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_CAM_CLK, + CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_DPU_CLK, + CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_FSYS_CLK, + CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_G2D_CLK, + CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_USB_CLK, + CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_VIPX1_CLK, + CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_VIPX2_CLK, + CLK_CON_GAT_GOUT_CORE_LHM_ACE_D_CPUCL0_CLK, + CLK_CON_GAT_GOUT_CORE_LHM_ACE_D_CPUCL1_CLK, + CLK_CON_GAT_GOUT_CORE_LHM_AXI_D0_MODEM_CLK, + CLK_CON_GAT_GOUT_CORE_LHM_AXI_D1_MODEM_CLK, + CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_ABOX_CLK, + CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_APM_CLK, + CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_CSSYS_CLK, + CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_G3D_CLK, + CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_GNSS_CLK, + CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_SHUB_CLK, + CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_WLBT_CLK, + CLK_CON_GAT_GOUT_CORE_LHS_AXI_D0_MIF_CPU_CLK, + CLK_CON_GAT_GOUT_CORE_LHS_AXI_D0_MIF_CP_CLK, + CLK_CON_GAT_GOUT_CORE_LHS_AXI_D0_MIF_NRT_CLK, + CLK_CON_GAT_GOUT_CORE_LHS_AXI_D0_MIF_RT_CLK, + CLK_CON_GAT_GOUT_CORE_LHS_AXI_D1_MIF_CPU_CLK, + CLK_CON_GAT_GOUT_CORE_LHS_AXI_D1_MIF_CP_CLK, + CLK_CON_GAT_GOUT_CORE_LHS_AXI_D1_MIF_NRT_CLK, + CLK_CON_GAT_GOUT_CORE_LHS_AXI_D1_MIF_RT_CLK, + CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_APM_CLK, + CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_CAM_CLK, + CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_CPUCL0_CLK, + CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_CPUCL1_CLK, + CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_DISPAUD_CLK, + CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_FSYS_CLK, + CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_G2D_CLK, + CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_G3D_CLK, + CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_GNSS_CLK, + CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_ISP_CLK, + CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_MFC_CLK, + CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_MIF0_CLK, + CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_MIF1_CLK, + CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_MODEM_CLK, + CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_PERI_CLK, + CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_SHUB_CLK, + CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_USB_CLK, + CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_VIPX1_CLK, + CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_VIPX2_CLK, + CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_WLBT_CLK, + CLK_CON_GAT_GOUT_CORE_PDMA_CORE_ACLK_PDMA0, + CLK_CON_GAT_GOUT_CORE_PGEN_LITE_SIREX_CLK, + CLK_CON_GAT_GOUT_CORE_PGEN_PDMA_CLK, + CLK_CON_GAT_GOUT_CORE_PPCFW_G3D_ACLK, + CLK_CON_GAT_GOUT_CORE_PPCFW_G3D_PCLK, + CLK_CON_GAT_GOUT_CORE_PPFW_CORE_MEM0_CLK, + CLK_CON_GAT_GOUT_CORE_PPFW_CORE_MEM1_CLK, + CLK_CON_GAT_GOUT_CORE_PPFW_CORE_PERI_CLK, + CLK_CON_GAT_GOUT_CORE_PPMU_ACE_CPUCL0_ACLK, + CLK_CON_GAT_GOUT_CORE_PPMU_ACE_CPUCL0_PCLK, + CLK_CON_GAT_GOUT_CORE_PPMU_ACE_CPUCL1_ACLK, + CLK_CON_GAT_GOUT_CORE_PPMU_ACE_CPUCL1_PCLK, + CLK_CON_GAT_GOUT_CORE_BUSD_CLK, + CLK_CON_GAT_GOUT_CORE_BUSP_G3D_OCC_CLK, + CLK_CON_GAT_GOUT_CORE_BUSP_CLK, + CLK_CON_GAT_GOUT_CORE_BUSP_OCC_CLK, + CLK_CON_GAT_GOUT_CORE_CCI_CLK, + CLK_CON_GAT_GOUT_CORE_CCI_OCC_CLK, + CLK_CON_GAT_GOUT_CORE_G3D_CLK, + CLK_CON_GAT_GOUT_CORE_G3D_OCC_CLK, + CLK_CON_GAT_GOUT_CORE_GIC_CLK, + CLK_CON_GAT_GOUT_CORE_OSCCLK_CLK, + CLK_CON_GAT_GOUT_CORE_SFR_APBIF_CMU_TOPC_PCLK, + CLK_CON_GAT_GOUT_CORE_SIREX_ACLK, + CLK_CON_GAT_GOUT_CORE_SIREX_PCLK, + CLK_CON_GAT_GOUT_CORE_SPDMA_CORE_ACLK_PDMA1, + CLK_CON_GAT_GOUT_CORE_SYSREG_PCLK, + CLK_CON_GAT_GOUT_CORE_TREX_D_ACLK, + CLK_CON_GAT_GOUT_CORE_TREX_D_CCLK, + CLK_CON_GAT_GOUT_CORE_TREX_D_GCLK, + CLK_CON_GAT_GOUT_CORE_TREX_D_PCLK, + CLK_CON_GAT_GOUT_CORE_TREX_D_NRT_ACLK, + CLK_CON_GAT_GOUT_CORE_TREX_D_NRT_PCLK, + CLK_CON_GAT_GOUT_CORE_TREX_P_ACLK_P_CORE, + CLK_CON_GAT_GOUT_CORE_TREX_P_CCLK_P_CORE, + CLK_CON_GAT_GOUT_CORE_TREX_P_PCLK, + CLK_CON_GAT_GOUT_CORE_TREX_P_PCLK_P_CORE, + CLK_CON_GAT_GOUT_CORE_XIU_D_ACLK, +}; + +PNAME(mout_pll_core_bus_user_p) =3D { "oscclk", + "dout_cmu_core_bus" }; +PNAME(mout_pll_core_cci_user_p) =3D { "oscclk", + "dout_cmu_core_cci" }; +PNAME(mout_pll_core_g3d_user_p) =3D { "oscclk", + "dout_cmu_core_g3d" }; +PNAME(mout_clk_core_gic_p) =3D { "oscclk", + "dout_clk_core_busp" }; + +static const struct samsung_mux_clock core_mux_clks[] __initconst =3D { + MUX(CLK_MOUT_PLL_CORE_BUS_USER, "mout_pll_core_bus_user", mout_pll_core_b= us_user_p, + PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 4, 1), + MUX(CLK_MOUT_PLL_CORE_CCI_USER, "mout_pll_core_cci_user", mout_pll_core_c= ci_user_p, + PLL_CON0_MUX_CLKCMU_CORE_CCI_USER, 4, 1), + MUX(CLK_MOUT_PLL_CORE_G3D_USER, "mout_pll_core_g3d_user", mout_pll_core_g= 3d_user_p, + PLL_CON0_MUX_CLKCMU_CORE_G3D_USER, 4, 1), + MUX(CLK_MOUT_CLK_CORE_GIC, "mout_clk_core_gic", mout_clk_core_gic_p, + CLK_CON_MUX_MUX_CLK_CORE_GIC, 0, 1), +}; + +static const struct samsung_div_clock core_div_clks[] __initconst =3D { + DIV(CLK_DOUT_CLK_CORE_BUSP, "dout_clk_core_busp", "mout_pll_core_bus_user= ", + CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 2), +}; + +static const struct samsung_gate_clock core_gate_clks[] __initconst =3D { + GATE(CLK_GOUT_CLK_CORE_CMU_PCLK, "gout_clk_core_cmu_pclk", "dout_clk_core= _busp", + CLK_CON_GAT_CLK_CORE_CMU_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_AD_APB_CCI_550_PCLKM, "gout_core_ad_apb_cci_550_pclkm", + "mout_pll_core_cci_user", CLK_CON_GAT_GOUT_CORE_AD_APB_CCI_550_PCLKM, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_AD_APB_DIT_PCLKM, "gout_core_ad_apb_dit_pclkm", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_AD_APB_DIT_PCLKM, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_AD_APB_PDMA0_PCLKM, "gout_core_ad_apb_pdma0_pclkm", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_AD_APB_PDMA0_PCLKM, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_AD_APB_PGEN_PDMA_PCLKM, "gout_core_ad_apb_pgen_pdma_pc= lkm", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_AD_APB_PGEN_PDMA_PCL= KM, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_AD_APB_PPFW_MEM0_PCLKM, "gout_core_ad_apb_ppfw_mem0_pc= lkm", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_AD_APB_PPFW_MEM0_PCL= KM, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_AD_APB_PPFW_MEM1_PCLKM, "gout_core_ad_apb_ppfw_mem1_pc= lkm", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_AD_APB_PPFW_MEM1_PCL= KM, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_AD_APB_PPFW_PERI_PCLKM, "gout_core_ad_apb_ppfw_peri_pc= lkm", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_AD_APB_PPFW_PERI_PCL= KM, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_AD_APB_SPDMA_PCLKM, "gout_core_ad_apb_spdma_pclkm", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_AD_APB_SPDMA_PCLKM, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_AD_AXI_GIC_ACLKM, "gout_core_ad_axi_gic_aclkm", + "mout_clk_core_gic", CLK_CON_GAT_GOUT_CORE_AD_AXI_GIC_ACLKM, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_ASYNCSFR_WR_DMC0_PCLK, "gout_core_asyncsfr_wr_dmc0_pcl= k", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_ASYNCSFR_WR_DMC0_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_ASYNCSFR_WR_DMC1_PCLK, "gout_core_asyncsfr_wr_dmc1_pcl= k", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_ASYNCSFR_WR_DMC1_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_AXI_US_A40_64TO128_DIT_ACLK, + "gout_core_axi_us_a40_64to128_dit_aclk", "mout_pll_core_bus_user", + CLK_CON_GAT_GOUT_CORE_AXI_US_A40_64TO128_DIT_ACLK, 21, CLK_IGNORE_UN= USED, 0), + GATE(CLK_GOUT_CORE_BAAW_P_GNSS_PCLK, "gout_core_baaw_p_gnss_pclk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_BAAW_P_GNSS_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_BAAW_P_MODEM_PCLK, "gout_core_baaw_p_modem_pclk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_BAAW_P_MODEM_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_BAAW_P_SHUB_PCLK, "gout_core_baaw_p_shub_pclk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_BAAW_P_SHUB_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_BAAW_P_WLBT_PCLK, "gout_core_baaw_p_wlbt_pclk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_BAAW_P_WLBT_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_CCI_550_ACLK, "gout_core_cci_550_aclk", + "mout_pll_core_cci_user", CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_DIT_ICLKL2A, "gout_core_dit_iclkl2a", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_DIT_ICLKL2A, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_GIC400_AIHWACG_CLK, "gout_core_gic400_aihwacg_clk", + "mout_clk_core_gic", CLK_CON_GAT_GOUT_CORE_GIC400_AIHWACG_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHM_ACEL_D0_ISP_CLK, "gout_core_lhm_acel_d0_isp_clk", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D0_ISP_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHM_ACEL_D0_MFC_CLK, "gout_core_lhm_acel_d0_mfc_clk", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D0_MFC_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHM_ACEL_D1_ISP_CLK, "gout_core_lhm_acel_d1_isp_clk", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D1_ISP_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHM_ACEL_D1_MFC_CLK, "gout_core_lhm_acel_d1_mfc_clk", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D1_MFC_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHM_ACEL_D_CAM_CLK, "gout_core_lhm_acel_d_cam_clk", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_CAM_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHM_ACEL_D_DPU_CLK, "gout_core_lhm_acel_d_dpu_clk", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_DPU_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHM_ACEL_D_FSYS_CLK, "gout_core_lhm_acel_d_fsys_clk", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_FSYS_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHM_ACEL_D_G2D_CLK, "gout_core_lhm_acel_d_g2d_clk", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_G2D_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHM_ACEL_D_USB_CLK, "gout_core_lhm_acel_d_usb_clk", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_USB_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHM_ACEL_D_VIPX1_CLK, "gout_core_lhm_acel_d_vipx1_clk", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_VIPX1_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHM_ACEL_D_VIPX2_CLK, "gout_core_lhm_acel_d_vipx2_clk", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_ACEL_D_VIPX2_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHM_ACE_D_CPUCL0_CLK, "gout_core_lhm_ace_d_cpucl0_clk", + "mout_pll_core_cci_user", CLK_CON_GAT_GOUT_CORE_LHM_ACE_D_CPUCL0_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHM_ACE_D_CPUCL1_CLK, "gout_core_lhm_ace_d_cpucl1_clk", + "mout_pll_core_cci_user", CLK_CON_GAT_GOUT_CORE_LHM_ACE_D_CPUCL1_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHM_AXI_D0_MODEM_CLK, "gout_core_lhm_axi_d0_modem_clk", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_AXI_D0_MODEM_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHM_AXI_D1_MODEM_CLK, "gout_core_lhm_axi_d1_modem_clk", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_AXI_D1_MODEM_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHM_AXI_D_ABOX_CLK, "gout_core_lhm_axi_d_abox_clk", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_ABOX_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHM_AXI_D_APM_CLK, "gout_core_lhm_axi_d_apm_clk", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_APM_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHM_AXI_D_CSSYS_CLK, "gout_core_lhm_axi_d_cssys_clk", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_CSSYS_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHM_AXI_D_G3D_CLK, "gout_core_lhm_axi_d_g3d_clk", + "mout_pll_core_g3d_user", CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_G3D_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHM_AXI_D_GNSS_CLK, "gout_core_lhm_axi_d_gnss_clk", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_GNSS_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHM_AXI_D_SHUB_CLK, "gout_core_lhm_axi_d_shub_clk", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_SHUB_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHM_AXI_D_WLBT_CLK, "gout_core_lhm_axi_d_wlbt_clk", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHM_AXI_D_WLBT_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHS_AXI_D0_MIF_CPU_CLK, "gout_core_lhs_axi_d0_mif_cpu_= clk", + "mout_pll_core_cci_user", CLK_CON_GAT_GOUT_CORE_LHS_AXI_D0_MIF_CPU_C= LK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHS_AXI_D0_MIF_CP_CLK, "gout_core_lhs_axi_d0_mif_cp_cl= k", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHS_AXI_D0_MIF_CP_CL= K, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHS_AXI_D0_MIF_NRT_CLK, "gout_core_lhs_axi_d0_mif_nrt_= clk", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHS_AXI_D0_MIF_NRT_C= LK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHS_AXI_D0_MIF_RT_CLK, "gout_core_lhs_axi_d0_mif_rt_cl= k", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHS_AXI_D0_MIF_RT_CL= K, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHS_AXI_D1_MIF_CPU_CLK, "gout_core_lhs_axi_d1_mif_cpu_= clk", + "mout_pll_core_cci_user", CLK_CON_GAT_GOUT_CORE_LHS_AXI_D1_MIF_CPU_C= LK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHS_AXI_D1_MIF_CP_CLK, "gout_core_lhs_axi_d1_mif_cp_cl= k", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHS_AXI_D1_MIF_CP_CL= K, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHS_AXI_D1_MIF_NRT_CLK, "gout_core_lhs_axi_d1_mif_nrt_= clk", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHS_AXI_D1_MIF_NRT_C= LK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHS_AXI_D1_MIF_RT_CLK, "gout_core_lhs_axi_d1_mif_rt_cl= k", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_LHS_AXI_D1_MIF_RT_CL= K, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHS_AXI_P_APM_CLK, "gout_core_lhs_axi_p_apm_clk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_APM_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHS_AXI_P_CAM_CLK, "gout_core_lhs_axi_p_cam_clk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_CAM_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHS_AXI_P_CPUCL0_CLK, "gout_core_lhs_axi_p_cpucl0_clk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_CPUCL0_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHS_AXI_P_CPUCL1_CLK, "gout_core_lhs_axi_p_cpucl1_clk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_CPUCL1_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHS_AXI_P_DISPAUD_CLK, "gout_core_lhs_axi_p_dispaud_cl= k", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_DISPAUD_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHS_AXI_P_FSYS_CLK, "gout_core_lhs_axi_p_fsys_clk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_FSYS_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHS_AXI_P_G2D_CLK, "gout_core_lhs_axi_p_g2d_clk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_G2D_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHS_AXI_P_G3D_CLK, "gout_core_lhs_axi_p_g3d_clk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_G3D_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHS_AXI_P_GNSS_CLK, "gout_core_lhs_axi_p_gnss_clk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_GNSS_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHS_AXI_P_ISP_CLK, "gout_core_lhs_axi_p_isp_clk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_ISP_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHS_AXI_P_MFC_CLK, "gout_core_lhs_axi_p_mfc_clk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_MFC_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHS_AXI_P_MIF0_CLK, "gout_core_lhs_axi_p_mif0_clk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_MIF0_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHS_AXI_P_MIF1_CLK, "gout_core_lhs_axi_p_mif1_clk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_MIF1_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHS_AXI_P_MODEM_CLK, "gout_core_lhs_axi_p_modem_clk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_MODEM_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHS_AXI_P_PERI_CLK, "gout_core_lhs_axi_p_peri_clk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_PERI_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHS_AXI_P_SHUB_CLK, "gout_core_lhs_axi_p_shub_clk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_SHUB_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHS_AXI_P_USB_CLK, "gout_core_lhs_axi_p_usb_clk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_USB_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHS_AXI_P_VIPX1_CLK, "gout_core_lhs_axi_p_vipx1_clk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_VIPX1_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHS_AXI_P_VIPX2_CLK, "gout_core_lhs_axi_p_vipx2_clk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_VIPX2_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_LHS_AXI_P_WLBT_CLK, "gout_core_lhs_wlbt_p_apm_clk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_LHS_AXI_P_WLBT_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_PDMA_CORE_ACLK_PDMA0, "gout_core_pdma_core_aclk_pdma0", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_PDMA_CORE_ACLK_PDMA0, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_PGEN_LITE_SIREX_CLK, "gout_core_pgen_lite_sirex_clk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_PGEN_LITE_SIREX_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_PGEN_PDMA_CLK, "gout_core_pgen_pdma_clk", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_PGEN_PDMA_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_PPCFW_G3D_ACLK, "gout_core_ppcfw_g3d_aclk", + "mout_pll_core_g3d_user", CLK_CON_GAT_GOUT_CORE_PPCFW_G3D_ACLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_PPCFW_G3D_PCLK, "gout_core_ppcfw_g3d_pclk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_PPCFW_G3D_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_PPFW_CORE_MEM0_CLK, "gout_core_ppfw_core_mem0_clk", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_PPFW_CORE_MEM0_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_PPFW_CORE_MEM1_CLK, "gout_core_ppfw_core_mem1_clk", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_PPFW_CORE_MEM1_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_PPFW_CORE_PERI_CLK, "gout_core_ppfw_core_peri_clk", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_PPFW_CORE_PERI_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_PPMU_ACE_CPUCL0_ACLK, "gout_core_ppmu_ace_cpucl0_aclk", + "mout_pll_core_cci_user", CLK_CON_GAT_GOUT_CORE_PPMU_ACE_CPUCL0_ACLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_PPMU_ACE_CPUCL0_PCLK, "gout_core_ppmu_ace_cpucl0_pclk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_PPMU_ACE_CPUCL0_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_PPMU_ACE_CPUCL1_ACLK, "gout_core_ppmu_ace_cpucl1_aclk", + "mout_pll_core_cci_user", CLK_CON_GAT_GOUT_CORE_PPMU_ACE_CPUCL1_ACLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_PPMU_ACE_CPUCL1_PCLK, "gout_core_ppmu_ace_cpucl1_pclk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_PPMU_ACE_CPUCL1_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_BUSD_CLK, "gout_core_busd_clk", "mout_pll_core_bus_use= r", + CLK_CON_GAT_GOUT_CORE_BUSD_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_BUSP_G3D_OCC_CLK, "gout_core_busp_g3d_occ_clk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_BUSP_G3D_OCC_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_BUSP_CLK, "gout_core_busp_clk", "dout_clk_core_busp", + CLK_CON_GAT_GOUT_CORE_BUSP_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_BUSP_OCC_CLK, "gout_core_busp_occ_clk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_BUSP_OCC_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_CCI_CLK, "gout_core_cci_clk", "mout_pll_core_cci_user", + CLK_CON_GAT_GOUT_CORE_CCI_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_CCI_OCC_CLK, "gout_core_cci_occ_clk", + "mout_pll_core_cci_user", CLK_CON_GAT_GOUT_CORE_CCI_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_G3D_CLK, "gout_core_g3d_clk", "mout_pll_core_g3d_user", + CLK_CON_GAT_GOUT_CORE_G3D_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_G3D_OCC_CLK, "gout_core_cci_g3d_occ_clk", + "mout_pll_core_cci_user", CLK_CON_GAT_GOUT_CORE_G3D_OCC_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_GIC_CLK, "gout_core_gic_clk", "mout_clk_core_gic", + CLK_CON_GAT_GOUT_CORE_GIC_CLK, 21, 0, 0), + GATE(CLK_GOUT_CORE_OSCCLK_CLK, "gout_core_oscclk_clk", "oscclk", + CLK_CON_GAT_GOUT_CORE_OSCCLK_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_SFR_APBIF_CMU_TOPC_PCLK, "gout_core_sfr_apbif_cmu_topc= _pclk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_SFR_APBIF_CMU_TOPC_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_SIREX_ACLK, "gout_core_sirex_aclk", "mout_pll_core_bus= _user", + CLK_CON_GAT_GOUT_CORE_SIREX_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_SIREX_PCLK, "gout_core_sirex_pclk", "dout_clk_core_bus= p", + CLK_CON_GAT_GOUT_CORE_SIREX_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_SPDMA_CORE_ACLK_PDMA1, "gout_core_spdma_core_aclk_pdma= 1", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_SPDMA_CORE_ACLK_PDMA= 1, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_SYSREG_PCLK, "gout_core_sysreg_pclk", "dout_clk_core_b= usp", + CLK_CON_GAT_GOUT_CORE_SYSREG_PCLK, 21, 0, 0), + GATE(CLK_GOUT_CORE_TREX_D_ACLK, "gout_core_trex_d_aclk", "mout_pll_core_b= us_user", + CLK_CON_GAT_GOUT_CORE_TREX_D_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_TREX_D_CCLK, "gout_core_trex_d_cclk", "mout_pll_core_c= ci_user", + CLK_CON_GAT_GOUT_CORE_TREX_D_CCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_TREX_D_GCLK, "gout_core_trex_d_gclk", "mout_pll_core_g= 3d_user", + CLK_CON_GAT_GOUT_CORE_TREX_D_GCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_TREX_D_PCLK, "gout_core_trex_d_pclk", "dout_clk_core_b= usp", + CLK_CON_GAT_GOUT_CORE_TREX_D_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_TREX_D_NRT_ACLK, "gout_core_trex_d_nrt_aclk", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_TREX_D_NRT_ACLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_TREX_D_NRT_PCLK, "gout_core_trex_d_nrt_pclk", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_TREX_D_NRT_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + + GATE(CLK_GOUT_CORE_TREX_P_ACLK_P_CORE, "gout_core_trex_p_aclk_p_core", + "mout_pll_core_bus_user", CLK_CON_GAT_GOUT_CORE_TREX_P_ACLK_P_CORE, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_TREX_P_CCLK_P_CORE, "gout_core_trex_p_cclk_p_core", + "mout_pll_core_cci_user", CLK_CON_GAT_GOUT_CORE_TREX_P_CCLK_P_CORE, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_TREX_P_PCLK, "gout_core_trex_p_pclk", "dout_clk_core_b= usp", + CLK_CON_GAT_GOUT_CORE_TREX_P_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_TREX_P_PCLK_P_CORE, "gout_core_trex_p_pclk_p_core", + "dout_clk_core_busp", CLK_CON_GAT_GOUT_CORE_TREX_P_PCLK_P_CORE, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CORE_XIU_D_ACLK, "gout_core_xiu_d_aclk", "mout_pll_core_bus= _user", + CLK_CON_GAT_GOUT_CORE_XIU_D_ACLK, 21, CLK_IGNORE_UNUSED, 0), +}; + +static const struct samsung_cmu_info core_cmu_info __initconst =3D { + .mux_clks =3D core_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(core_mux_clks), + .gate_clks =3D core_gate_clks, + .nr_gate_clks =3D ARRAY_SIZE(core_gate_clks), + .clk_regs =3D core_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(core_clk_regs), + .nr_clk_ids =3D CLKS_NR_CORE, +}; + +/* CMU_DISPAUD */ +#define PLL_LOCKTIME_PLL_AUD 0x0000 +#define PLL_CON0_MUX_CLKCMU_DISPAUD_AUD_USER 0x0100 +#define PLL_CON2_MUX_CLKCMU_DISPAUD_AUD_USER 0x0108 +#define PLL_CON0_MUX_CLKCMU_DISPAUD_CPU_USER 0x0120 +#define PLL_CON2_MUX_CLKCMU_DISPAUD_CPU_USER 0x0128 +#define PLL_CON0_MUX_CLKCMU_DISPAUD_DISP_USER 0x0140 +#define PLL_CON2_MUX_CLKCMU_DISPAUD_DISP_USER 0x0148 +#define PLL_CON0_PLL_AUD 0x0160 +#define PLL_CON3_PLL_AUD 0x016c +#define CLK_CON_MUX_MUX_CLK_AUD_BUS 0x1000 +#define CLK_CON_MUX_MUX_CLK_AUD_CPU 0x1004 +#define CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH 0x1008 +#define CLK_CON_MUX_MUX_CLK_AUD_FM 0x100c +#define CLK_CON_MUX_MUX_CLK_AUD_UAIF0 0x1010 +#define CLK_CON_MUX_MUX_CLK_AUD_UAIF1 0x1014 +#define CLK_CON_MUX_MUX_CLK_AUD_UAIF2 0x1018 +#define CLK_CON_DIV_DIV_CLK_AUD_AUDIF 0x1800 +#define CLK_CON_DIV_DIV_CLK_AUD_BUS 0x1808 +#define CLK_CON_DIV_DIV_CLK_AUD_CPU 0x180c +#define CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK 0x1810 +#define CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG 0x1814 +#define CLK_CON_DIV_DIV_CLK_AUD_DSIF 0x1818 +#define CLK_CON_DIV_DIV_CLK_AUD_FM 0x181c +#define CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY 0x1820 +#define CLK_CON_DIV_DIV_CLK_AUD_UAIF0 0x1824 +#define CLK_CON_DIV_DIV_CLK_AUD_UAIF1 0x1828 +#define CLK_CON_DIV_DIV_CLK_AUD_UAIF2 0x182c +#define CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP 0x1830 +#define CLK_CON_GAT_CLK_DISPAUD_ABOX_BCLK_UAIF0 0x2000 +#define CLK_CON_GAT_CLK_DISPAUD_ABOX_BCLK_UAIF1 0x2004 +#define CLK_CON_GAT_CLK_DISPAUD_ABOX_BCLK_UAIF2 0x2008 +#define CLK_CON_GAT_CLK_DISPAUD_CMU_PCLK 0x200c +#define CLK_CON_GAT_CLK_DISPAUD_CLK_AUD_UAIF0_CLK 0x2010 +#define CLK_CON_GAT_CLK_DISPAUD_CLK_AUD_UAIF1_CLK 0x2014 +#define CLK_CON_GAT_CLK_DISPAUD_CLK_AUD_UAIF2_CLK 0x2018 +#define CLK_CON_GAT_CLK_DISPAUD_OSCCLK_CLK 0x201c +#define CLK_CON_GAT_GOUT_DISPAUD_ABOX_ACLK 0x2020 +#define CLK_CON_GAT_GOUT_DISPAUD_ABOX_BCLK_DSIF 0x2024 +#define CLK_CON_GAT_GOUT_DISPAUD_ABOX_BCLK_SPDY 0x2028 +#define CLK_CON_GAT_GOUT_DISPAUD_ABOX_CCLK_ASB 0x202c +#define CLK_CON_GAT_GOUT_DISPAUD_ABOX_CCLK_CA7 0x2030 +#define CLK_CON_GAT_GOUT_DISPAUD_ABOX_CCLK_DBG 0x2034 +#define CLK_CON_GAT_GOUT_DISPAUD_ABOX_OSC_SPDY 0x2038 +#define CLK_CON_GAT_GOUT_DISPAUD_AXI_US_32TO128_ACLK 0x203c +#define CLK_CON_GAT_GOUT_DISPAUD_CLK_DISPAUD_AUD 0x2040 +#define CLK_CON_GAT_GOUT_DISPAUD_CLK_DISPAUD_DISP 0x2044 +#define CLK_CON_GAT_GOUT_DISPAUD_BTM_ABOX_ACLK 0x2048 +#define CLK_CON_GAT_GOUT_DISPAUD_BTM_ABOX_PCLK 0x204c +#define CLK_CON_GAT_GOUT_DISPAUD_BTM_DPU_ACLK 0x2050 +#define CLK_CON_GAT_GOUT_DISPAUD_BTM_DPU_PCLK 0x2054 +#define CLK_CON_GAT_GOUT_DISPAUD_DFTMUX_AUD_CODEC_MCLK 0x2058 +#define CLK_CON_GAT_GOUT_DISPAUD_DPU_ACLK_DECON 0x2060 +#define CLK_CON_GAT_GOUT_DISPAUD_DPU_ACLK_DMA 0x2064 +#define CLK_CON_GAT_GOUT_DISPAUD_DPU_ACLK_DPP 0x2068 +#define CLK_CON_GAT_GOUT_DISPAUD_GPIO_DISPAUD_PCLK 0x206c +#define CLK_CON_GAT_GOUT_DISPAUD_LHM_AXI_P_DISPAUD_CLK 0x2070 +#define CLK_CON_GAT_GOUT_DISPAUD_LHS_ACEL_D_DPU_CLK 0x2074 +#define CLK_CON_GAT_GOUT_DISPAUD_LHS_AXI_D_ABOX_CLK 0x2078 +#define CLK_CON_GAT_GOUT_DISPAUD_PERI_AXI_ASB_ACLKM 0x207c +#define CLK_CON_GAT_GOUT_DISPAUD_PERI_AXI_ASB_PCLK 0x2080 +#define CLK_CON_GAT_GOUT_DISPAUD_PPMU_ABOX_ACLK 0x2084 +#define CLK_CON_GAT_GOUT_DISPAUD_PPMU_ABOX_PCLK 0x2088 +#define CLK_CON_GAT_GOUT_DISPAUD_PPMU_DPU_ACLK 0x208c +#define CLK_CON_GAT_GOUT_DISPAUD_PPMU_DPU_PCLK 0x2090 +#define CLK_CON_GAT_GOUT_DISPAUD_CLK_AUD_CPU_ACLK_CLK 0x2094 +#define CLK_CON_GAT_GOUT_DISPAUD_CLK_AUD_CPU_CLKIN_CLK 0x2098 +#define CLK_CON_GAT_GOUT_DISPAUD_CLK_AUD_CPU_PCLKDBG_CLK 0x209c +#define CLK_CON_GAT_GOUT_DISPAUD_CLK_AUD_DSIF_CLK 0x20a0 +#define CLK_CON_GAT_GOUT_DISPAUD_CLK_AUD_CLK 0x20a4 +#define CLK_CON_GAT_GOUT_DISPAUD_CLK_BUSP_CLK 0x20a8 +#define CLK_CON_GAT_GOUT_DISPAUD_CLK_DISP_CLK 0x20ac +#define CLK_CON_GAT_GOUT_DISPAUD_SMMU_ABOX_CLK 0x20b0 +#define CLK_CON_GAT_GOUT_DISPAUD_SMMU_DPU_CLK 0x20b4 +#define CLK_CON_GAT_GOUT_DISPAUD_SYSREG_PCLK 0x20b8 +#define CLK_CON_GAT_GOUT_DISPAUD_WDT_AUD_PCLK 0x20bc + +static const unsigned long dispaud_clk_regs[] __initconst =3D { + PLL_LOCKTIME_PLL_AUD, + PLL_CON0_MUX_CLKCMU_DISPAUD_AUD_USER, + PLL_CON2_MUX_CLKCMU_DISPAUD_AUD_USER, + PLL_CON0_MUX_CLKCMU_DISPAUD_CPU_USER, + PLL_CON2_MUX_CLKCMU_DISPAUD_CPU_USER, + PLL_CON0_MUX_CLKCMU_DISPAUD_DISP_USER, + PLL_CON2_MUX_CLKCMU_DISPAUD_DISP_USER, + PLL_CON0_PLL_AUD, + PLL_CON3_PLL_AUD, + CLK_CON_MUX_MUX_CLK_AUD_BUS, + CLK_CON_MUX_MUX_CLK_AUD_CPU, + CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH, + CLK_CON_MUX_MUX_CLK_AUD_FM, + CLK_CON_MUX_MUX_CLK_AUD_UAIF0, + CLK_CON_MUX_MUX_CLK_AUD_UAIF1, + CLK_CON_MUX_MUX_CLK_AUD_UAIF2, + CLK_CON_DIV_DIV_CLK_AUD_AUDIF, + CLK_CON_DIV_DIV_CLK_AUD_BUS, + CLK_CON_DIV_DIV_CLK_AUD_CPU, + CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, + CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, + CLK_CON_DIV_DIV_CLK_AUD_DSIF, + CLK_CON_DIV_DIV_CLK_AUD_FM, + CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, + CLK_CON_DIV_DIV_CLK_AUD_UAIF0, + CLK_CON_DIV_DIV_CLK_AUD_UAIF1, + CLK_CON_DIV_DIV_CLK_AUD_UAIF2, + CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP, + CLK_CON_GAT_CLK_DISPAUD_ABOX_BCLK_UAIF0, + CLK_CON_GAT_CLK_DISPAUD_ABOX_BCLK_UAIF1, + CLK_CON_GAT_CLK_DISPAUD_ABOX_BCLK_UAIF2, + CLK_CON_GAT_CLK_DISPAUD_CMU_PCLK, + CLK_CON_GAT_CLK_DISPAUD_CLK_AUD_UAIF0_CLK, + CLK_CON_GAT_CLK_DISPAUD_CLK_AUD_UAIF1_CLK, + CLK_CON_GAT_CLK_DISPAUD_CLK_AUD_UAIF2_CLK, + CLK_CON_GAT_CLK_DISPAUD_OSCCLK_CLK, + CLK_CON_GAT_GOUT_DISPAUD_ABOX_ACLK, + CLK_CON_GAT_GOUT_DISPAUD_ABOX_BCLK_DSIF, + CLK_CON_GAT_GOUT_DISPAUD_ABOX_BCLK_SPDY, + CLK_CON_GAT_GOUT_DISPAUD_ABOX_CCLK_ASB, + CLK_CON_GAT_GOUT_DISPAUD_ABOX_CCLK_CA7, + CLK_CON_GAT_GOUT_DISPAUD_ABOX_CCLK_DBG, + CLK_CON_GAT_GOUT_DISPAUD_ABOX_OSC_SPDY, + CLK_CON_GAT_GOUT_DISPAUD_AXI_US_32TO128_ACLK, + CLK_CON_GAT_GOUT_DISPAUD_CLK_DISPAUD_AUD, + CLK_CON_GAT_GOUT_DISPAUD_CLK_DISPAUD_DISP, + CLK_CON_GAT_GOUT_DISPAUD_BTM_ABOX_ACLK, + CLK_CON_GAT_GOUT_DISPAUD_BTM_ABOX_PCLK, + CLK_CON_GAT_GOUT_DISPAUD_BTM_DPU_ACLK, + CLK_CON_GAT_GOUT_DISPAUD_BTM_DPU_PCLK, + CLK_CON_GAT_GOUT_DISPAUD_DFTMUX_AUD_CODEC_MCLK, + CLK_CON_GAT_GOUT_DISPAUD_DPU_ACLK_DECON, + CLK_CON_GAT_GOUT_DISPAUD_DPU_ACLK_DMA, + CLK_CON_GAT_GOUT_DISPAUD_DPU_ACLK_DPP, + CLK_CON_GAT_GOUT_DISPAUD_GPIO_DISPAUD_PCLK, + CLK_CON_GAT_GOUT_DISPAUD_LHM_AXI_P_DISPAUD_CLK, + CLK_CON_GAT_GOUT_DISPAUD_LHS_ACEL_D_DPU_CLK, + CLK_CON_GAT_GOUT_DISPAUD_LHS_AXI_D_ABOX_CLK, + CLK_CON_GAT_GOUT_DISPAUD_PERI_AXI_ASB_ACLKM, + CLK_CON_GAT_GOUT_DISPAUD_PERI_AXI_ASB_PCLK, + CLK_CON_GAT_GOUT_DISPAUD_PPMU_ABOX_ACLK, + CLK_CON_GAT_GOUT_DISPAUD_PPMU_ABOX_PCLK, + CLK_CON_GAT_GOUT_DISPAUD_PPMU_DPU_ACLK, + CLK_CON_GAT_GOUT_DISPAUD_PPMU_DPU_PCLK, + CLK_CON_GAT_GOUT_DISPAUD_CLK_AUD_CPU_ACLK_CLK, + CLK_CON_GAT_GOUT_DISPAUD_CLK_AUD_CPU_CLKIN_CLK, + CLK_CON_GAT_GOUT_DISPAUD_CLK_AUD_CPU_PCLKDBG_CLK, + CLK_CON_GAT_GOUT_DISPAUD_CLK_AUD_DSIF_CLK, + CLK_CON_GAT_GOUT_DISPAUD_CLK_AUD_CLK, + CLK_CON_GAT_GOUT_DISPAUD_CLK_BUSP_CLK, + CLK_CON_GAT_GOUT_DISPAUD_CLK_DISP_CLK, + CLK_CON_GAT_GOUT_DISPAUD_SMMU_ABOX_CLK, + CLK_CON_GAT_GOUT_DISPAUD_SMMU_DPU_CLK, + CLK_CON_GAT_GOUT_DISPAUD_SYSREG_PCLK, + CLK_CON_GAT_GOUT_DISPAUD_WDT_AUD_PCLK, +}; + +static const struct samsung_pll_rate_table pll_aud_rate_table[] __initcons= t =3D { + PLL_36XX_RATE(26 * MHZ, 1179648040, 45, 1, 0, 24319), + PLL_36XX_RATE(26 * MHZ, 1083801605, 42, 1, 0, -20665), +}; + +static const struct samsung_pll_clock dispaud_pll_clks[] __initconst =3D { + PLL(pll_1061x, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk", + PLL_LOCKTIME_PLL_AUD, PLL_CON0_PLL_AUD, pll_aud_rate_table), +}; + +PNAME(mout_pll_dispaud_aud_user_p) =3D { "oscclk", + "dout_cmu_dispaud_aud" }; +PNAME(mout_pll_dispaud_cpu_user_p) =3D { "oscclk", + "dout_cmu_dispaud_cpu" }; +PNAME(mout_pll_dispaud_disp_user_p) =3D { "oscclk", + "dout_cmu_dispaud_disp" }; +PNAME(mout_clk_aud_bus_p) =3D { "dout_clk_aud_bus", + "mout_pll_dispaud_aud_user" }; +PNAME(mout_clk_aud_cpu_p) =3D { "dout_clk_aud_cpu", + "mout_pll_dispaud_cpu_user" }; +PNAME(mout_clk_aud_cpu_hch_p) =3D { "mout_clk_aud_cpu", "oscclk" }; +PNAME(mout_clk_aud_fm_p) =3D { "oscclk", + "dout_clk_aud_fm_spdy" }; +PNAME(mout_clk_aud_uaif0_p) =3D { "dout_clk_aud_uaif0", + "ioclk_audiocdclk0" }; +PNAME(mout_clk_aud_uaif1_p) =3D { "dout_clk_aud_uaif1", + "ioclk_audiocdclk1" }; +PNAME(mout_clk_aud_uaif2_p) =3D { "dout_clk_aud_uaif2", + "ioclk_audiocdclk0" }; + +static const struct samsung_mux_clock dispaud_mux_clks[] __initconst =3D { + MUX(CLK_MOUT_PLL_DISPAUD_AUD_USER, "mout_pll_dispaud_aud_user", mout_pll_= dispaud_aud_user_p, + PLL_CON0_MUX_CLKCMU_DISPAUD_AUD_USER, 4, 1), + MUX(CLK_MOUT_PLL_DISPAUD_CPU_USER, "mout_pll_dispaud_cpu_user", mout_pll_= dispaud_cpu_user_p, + PLL_CON0_MUX_CLKCMU_DISPAUD_CPU_USER, 4, 1), + MUX(CLK_MOUT_PLL_DISPAUD_DISP_USER, "mout_pll_dispaud_disp_user", + mout_pll_dispaud_disp_user_p, PLL_CON0_MUX_CLKCMU_DISPAUD_DISP_USER, = 4, 1), + MUX(CLK_MOUT_CLK_AUD_BUS, "mout_clk_aud_bus", mout_clk_aud_bus_p, + CLK_CON_MUX_MUX_CLK_AUD_BUS, 0, 1), + MUX(CLK_MOUT_CLK_AUD_CPU, "mout_clk_aud_cpu", mout_clk_aud_cpu_p, + CLK_CON_MUX_MUX_CLK_AUD_CPU, 0, 1), + MUX(CLK_MOUT_CLK_AUD_CPU_HCH, "mout_clk_aud_cpu_hch", mout_clk_aud_cpu_hc= h_p, + CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH, 0, 1), + MUX(CLK_MOUT_CLK_AUD_FM, "mout_clk_aud_fm", mout_clk_aud_fm_p, + CLK_CON_MUX_MUX_CLK_AUD_FM, 0, 1), + MUX(CLK_MOUT_CLK_AUD_UAIF0, "mout_clk_aud_uaif0", mout_clk_aud_uaif0_p, + CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 0, 1), + MUX(CLK_MOUT_CLK_AUD_UAIF1, "mout_clk_aud_uaif1", mout_clk_aud_uaif1_p, + CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 0, 1), + MUX(CLK_MOUT_CLK_AUD_UAIF2, "mout_clk_aud_uaif2", mout_clk_aud_uaif2_p, + CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 0, 1), +}; + +static const struct samsung_div_clock dispaud_div_clks[] __initconst =3D { + DIV(CLK_DOUT_CLK_AUD_AUDIF, "dout_clk_aud_audif", "fout_aud_pll", + CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 0, 9), + DIV(CLK_DOUT_CLK_AUD_BUS, "dout_clk_aud_bus", "fout_aud_pll", + CLK_CON_DIV_DIV_CLK_AUD_BUS, 0, 3), + DIV(CLK_DOUT_CLK_AUD_CPU, "dout_clk_aud_cpu", "fout_aud_pll", + CLK_CON_DIV_DIV_CLK_AUD_CPU, 0, 4), + DIV(CLK_DOUT_CLK_AUD_CPU_ACLK, "dout_clk_aud_cpu_aclk", "mout_clk_aud_cpu= _hch", + CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 0, 3), + DIV(CLK_DOUT_CLK_AUD_CPU_PCLKDBG, "dout_clk_aud_cpu_pclkdbg", "mout_clk_a= ud_cpu_hch", + CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 0, 3), + DIV(CLK_DOUT_CLK_AUD_DSIF, "dout_clk_aud_dsif", "dout_clk_aud_audif", + CLK_CON_DIV_DIV_CLK_AUD_DSIF, 0, 9), + DIV(CLK_DOUT_CLK_AUD_FM, "dout_clk_aud_fm", "mout_clk_aud_fm", + CLK_CON_DIV_DIV_CLK_AUD_FM, 0, 9), + DIV(CLK_DOUT_CLK_AUD_FM_SPDY, "dout_clk_aud_fm_spdy", "tick_usb", + CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, 0, 9), + DIV(CLK_DOUT_CLK_AUD_UAIF0, "dout_clk_aud_uaif0", "dout_clk_aud_audif", + CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 0, 9), + DIV(CLK_DOUT_CLK_AUD_UAIF1, "dout_clk_aud_uaif1", "dout_clk_aud_audif", + CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 0, 9), + DIV(CLK_DOUT_CLK_AUD_UAIF2, "dout_clk_aud_uaif2", "dout_clk_aud_audif", + CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 0, 9), + DIV(CLK_DOUT_CLK_DISPAUD_BUSP, "dout_clk_dispaud_busp", "mout_pll_dispaud= _disp_user", + CLK_CON_DIV_DIV_CLK_DISPAUD_BUSP, 0, 3), +}; + +static const struct samsung_gate_clock dispaud_gate_clks[] __initconst =3D= { + GATE(CLK_GOUT_CLK_DISPAUD_ABOX_BCLK_UAIF0, "gout_clk_dispaud_abox_bclk_ua= if0", + "mout_clk_aud_uaif0", CLK_CON_GAT_CLK_DISPAUD_ABOX_BCLK_UAIF0, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CLK_DISPAUD_ABOX_BCLK_UAIF1, "gout_clk_dispaud_abox_bclk_ua= if1", + "mout_clk_aud_uaif1", CLK_CON_GAT_CLK_DISPAUD_ABOX_BCLK_UAIF1, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CLK_DISPAUD_ABOX_BCLK_UAIF2, "gout_clk_dispaud_abox_bclk_ua= if2", + "mout_clk_aud_uaif2", CLK_CON_GAT_CLK_DISPAUD_ABOX_BCLK_UAIF2, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CLK_DISPAUD_CMU_PCLK, "gout_clk_dispaud_cmu_pclk", + "dout_clk_dispaud_busp", CLK_CON_GAT_CLK_DISPAUD_CMU_PCLK, 21, CLK_I= GNORE_UNUSED, 0), + GATE(CLK_GOUT_CLK_DISPAUD_CLK_AUD_UAIF0_CLK, "gout_clk_dispaud_clk_aud_ua= if0_clk", + "mout_clk_aud_uaif0", CLK_CON_GAT_CLK_DISPAUD_CLK_AUD_UAIF0_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CLK_DISPAUD_CLK_AUD_UAIF1_CLK, "gout_clk_dispaud_clk_aud_ua= if1_clk", + "mout_clk_aud_uaif1", CLK_CON_GAT_CLK_DISPAUD_CLK_AUD_UAIF1_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CLK_DISPAUD_CLK_AUD_UAIF2_CLK, "gout_clk_dispaud_clk_aud_ua= if2_clk", + "mout_clk_aud_uaif2", CLK_CON_GAT_CLK_DISPAUD_CLK_AUD_UAIF2_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CLK_DISPAUD_OSCCLK_CLK, "gout_clk_dispaud_oscclk_clk", "osc= clk", + CLK_CON_GAT_CLK_DISPAUD_OSCCLK_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_ABOX_ACLK, "gout_clk_dispaud_abox_aclk", "mout_clk_= aud_bus", + CLK_CON_GAT_GOUT_DISPAUD_ABOX_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_ABOX_BCLK_DSIF, "gout_clk_dispaud_abox_bclk_dsif", + "dout_clk_aud_dsif", CLK_CON_GAT_GOUT_DISPAUD_ABOX_BCLK_DSIF, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_ABOX_BCLK_SPDY, "gout_clk_dispaud_abox_bclk_spdy", + "dout_clk_aud_fm", CLK_CON_GAT_GOUT_DISPAUD_ABOX_BCLK_SPDY, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_ABOX_CCLK_ASB, "gout_clk_dispaud_abox_cclk_asb", + "dout_clk_aud_cpu_aclk", CLK_CON_GAT_GOUT_DISPAUD_ABOX_CCLK_ASB, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_ABOX_CCLK_CA7, "gout_clk_dispaud_abox_cclk_ca7", + "mout_clk_aud_cpu_hch", CLK_CON_GAT_GOUT_DISPAUD_ABOX_CCLK_CA7, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_ABOX_CCLK_DBG, "gout_clk_dispaud_abox_cclk_dbg", + "dout_clk_aud_cpu_pclkdbg", CLK_CON_GAT_GOUT_DISPAUD_ABOX_CCLK_DBG, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_ABOX_OSC_SPDY, "gout_clk_dispaud_abox_osc_spdy", + "mout_clk_aud_fm", CLK_CON_GAT_GOUT_DISPAUD_ABOX_OSC_SPDY, 21, CLK_I= GNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_AXI_US_32TO128_ACLK, "gout_dispaud_axi_us_32to128_a= clk", + "mout_clk_aud_bus", CLK_CON_GAT_GOUT_DISPAUD_AXI_US_32TO128_ACLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_CLK_DISPAUD_AUD, "gout_dispaud_clk_dispaud_aud", + "mout_clk_aud_bus", CLK_CON_GAT_GOUT_DISPAUD_CLK_DISPAUD_AUD, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_CLK_DISPAUD_DISP, "gout_dispaud_clk_dispaud_disp", + "mout_pll_dispaud_disp_user", CLK_CON_GAT_GOUT_DISPAUD_CLK_DISPAUD_D= ISP, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_BTM_ABOX_ACLK, "gout_dispaud_btm_abox_aclk", "mout_= clk_aud_bus", + CLK_CON_GAT_GOUT_DISPAUD_BTM_ABOX_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_BTM_ABOX_PCLK, "gout_dispaud_btm_abox_pclk", + "dout_clk_dispaud_busp", CLK_CON_GAT_GOUT_DISPAUD_BTM_ABOX_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_BTM_DPU_ACLK, "gout_dispaud_btm_dpu_aclk", + "mout_cmu_dispaud_disp_user", CLK_CON_GAT_GOUT_DISPAUD_BTM_DPU_ACLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_BTM_DPU_PCLK, "gout_dispaud_btm_dpu_pclk", + "dout_clk_dispaud_busp", CLK_CON_GAT_GOUT_DISPAUD_BTM_DPU_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_DFTMUX_AUD_CODEC_MCLK, "gout_dispaud_dftmux_aud_cod= ec_mclk", + "dout_clk_aud_audif", CLK_CON_GAT_GOUT_DISPAUD_DFTMUX_AUD_CODEC_MCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_DPU_ACLK_DECON, "gout_dispaud_dpu_aclk_decon", + "mout_pll_dispaud_disp_user", CLK_CON_GAT_GOUT_DISPAUD_DPU_ACLK_DECO= N, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_DPU_ACLK_DMA, "gout_dispaud_dpu_aclk_dma", + "mout_pll_dispaud_disp_user", CLK_CON_GAT_GOUT_DISPAUD_DPU_ACLK_DMA, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_DPU_ACLK_DPP, "gout_dispaud_dpu_aclk_dpp", + "mout_pll_dispaud_disp_user", CLK_CON_GAT_GOUT_DISPAUD_DPU_ACLK_DPP, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_GPIO_DISPAUD_PCLK, "gout_dispaud_gpio_dispaud_pclk", + "mout_clk_aud_bus", CLK_CON_GAT_GOUT_DISPAUD_GPIO_DISPAUD_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_DISPAUD_LHM_AXI_P_DISPAUD_CLK, "gout_dispaud_lhm_axi_p_disp= aud_clk", + "mout_clk_aud_bus", CLK_CON_GAT_GOUT_DISPAUD_LHM_AXI_P_DISPAUD_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_LHS_ACEL_D_DPU_CLK, "gout_dispaud_lhs_acel_d_dpu_cl= k", + "mout_cmu_dispaud_disp_user", CLK_CON_GAT_GOUT_DISPAUD_LHS_ACEL_D_DP= U_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_LHS_AXI_D_ABOX_CLK, "gout_dispaud_lhs_axi_d_abox_cl= k", + "mout_clk_aud_bus", CLK_CON_GAT_GOUT_DISPAUD_LHS_AXI_D_ABOX_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_PERI_AXI_ASB_ACLKM, "gout_dispaud_peri_axi_asb_aclk= m", + "mout_clk_aud_bus", CLK_CON_GAT_GOUT_DISPAUD_PERI_AXI_ASB_ACLKM, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_PERI_AXI_ASB_PCLK, "gout_dispaud_peri_axi_asb_pclk", + "mout_clk_aud_bus", CLK_CON_GAT_GOUT_DISPAUD_PERI_AXI_ASB_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_PPMU_ABOX_ACLK, "gout_dispaud_ppmu_abox_aclk", + "mout_clk_aud_bus", CLK_CON_GAT_GOUT_DISPAUD_PPMU_ABOX_ACLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_PPMU_ABOX_PCLK, "gout_dispaud_ppmu_abox_pclk", + "mout_clk_aud_bus", CLK_CON_GAT_GOUT_DISPAUD_PPMU_ABOX_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_PPMU_DPU_ACLK, "gout_dispaud_ppmu_dpu_aclk", + "mout_cmu_dispaud_disp_user", CLK_CON_GAT_GOUT_DISPAUD_PPMU_DPU_ACLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_PPMU_DPU_PCLK, "gout_dispaud_ppmu_dpu_pclk", + "dout_clk_dispaud_busp", CLK_CON_GAT_GOUT_DISPAUD_PPMU_DPU_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_CLK_AUD_CPU_ACLK_CLK, + "gout_dispaud_clk_aud_cpu_aclk_clk", "dout_clk_aud_cpu_aclk", + CLK_CON_GAT_GOUT_DISPAUD_CLK_AUD_CPU_ACLK_CLK, 21, CLK_IGNORE_UNUSED= , 0), + GATE(CLK_GOUT_DISPAUD_CLK_AUD_CPU_CLKIN_CLK, + "gout_dispaud_clk_aud_cpu_clkin_clk", "mout_clk_aud_cpu_hch", + CLK_CON_GAT_GOUT_DISPAUD_CLK_AUD_CPU_CLKIN_CLK, 21, CLK_IGNORE_UNUSE= D, 0), + GATE(CLK_GOUT_DISPAUD_CLK_AUD_CPU_PCLKDBG_CLK, + "gout_dispaud_clk_aud_cpu_pclkdbg_clk", "dout_clk_aud_cpu_pclkdbg", + CLK_CON_GAT_GOUT_DISPAUD_CLK_AUD_CPU_PCLKDBG_CLK, 21, CLK_IGNORE_UNU= SED, 0), + GATE(CLK_GOUT_DISPAUD_CLK_AUD_DSIF_CLK, "gout_dispaud_clk_aud_dsif_clk", + "dout_clk_aud_dsif", CLK_CON_GAT_GOUT_DISPAUD_CLK_AUD_DSIF_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_CLK_AUD_CLK, "gout_dispaud_clk_aud_clk", + "mout_clk_aud_bus", CLK_CON_GAT_GOUT_DISPAUD_CLK_AUD_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_CLK_BUSP_CLK, "gout_dispaud_clk_busp_clk", + "dout_clk_dispaud_busp", CLK_CON_GAT_GOUT_DISPAUD_CLK_BUSP_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_CLK_DISP_CLK, "gout_dispaud_clk_disp_clk", + "mout_cmu_dispaud_disp_user", CLK_CON_GAT_GOUT_DISPAUD_CLK_DISP_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_SMMU_ABOX_CLK, "gout_dispaud_smmu_abox_clk", + "mout_clk_aud_bus", CLK_CON_GAT_GOUT_DISPAUD_SMMU_ABOX_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_SMMU_DPU_CLK, "gout_dispaud_smmu_dpu_clk", + "mout_cmu_dispaud_disp_user", CLK_CON_GAT_GOUT_DISPAUD_SMMU_DPU_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_DISPAUD_SYSREG_PCLK, "gout_dispaud_sysreg_pclk", + "dout_clk_dispaud_busp", CLK_CON_GAT_GOUT_DISPAUD_SYSREG_PCLK, + 21, 0, 0), + GATE(CLK_GOUT_DISPAUD_WDT_AUD_PCLK, "gout_dispaud_wdt_aud_pclk", + "mout_clk_aud_bus", CLK_CON_GAT_GOUT_DISPAUD_WDT_AUD_PCLK, + 21, CLK_IGNORE_UNUSED, 0), +}; + +static const struct samsung_cmu_info dispaud_cmu_info __initconst =3D { + .pll_clks =3D dispaud_pll_clks, + .nr_pll_clks =3D ARRAY_SIZE(dispaud_pll_clks), + .mux_clks =3D dispaud_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(dispaud_mux_clks), + .div_clks =3D dispaud_div_clks, + .nr_div_clks =3D ARRAY_SIZE(dispaud_div_clks), + .gate_clks =3D dispaud_gate_clks, + .nr_gate_clks =3D ARRAY_SIZE(dispaud_gate_clks), + .nr_clk_ids =3D CLKS_NR_DISPAUD, + .clk_regs =3D dispaud_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(dispaud_clk_regs), +}; + +/* CMU_FSYS */ +#define PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER 0x0100 +#define PLL_CON2_MUX_CLKCMU_FSYS_BUS_USER 0x0108 +#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER 0x0120 +#define PLL_CON2_MUX_CLKCMU_FSYS_MMC_CARD_USER 0x0128 +#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER 0x0140 +#define PLL_CON2_MUX_CLKCMU_FSYS_MMC_EMBD_USER 0x0148 +#define PLL_CON0_MUX_CLKCMU_FSYS_UFS_EMBD_USER 0x0160 +#define PLL_CON2_MUX_CLKCMU_FSYS_UFS_EMBD_USER 0x0168 +#define CLK_CON_GAT_CLK_FSYS_CMU_PCLK 0x2000 +#define CLK_CON_GAT_CLK_FSYS_OSCCLK_CLK 0x2004 +#define CLK_CON_GAT_GOUT_FSYS_ADM_AHB_SSS_HCLKM 0x2008 +#define CLK_CON_GAT_GOUT_FSYS_BTM_ACLK 0x200c +#define CLK_CON_GAT_GOUT_FSYS_BTM_PCLK 0x2010 +#define CLK_CON_GAT_GOUT_FSYS_GPIO_PCLK 0x2014 +#define CLK_CON_GAT_GOUT_FSYS_LHM_AXI_P_CLK 0x2018 +#define CLK_CON_GAT_GOUT_FSYS_LHS_ACEL_D_CLK 0x201c +#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_ACLK 0x2020 +#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN 0x2024 +#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_ACLK 0x2028 +#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN 0x202c +#define CLK_CON_GAT_GOUT_FSYS_PGEN_LITE_CLK 0x2030 +#define CLK_CON_GAT_GOUT_FSYS_PPMU_ACLK 0x2034 +#define CLK_CON_GAT_GOUT_FSYS_PPMU_PCLK 0x2038 +#define CLK_CON_GAT_GOUT_FSYS_BUS_CLK 0x203c +#define CLK_CON_GAT_GOUT_FSYS_RTIC_ACLK 0x2040 +#define CLK_CON_GAT_GOUT_FSYS_RTIC_PCLK 0x2044 +#define CLK_CON_GAT_GOUT_FSYS_SSS_ACLK 0x2048 +#define CLK_CON_GAT_GOUT_FSYS_SSS_PCLK 0x204c +#define CLK_CON_GAT_GOUT_FSYS_SYSREG_PCLK 0x2050 +#define CLK_CON_GAT_GOUT_FSYS_UFS_EMBD_ACLK 0x2054 +#define CLK_CON_GAT_GOUT_FSYS_UFS_EMBD_CLK_UNIPRO 0x2058 +#define CLK_CON_GAT_GOUT_FSYS_UFS_EMBD_FMP_CLK 0x205c +#define CLK_CON_GAT_GOUT_FSYS_XIU_D_ACLK 0x2060 + +static const unsigned long fsys_clk_regs[] __initconst =3D { + PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER, + PLL_CON2_MUX_CLKCMU_FSYS_BUS_USER, + PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER, + PLL_CON2_MUX_CLKCMU_FSYS_MMC_CARD_USER, + PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER, + PLL_CON2_MUX_CLKCMU_FSYS_MMC_EMBD_USER, + PLL_CON0_MUX_CLKCMU_FSYS_UFS_EMBD_USER, + PLL_CON2_MUX_CLKCMU_FSYS_UFS_EMBD_USER, + CLK_CON_GAT_CLK_FSYS_CMU_PCLK, + CLK_CON_GAT_CLK_FSYS_OSCCLK_CLK, + CLK_CON_GAT_GOUT_FSYS_ADM_AHB_SSS_HCLKM, + CLK_CON_GAT_GOUT_FSYS_BTM_ACLK, + CLK_CON_GAT_GOUT_FSYS_BTM_PCLK, + CLK_CON_GAT_GOUT_FSYS_GPIO_PCLK, + CLK_CON_GAT_GOUT_FSYS_LHM_AXI_P_CLK, + CLK_CON_GAT_GOUT_FSYS_LHS_ACEL_D_CLK, + CLK_CON_GAT_GOUT_FSYS_MMC_CARD_ACLK, + CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_ACLK, + CLK_CON_GAT_GOUT_FSYS_PGEN_LITE_CLK, + CLK_CON_GAT_GOUT_FSYS_PPMU_ACLK, + CLK_CON_GAT_GOUT_FSYS_PPMU_PCLK, + CLK_CON_GAT_GOUT_FSYS_BUS_CLK, + CLK_CON_GAT_GOUT_FSYS_SYSREG_PCLK, + CLK_CON_GAT_GOUT_FSYS_UFS_EMBD_ACLK, + CLK_CON_GAT_GOUT_FSYS_UFS_EMBD_FMP_CLK, + CLK_CON_GAT_GOUT_FSYS_XIU_D_ACLK, +}; + +PNAME(mout_pll_fsys_bus_user_p) =3D { "oscclk", + "dout_cmu_fsys_bus" }; +PNAME(mout_pll_fsys_mmc_card_user_p) =3D { "oscclk", + "dout_cmu_fsys_mmc_card" }; +PNAME(mout_pll_fsys_mmc_embd_user_p) =3D { "oscclk", + "dout_cmu_fsys_mmc_embd" }; +PNAME(mout_pll_fsys_ufs_embd_user_p) =3D { "oscclk", + "dout_cmu_fsys_ufs_embd" }; + +static const struct samsung_mux_clock fsys_mux_clks[] __initconst =3D { + MUX(CLK_MOUT_PLL_FSYS_BUS_USER, "mout_pll_fsys_bus_user", mout_pll_fsys_b= us_user_p, + PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER, 4, 1), + MUX(CLK_MOUT_PLL_FSYS_MMC_CARD_USER, "mout_pll_fsys_mmc_card_user", + mout_pll_fsys_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER= , 4, 1), + MUX(CLK_MOUT_PLL_FSYS_MMC_EMBD_USER, "mout_pll_fsys_mmc_embd_user", + mout_pll_fsys_mmc_embd_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER= , 4, 1), + MUX(CLK_MOUT_PLL_FSYS_UFS_EMBD_USER, "mout_pll_fsys_ufs_embd_user", + mout_pll_fsys_ufs_embd_user_p, PLL_CON0_MUX_CLKCMU_FSYS_UFS_EMBD_USER= , 4, 1), +}; + +static const struct samsung_gate_clock fsys_gate_clks[] __initconst =3D { + GATE(CLK_GOUT_FSYS_CMU_PCLK, "gout_fsys_cmu_pclk", "mout_pll_fsys_bus_use= r", + CLK_CON_GAT_CLK_FSYS_CMU_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_FSYS_OSCCLK_CLK, "gout_fsys_oscclk_clk", "oscclk", + CLK_CON_GAT_CLK_FSYS_OSCCLK_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_FSYS_ADM_AHB_SSS_HCLKM, "gout_fsys_adm_ahb_sss_hclkm", + "mout_pll_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_ADM_AHB_SSS_HCLKM, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_FSYS_BTM_ACLK, "gout_fsys_btm_aclk", "mout_pll_fsys_bus_use= r", + CLK_CON_GAT_GOUT_FSYS_BTM_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_FSYS_BTM_PCLK, "gout_fsys_btm_pclk", "mout_pll_fsys_bus_use= r", + CLK_CON_GAT_GOUT_FSYS_BTM_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_FSYS_GPIO_PCLK, "gout_fsys_gpio_pclk", "mout_pll_fsys_bus_u= ser", + CLK_CON_GAT_GOUT_FSYS_GPIO_PCLK, 21, 0, 0), + GATE(CLK_GOUT_FSYS_LHM_AXI_P_CLK, "gout_fsys_lhm_axi_p_clk", + "mout_pll_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_LHM_AXI_P_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_FSYS_LHS_ACEL_D_CLK, "gout_fsys_lhs_acel_d_clk", + "mout_pll_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_LHS_ACEL_D_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_FSYS_MMC_CARD_ACLK, "gout_fsys_mmc_card_aclk", + "mout_pll_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_MMC_CARD_ACLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_FSYS_MMC_CARD_SDCLKIN, "gout_fsys_mmc_card_sdclkin", + "mout_pll_fsys_mmc_card_user", CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKI= N, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_FSYS_MMC_EMBD_ACLK, "gout_fsys_mmc_embd_aclk", + "mout_pll_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_ACLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_FSYS_MMC_EMBD_SDCLKIN, "gout_fsys_mmc_embd_sdclkin", + "mout_pll_fsys_mmc_embd_user", CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKI= N, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_FSYS_PGEN_LITE_CLK, "gout_fsys_pgen_lite_clk", + "mout_pll_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_PGEN_LITE_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_FSYS_PPMU_ACLK, "gout_fsys_ppmu_aclk", "mout_pll_fsys_bus_u= ser", + CLK_CON_GAT_GOUT_FSYS_PPMU_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_FSYS_PPMU_PCLK, "gout_fsys_ppmu_pclk", "mout_pll_fsys_bus_u= ser", + CLK_CON_GAT_GOUT_FSYS_PPMU_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_FSYS_BUS_CLK, "gout_fsys_bus_clk", "mout_pll_fsys_bus_user", + CLK_CON_GAT_GOUT_FSYS_BUS_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_FSYS_SYSREG_PCLK, "gout_fsys_sysreg_pclk", "mout_pll_fsys_b= us_user", + CLK_CON_GAT_GOUT_FSYS_SYSREG_PCLK, 21, 0, 0), + GATE(CLK_GOUT_FSYS_UFS_EMBD_ACLK, "gout_fsys_ufs_embd_aclk", + "mout_pll_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_UFS_EMBD_ACLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_FSYS_UFS_EMBD_CLK_UNIPRO, "gout_fsys_ufs_embd_clk_unipro", + "mout_pll_fsys_ufs_embd_user", CLK_CON_GAT_GOUT_FSYS_UFS_EMBD_CLK_UN= IPRO, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_FSYS_UFS_EMBD_FMP_CLK, "gout_fsys_ufs_embd_fmp_clk", + "mout_pll_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_UFS_EMBD_FMP_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_FSYS_XIU_D_ACLK, "gout_fsys_xiu_d_aclk", "mout_pll_fsys_bus= _user", + CLK_CON_GAT_GOUT_FSYS_XIU_D_ACLK, 21, CLK_IGNORE_UNUSED, 0), +}; + +static const struct samsung_cmu_info fsys_cmu_info __initconst =3D { + .mux_clks =3D fsys_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(fsys_mux_clks), + .gate_clks =3D fsys_gate_clks, + .nr_gate_clks =3D ARRAY_SIZE(fsys_gate_clks), + .clk_regs =3D fsys_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(fsys_clk_regs), + .nr_clk_ids =3D CLKS_NR_FSYS, +}; + +/* CMU_G2D */ +#define PLL_CON0_MUX_CLKCMU_G2D_G2D_USER 0x0100 +#define PLL_CON2_MUX_CLKCMU_G2D_G2D_USER 0x0108 +#define PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER 0x0120 +#define PLL_CON2_MUX_CLKCMU_G2D_MSCL_USER 0x0128 +#define CLK_CON_DIV_DIV_CLK_G2D_BUSP 0x1800 +#define CLK_CON_GAT_CLK_G2D_CMU_PCLK 0x2000 +#define CLK_CON_GAT_CLK_G2D_OSCCLK_CLK 0x2004 +#define CLK_CON_GAT_GOUT_G2D_AS_AXI_JPEG_ACLKM 0x2008 +#define CLK_CON_GAT_GOUT_G2D_AS_AXI_JPEG_ACLKS 0x200c +#define CLK_CON_GAT_GOUT_G2D_AS_AXI_MSCL_ACLKM 0x2010 +#define CLK_CON_GAT_GOUT_G2D_AS_AXI_MSCL_ACLKS 0x2014 +#define CLK_CON_GAT_GOUT_G2D_CLK_G2D_G2D 0x2018 +#define CLK_CON_GAT_GOUT_G2D_CLK_G2D_MSCL 0x201c +#define CLK_CON_GAT_GOUT_G2D_BTM_G2D_ACLK 0x2020 +#define CLK_CON_GAT_GOUT_G2D_BTM_G2D_PCLK 0x2024 +#define CLK_CON_GAT_GOUT_G2D_G2D_ACLK 0x2028 +#define CLK_CON_GAT_GOUT_G2D_JPEG_FIMP_CLK 0x202c +#define CLK_CON_GAT_GOUT_G2D_LHM_AXI_P_CLK 0x2030 +#define CLK_CON_GAT_GOUT_G2D_LHS_ACEL_D_CLK 0x2034 +#define CLK_CON_GAT_GOUT_G2D_MSCL_ACLK 0x2038 +#define CLK_CON_GAT_GOUT_G2D_PGEN100_LITE_CLK 0x203c +#define CLK_CON_GAT_GOUT_G2D_PPMU_ACLK 0x2040 +#define CLK_CON_GAT_GOUT_G2D_PPMU_PCLK 0x2044 +#define CLK_CON_GAT_GOUT_G2D_BUSP_CLK 0x2048 +#define CLK_CON_GAT_GOUT_G2D_G2D_CLK 0x204c +#define CLK_CON_GAT_GOUT_G2D_MSCL_CLK 0x2050 +#define CLK_CON_GAT_GOUT_G2D_SYSMMU_CLK 0x2054 +#define CLK_CON_GAT_GOUT_G2D_SYSREG_PCLK 0x2058 +#define CLK_CON_GAT_GOUT_G2D_XIU_D_MSCL_ACLK 0x205c + +static const unsigned long g2d_clk_regs[] __initconst =3D { + PLL_CON0_MUX_CLKCMU_G2D_G2D_USER, + PLL_CON2_MUX_CLKCMU_G2D_G2D_USER, + PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER, + PLL_CON2_MUX_CLKCMU_G2D_MSCL_USER, + CLK_CON_DIV_DIV_CLK_G2D_BUSP, + CLK_CON_GAT_CLK_G2D_CMU_PCLK, + CLK_CON_GAT_CLK_G2D_OSCCLK_CLK, + CLK_CON_GAT_GOUT_G2D_AS_AXI_JPEG_ACLKM, + CLK_CON_GAT_GOUT_G2D_AS_AXI_JPEG_ACLKS, + CLK_CON_GAT_GOUT_G2D_AS_AXI_MSCL_ACLKM, + CLK_CON_GAT_GOUT_G2D_AS_AXI_MSCL_ACLKS, + CLK_CON_GAT_GOUT_G2D_CLK_G2D_G2D, + CLK_CON_GAT_GOUT_G2D_CLK_G2D_MSCL, + CLK_CON_GAT_GOUT_G2D_BTM_G2D_ACLK, + CLK_CON_GAT_GOUT_G2D_BTM_G2D_PCLK, + CLK_CON_GAT_GOUT_G2D_G2D_ACLK, + CLK_CON_GAT_GOUT_G2D_JPEG_FIMP_CLK, + CLK_CON_GAT_GOUT_G2D_LHM_AXI_P_CLK, + CLK_CON_GAT_GOUT_G2D_LHS_ACEL_D_CLK, + CLK_CON_GAT_GOUT_G2D_MSCL_ACLK, + CLK_CON_GAT_GOUT_G2D_PGEN100_LITE_CLK, + CLK_CON_GAT_GOUT_G2D_PPMU_ACLK, + CLK_CON_GAT_GOUT_G2D_PPMU_PCLK, + CLK_CON_GAT_GOUT_G2D_BUSP_CLK, + CLK_CON_GAT_GOUT_G2D_G2D_CLK, + CLK_CON_GAT_GOUT_G2D_MSCL_CLK, + // CLK_CON_GAT_GOUT_G2D_SYSMMU_CLK, // wronly + CLK_CON_GAT_GOUT_G2D_SYSREG_PCLK, + CLK_CON_GAT_GOUT_G2D_XIU_D_MSCL_ACLK, +}; + +PNAME(mout_pll_g2d_g2d_user_p) =3D { "oscclk", "dout_cmu_g2d_g2d" }; +PNAME(mout_pll_g2d_mscl_user_p) =3D { "oscclk", "dout_cmu_g2d_mscl" }; + +static const struct samsung_mux_clock g2d_mux_clks[] __initconst =3D { + MUX(CLK_MOUT_PLL_G2D_G2D_USER, "mout_pll_g2d_g2d_user", mout_pll_g2d_g2d_= user_p, + PLL_CON0_MUX_CLKCMU_G2D_G2D_USER, 4, 1), + MUX(CLK_MOUT_PLL_G2D_MSCL_USER, "mout_pll_g2d_mscl_user", mout_pll_g2d_ms= cl_user_p, + PLL_CON0_MUX_CLKCMU_G2D_MSCL_USER, 4, 1), +}; + +static const struct samsung_div_clock g2d_div_clks[] __initconst =3D { + DIV(CLK_DOUT_CLK_G2D_BUSP, "dout_clk_g2d_busp", "mout_pll_g2d_mscl_user", + CLK_CON_DIV_DIV_CLK_G2D_BUSP, 0, 3), +}; + +static const struct samsung_gate_clock g2d_gate_clks[] __initconst =3D { + GATE(CLK_GOUT_CLK_G2D_CMU_PCLK, "gout_clk_g2d_cmu_pclk", "dout_clk_g2d_bu= sp", + CLK_CON_GAT_CLK_G2D_CMU_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CLK_G2D_OSCCLK_CLK, "gout_clk_g2d_oscclk_clk", "oscclk", + CLK_CON_GAT_CLK_G2D_OSCCLK_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G2D_AS_AXI_JPEG_ACLKM, "gout_g2d_as_axi_jpeg_aclkm", + "mout_pll_g2d_g2d_user", CLK_CON_GAT_GOUT_G2D_AS_AXI_JPEG_ACLKM, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G2D_AS_AXI_JPEG_ACLKS, "gout_g2d_as_axi_jpeg_aclks", + "mout_pll_g2d_mscl_user", CLK_CON_GAT_GOUT_G2D_AS_AXI_JPEG_ACLKS, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G2D_AS_AXI_MSCL_ACLKM, "gout_g2d_as_axi_mscl_aclkm", + "mout_pll_g2d_g2d_user", CLK_CON_GAT_GOUT_G2D_AS_AXI_MSCL_ACLKM, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G2D_AS_AXI_MSCL_ACLKS, "gout_g2d_as_axi_mscl_aclks", + "mout_pll_g2d_mscl_user", CLK_CON_GAT_GOUT_G2D_AS_AXI_MSCL_ACLKS, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G2D_CLK_G2D_G2D, "gout_g2d_clk_g2d_g2d", "mout_pll_g2d_g2d_= user", + CLK_CON_GAT_GOUT_G2D_CLK_G2D_G2D, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G2D_CLK_G2D_MSCL, "gout_g2d_clk_g2d_mscl", "mout_pll_g2d_ms= cl_user", + CLK_CON_GAT_GOUT_G2D_CLK_G2D_MSCL, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G2D_BTM_G2D_ACLK, "gout_g2d_btm_g2d_aclk", "mout_pll_g2d_g2= d_user", + CLK_CON_GAT_GOUT_G2D_BTM_G2D_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G2D_BTM_G2D_PCLK, "gout_g2d_btm_g2d_pclk", "dout_clk_g2d_bu= sp", + CLK_CON_GAT_GOUT_G2D_BTM_G2D_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G2D_G2D_ACLK, "gout_g2d_g2d_aclk", "mout_pll_g2d_g2d_user", + CLK_CON_GAT_GOUT_G2D_G2D_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G2D_JPEG_FIMP_CLK, "gout_g2d_jpeg_fimp_clk", "mout_pll_g2d_= mscl_user", + CLK_CON_GAT_GOUT_G2D_JPEG_FIMP_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G2D_LHM_AXI_P_CLK, "gout_g2d_lhm_axi_p_clk", "dout_clk_g2d_= busp", + CLK_CON_GAT_GOUT_G2D_LHM_AXI_P_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G2D_LHS_ACEL_D_CLK, "gout_g2d_lhs_acel_d_clk", "mout_pll_g2= d_mscl_user", + CLK_CON_GAT_GOUT_G2D_LHS_ACEL_D_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G2D_MSCL_ACLK, "gout_g2d_mscl_aclk", "mout_pll_g2d_mscl_use= r", + CLK_CON_GAT_GOUT_G2D_MSCL_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G2D_PGEN100_LITE_CLK, "gout_g2d_pgen100_lite_clk", "dout_cl= k_g2d_busp", + CLK_CON_GAT_GOUT_G2D_PGEN100_LITE_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G2D_PPMU_ACLK, "gout_g2d_ppmu_aclk", "mout_pll_g2d_g2d_user= ", + CLK_CON_GAT_GOUT_G2D_PPMU_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G2D_PPMU_PCLK, "gout_g2d_ppmu_pclk", "dout_clk_g2d_busp", + CLK_CON_GAT_GOUT_G2D_PPMU_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G2D_BUSP_CLK, "gout_g2d_busp_clk", "dout_clk_g2d_busp", + CLK_CON_GAT_GOUT_G2D_BUSP_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G2D_SYSMMU_CLK, "gout_g2d_sysmmu_clk", "mout_pll_g2d_g2d_us= er", + CLK_CON_GAT_GOUT_G2D_SYSMMU_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G2D_SYSREG_PCLK, "gout_g2d_sysreg_pclk", "dout_clk_g2d_busp= ", + CLK_CON_GAT_GOUT_G2D_SYSREG_PCLK, 21, 0, 0), + GATE(CLK_GOUT_G2D_XIU_D_MSCL_ACLK, "gout_g2d_xiu_d_mscl_aclk", "mout_pll_= g2d_g2d_user", + CLK_CON_GAT_GOUT_G2D_XIU_D_MSCL_ACLK, 21, CLK_IGNORE_UNUSED, 0), +}; + +static const struct samsung_cmu_info g2d_cmu_info __initconst =3D { + .mux_clks =3D g2d_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(g2d_mux_clks), + .div_clks =3D g2d_div_clks, + .nr_div_clks =3D ARRAY_SIZE(g2d_div_clks), + .gate_clks =3D g2d_gate_clks, + .nr_gate_clks =3D ARRAY_SIZE(g2d_gate_clks), + .clk_regs =3D g2d_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(g2d_clk_regs), + .nr_clk_ids =3D CLKS_NR_G2D, +}; + +/* CMU_G3D */ +#define PLL_LOCKTIME_PLL_G3D 0x0000 +#define PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER 0x0100 +#define PLL_CON2_MUX_CLKCMU_G3D_SWITCH_USER 0x0108 +#define PLL_CON0_PLL_G3D 0x0120 +#define CLK_CON_MUX_MUX_CLK_G3D_BUSD 0x1004 +#define CLK_CON_DIV_DIV_CLK_G3D_BUSD 0x1800 +#define CLK_CON_DIV_DIV_CLK_G3D_BUSP 0x1804 +#define CLK_CON_GAT_CLK_G3D_CMU_PCLK 0x2000 +#define CLK_CON_GAT_CLK_G3D_G3D_CLK 0x2004 +#define CLK_CON_GAT_CLK_G3D_HPM_TARGETCLK_C 0x2008 +#define CLK_CON_GAT_CLK_G3D_OSCCLK_CLK 0x200c +#define CLK_CON_GAT_GOUT_G3D_BTM_G3D_ACLK 0x2014 +#define CLK_CON_GAT_GOUT_G3D_BTM_G3D_PCLK 0x2018 +#define CLK_CON_GAT_GOUT_G3D_BUSIF_HPMG3D_PCLK 0x201c +#define CLK_CON_GAT_GOUT_G3D_GRAY2BIN_G3D_CLK 0x2020 +#define CLK_CON_GAT_GOUT_G3D_LHM_AXI_G3DSFR_CLK 0x2024 +#define CLK_CON_GAT_GOUT_G3D_LHM_AXI_P_G3D_CLK 0x2028 +#define CLK_CON_GAT_GOUT_G3D_LHS_AXI_D_G3D_CLK 0x202c +#define CLK_CON_GAT_GOUT_G3D_LHS_AXI_G3DSFR_CLK 0x2030 +#define CLK_CON_GAT_GOUT_G3D_PGEN_LITE_G3D_CLK 0x2034 +#define CLK_CON_GAT_GOUT_G3D_BUSD_CLK 0x2038 +#define CLK_CON_GAT_GOUT_G3D_BUSP_CLK 0x203c +#define CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK 0x2040 + +static const unsigned long g3d_clk_regs[] __initconst =3D { + PLL_LOCKTIME_PLL_G3D, + PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, + PLL_CON2_MUX_CLKCMU_G3D_SWITCH_USER, + PLL_CON0_PLL_G3D, + CLK_CON_MUX_MUX_CLK_G3D_BUSD, + CLK_CON_DIV_DIV_CLK_G3D_BUSD, + CLK_CON_DIV_DIV_CLK_G3D_BUSP, + CLK_CON_GAT_CLK_G3D_CMU_PCLK, + CLK_CON_GAT_CLK_G3D_G3D_CLK, + CLK_CON_GAT_CLK_G3D_HPM_TARGETCLK_C, + CLK_CON_GAT_CLK_G3D_OSCCLK_CLK, + CLK_CON_GAT_GOUT_G3D_BTM_G3D_ACLK, + CLK_CON_GAT_GOUT_G3D_BTM_G3D_PCLK, + CLK_CON_GAT_GOUT_G3D_BUSIF_HPMG3D_PCLK, + CLK_CON_GAT_GOUT_G3D_GRAY2BIN_G3D_CLK, + CLK_CON_GAT_GOUT_G3D_LHM_AXI_G3DSFR_CLK, + CLK_CON_GAT_GOUT_G3D_LHM_AXI_P_G3D_CLK, + CLK_CON_GAT_GOUT_G3D_LHS_AXI_D_G3D_CLK, + CLK_CON_GAT_GOUT_G3D_LHS_AXI_G3DSFR_CLK, + CLK_CON_GAT_GOUT_G3D_PGEN_LITE_G3D_CLK, + CLK_CON_GAT_GOUT_G3D_BUSD_CLK, + CLK_CON_GAT_GOUT_G3D_BUSP_CLK, + CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK, +}; + +static const struct samsung_pll_rate_table pll_g3d_rate_table[] __initcons= t =3D { + PLL_35XX_RATE(26 * MHZ, 750000000, 375, 13, 0), + PLL_35XX_RATE(26 * MHZ, 1000000000, 500, 13, 0), + PLL_35XX_RATE(26 * MHZ, 1200000000, 600, 13, 0), + PLL_35XX_RATE(26 * MHZ, 330000000, 660, 13, 2), + PLL_35XX_RATE(26 * MHZ, 550000000, 550, 13, 1), +}; + +static const struct samsung_pll_clock g3d_pll_clks[] __initconst =3D { + PLL(pll_1052x, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk", + PLL_LOCKTIME_PLL_G3D, PLL_CON0_PLL_G3D, + pll_g3d_rate_table), +}; + +PNAME(mout_g3d_switch_user_p) =3D { "oscclk", "dout_cmu_g3d_switch" }; +PNAME(mout_clk_g3d_busd_p) =3D { "fout_g3d_pll", + "mout_g3d_switch_user" }; + +static const struct samsung_mux_clock g3d_mux_clks[] __initconst =3D { + MUX(CLK_MOUT_G3D_SWITCH_USER, "mout_g3d_switch_user", mout_g3d_switch_use= r_p, + PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, 4, 1), + MUX(CLK_MOUT_CLK_G3D_BUSD, "mout_clk_g3d_busd", mout_clk_g3d_busd_p, + CLK_CON_MUX_MUX_CLK_G3D_BUSD, 0, 1), +}; + +static const struct samsung_div_clock g3d_div_clks[] __initconst =3D { + DIV(CLK_DOUT_CLK_G3D_BUSD, "dout_clk_g3d_busd", "mout_clk_g3d_busd", + CLK_CON_DIV_DIV_CLK_G3D_BUSD, 0, 1), + DIV(CLK_DOUT_CLK_G3D_BUSP, "dout_clk_g3d_busp", "mout_clk_g3d_busd", + CLK_CON_DIV_DIV_CLK_G3D_BUSP, 0, 3), +}; + +static const struct samsung_gate_clock g3d_gate_clks[] __initconst =3D { + GATE(CLK_GOUT_CLK_G3D_CMU_PCLK, "gout_clk_g3d_cmu_pclk", "dout_clk_g3d_bu= sp", + CLK_CON_GAT_CLK_G3D_CMU_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CLK_G3D_G3D_CLK, "gout_clk_g3d_g3d_clk", "dout_clk_g3d_busd= ", + CLK_CON_GAT_CLK_G3D_G3D_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_CLK_G3D_HPM_TARGETCLK_C, "gout_clk_g3d_hpm_targetclk_c", + "dout_cmu_hpm", CLK_CON_GAT_CLK_G3D_HPM_TARGETCLK_C, 21, CLK_IGNORE_= UNUSED, 0), + GATE(CLK_GOUT_CLK_G3D_OSCCLK_CLK, "gout_clk_g3d_oscclk_clk", "oscclk", + CLK_CON_GAT_CLK_G3D_OSCCLK_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G3D_BTM_G3D_ACLK, "gout_g3d_btm_g3d_aclk", "dout_clk_g3d_bu= sd", + CLK_CON_GAT_GOUT_G3D_BTM_G3D_ACLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G3D_BTM_G3D_PCLK, "gout_g3d_btm_g3d_pclk", "dout_clk_g3d_bu= sp", + CLK_CON_GAT_GOUT_G3D_BTM_G3D_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G3D_BUSIF_HPMG3D_PCLK, "gout_g3d_busif_hpmg3d_pclk", + "dout_clk_g3d_busp", CLK_CON_GAT_GOUT_G3D_BUSIF_HPMG3D_PCLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G3D_GRAY2BIN_G3D_CLK, "gout_g3d_gray2bin_g3d_clk", + "dout_clk_g3d_busd", CLK_CON_GAT_GOUT_G3D_GRAY2BIN_G3D_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G3D_LHM_AXI_G3DSFR_CLK, "gout_g3d_lhm_axi_g3dsfr_clk", + "dout_clk_g3d_busd", CLK_CON_GAT_GOUT_G3D_LHM_AXI_G3DSFR_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G3D_LHM_AXI_P_G3D_CLK, "gout_g3d_lhm_axi_p_g3d_clk", + "dout_clk_g3d_busp", CLK_CON_GAT_GOUT_G3D_LHM_AXI_P_G3D_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G3D_LHS_AXI_D_G3D_CLK, "gout_g3d_lhs_axi_d_g3d_clk", + "dout_clk_g3d_busd", CLK_CON_GAT_GOUT_G3D_LHS_AXI_D_G3D_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G3D_LHS_AXI_G3DSFR_CLK, "gout_g3d_lhs_axi_g3dsfr_clk", + "dout_clk_g3d_busp", CLK_CON_GAT_GOUT_G3D_LHS_AXI_G3DSFR_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G3D_PGEN_LITE_G3D_CLK, "gout_g3d_pgen_lite_g3d_clk", + "dout_clk_g3d_busp", CLK_CON_GAT_GOUT_G3D_PGEN_LITE_G3D_CLK, + 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G3D_BUSD_CLK, "gout_g3d_busd_clk", "dout_clk_g3d_busd", + CLK_CON_GAT_GOUT_G3D_BUSD_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G3D_BUSP_CLK, "gout_g3d_busp_clk", "dout_clk_g3d_busp", + CLK_CON_GAT_GOUT_G3D_BUSP_CLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G3D_SYSREG_PCLK, "gout_g3d_sysreg_pclk", "dout_clk_g3d_busp= ", + CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK, 21, 0, 0), +}; + +static const struct samsung_cmu_info g3d_cmu_info __initconst =3D { + .pll_clks =3D g3d_pll_clks, + .nr_pll_clks =3D ARRAY_SIZE(g3d_pll_clks), + .mux_clks =3D g3d_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(g3d_mux_clks), + .div_clks =3D g3d_div_clks, + .nr_div_clks =3D ARRAY_SIZE(g3d_div_clks), + .gate_clks =3D g3d_gate_clks, + .nr_gate_clks =3D ARRAY_SIZE(g3d_gate_clks), + .clk_regs =3D g3d_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(g3d_clk_regs), + .nr_clk_ids =3D CLKS_NR_G3D, +}; + +static int __init exynos9610_cmu_probe(struct platform_device *pdev) +{ + const struct samsung_cmu_info *info; + struct device *dev =3D &pdev->dev; + + info =3D of_device_get_match_data(dev); + exynos_arm64_register_cmu(dev, dev->of_node, info); + + return 0; +} + +static const struct of_device_id exynos9610_cmu_of_match[] =3D { + { + .compatible =3D "samsung,exynos9610-cmu-cam", + .data =3D &cam_cmu_info, + }, + { + .compatible =3D "samsung,exynos9610-cmu-cmgp", + .data =3D &cmgp_cmu_info, + }, + { + .compatible =3D "samsung,exynos9610-cmu-core", + .data =3D &core_cmu_info, + }, + { + .compatible =3D "samsung,exynos9610-cmu-dispaud", + .data =3D &dispaud_cmu_info, + }, + { + .compatible =3D "samsung,exynos9610-cmu-fsys", + .data =3D &fsys_cmu_info, + }, + { + .compatible =3D "samsung,exynos9610-cmu-g2d", + .data =3D &g2d_cmu_info, + }, + { + .compatible =3D "samsung,exynos9610-cmu-g3d", + .data =3D &g3d_cmu_info, + }, + { } +}; + +static struct platform_driver exynos9610_cmu_driver __refdata =3D { + .driver =3D { + .name =3D "exynos9610-cmu", + .of_match_table =3D exynos9610_cmu_of_match, + .suppress_bind_attrs =3D true, + }, + .probe =3D exynos9610_cmu_probe, +}; + +static int __init exynos9610_cmu_init(void) +{ + return platform_driver_register(&exynos9610_cmu_driver); +} +core_initcall(exynos9610_cmu_init); --=20 2.47.3 From nobody Thu Oct 2 16:35:37 2025 Received: from mail-4317.protonmail.ch (mail-4317.protonmail.ch [185.70.43.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 356A62E717C; Sun, 14 Sep 2025 21:20:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757884809; cv=none; b=toQzo2KvOLA+BFJcsD1D8D8h/ueE0FMoq2WMSR3xUe1/+NsViOtUSz0v614HlmsZZSaLCsZeF3l2lLS5wzY+aAJ6N9RXC8f7dORnazSvpclByjpCk7qjNN459hMchd/nPNl7TRiTbHj19nOQt9fu2rtABTvlT3+KahVqWs7eLVc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757884809; c=relaxed/simple; bh=9xBHetlyUrobi2XPbkzo7wzDxeEYes8wkO71U/Sqz5A=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=WyrXMepzl9w5E8qEkZdoebK9VENPCw7JOx761v0x487peK4RTgWqe5pqt45wtXLmNQnV24nGemIUt0GUciUameWLu/GrJg6hMoYailcAv8gbEMAW58V/lQs4PXLjUJB5jmlrhQc1EEjgV5mg8Wm1BsqBZKIZ5Avur/qgV3NDPg4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=chimac.ro; spf=pass smtp.mailfrom=chimac.ro; dkim=pass (2048-bit key) header.d=chimac.ro header.i=@chimac.ro header.b=JYM8vV2C; arc=none smtp.client-ip=185.70.43.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=chimac.ro Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chimac.ro Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=chimac.ro header.i=@chimac.ro header.b="JYM8vV2C" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chimac.ro; s=protonmail; t=1757884803; x=1758144003; bh=1EaguFJG3EwdqxLOzj/lIvUP3qDQ9JAhvQikWa36Nr4=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=JYM8vV2CWrCgcOVDN9MlGimqWOPYRDl2Djc71AzdipWFvhEDiol+wcdZXOFixjH2Q FCuCQ5pu7kmRGLub+CCINydStERdi8P/lcThKD1uz2D60cLDssdQM8gvtZXEq5bSkS +klNWGAjaKUBZqlEODvRnkbC2ov+Fp7lZkrB7awlPwszKk7eufADz4FYJofXMHxK6r 8IVg17Cia2qyV1AEQiwY8F9ngetrZQYjAAl43leOQK0ubYiS9pWQ+l/5MiD6M8zVuL PhTFyIKZ79ELi1OzYqSzvfM3scNcSsEjjvaOa3l1pQGjN1Ki+hFtZE2rJP8ujEgsGT JvPFvV1B10Egg== Date: Sun, 14 Sep 2025 21:19:57 +0000 To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Alexandru Chimac , Krzysztof Kozlowski From: Alexandru Chimac Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Alexandru Chimac Subject: [PATCH 4/8] arm64: dts: exynos9610: Enable clock support Message-ID: <20250915-exynos9610-clocks-v1-4-3f615022b178@chimac.ro> In-Reply-To: <20250915-exynos9610-clocks-v1-0-3f615022b178@chimac.ro> References: <20250915-exynos9610-clocks-v1-0-3f615022b178@chimac.ro> Feedback-ID: 139133584:user:proton X-Pm-Message-ID: 5451127c6ce1cf9b66b10cf80d71c9691606530d Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add CMU (Clock Management Unit) nodes and required fixed clocks. Signed-off-by: Alexandru Chimac --- arch/arm64/boot/dts/exynos/exynos9610-gta4xl.dts | 1 + arch/arm64/boot/dts/exynos/exynos9610.dtsi | 205 +++++++++++++++++++= ++++ 2 files changed, 206 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos9610-gta4xl.dts b/arch/arm64/= boot/dts/exynos/exynos9610-gta4xl.dts index f455af22ff872c6f07b9bcfc68b1ae1f45d0def3..1a09d5e8ebaa130e9cd0b7f3266= ee2c9dac4cf9a 100644 --- a/arch/arm64/boot/dts/exynos/exynos9610-gta4xl.dts +++ b/arch/arm64/boot/dts/exynos/exynos9610-gta4xl.dts @@ -10,6 +10,7 @@ #include "exynos9610.dtsi" #include #include +#include =20 / { compatible =3D "samsung,gta4xl", "samsung,exynos9610"; diff --git a/arch/arm64/boot/dts/exynos/exynos9610.dtsi b/arch/arm64/boot/d= ts/exynos/exynos9610.dtsi index 852f7111e5cdfd82b5afc350792e8b539fe87d39..2a15986c459d6af9f83362c27cd= cc3a2646c256b 100644 --- a/arch/arm64/boot/dts/exynos/exynos9610.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos9610.dtsi @@ -6,6 +6,7 @@ */ =20 #include +#include =20 / { compatible =3D "samsung,exynos9610"; @@ -161,6 +162,41 @@ oscclk: clock-osc { clock-frequency =3D <26000000>; }; =20 + dll_dco: clock-dll-dco { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-output-names =3D "dll_dco"; + clock-frequency =3D <360000000>; + }; + + oscclk_rco_cmgp: clock-osc-rco { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-output-names =3D "oscclk_rco"; + clock-frequency =3D <30000000>; + }; + + ioclk_audiocdclk0: clock-audiocdclk0 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-output-names =3D "ioclk_audiocdclk0"; + clock-frequency =3D <10000000>; + }; + + ioclk_audiocdclk1: clock-audiocdclk1 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-output-names =3D "ioclk_audiocdclk1"; + clock-frequency =3D <100000000>; + }; + + tick_usb: clock-tick-usb { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-output-names =3D "tick_usb"; + clock-frequency =3D <60000000>; + }; + soc: soc@0 { compatible =3D "simple-bus"; ranges =3D <0x0 0x0 0x0 0x20000000>; @@ -174,12 +210,81 @@ chipid@10000000 { reg =3D <0x10000000 0x100>; }; =20 + cmu_peri: clock-controller@10030000 { + compatible =3D "samsung,exynos9610-cmu-peri"; + reg =3D <0x10030000 0x8000>; + #clock-cells =3D <1>; + + clocks =3D <&oscclk>, + <&cmu_top CLK_DOUT_CMU_PERI_BUS>, + <&cmu_top CLK_DOUT_CMU_PERI_IP>, + <&cmu_top CLK_DOUT_CMU_PERI_UART>; + clock-names =3D "oscclk", + "dout_cmu_peri_bus", + "dout_cmu_peri_ip", + "dout_cmu_peri_uart"; + }; + + cmu_cpucl1: clock-controller@0x10800000 { + compatible =3D "samsung,exynos9610-cmu-cpucl1"; + reg =3D <0x10800000 0x8000>; + #clock-cells =3D <1>; + + clocks =3D <&oscclk>, + <&cmu_top CLK_DOUT_CMU_CPUCL1_SWITCH>, + <&cmu_top CLK_DOUT_CMU_HPM>; + clock-names =3D "oscclk", + "dout_cmu_cpucl1_switch", + "dout_cmu_hpm"; + }; + + cmu_cpucl0: clock-controller@0x10900000 { + compatible =3D "samsung,exynos9610-cmu-cpucl0"; + reg =3D <0x10900000 0x8000>; + #clock-cells =3D <1>; + + clocks =3D <&oscclk>, + <&cmu_top CLK_DOUT_CMU_CPUCL0_DBG>, + <&cmu_top CLK_DOUT_CMU_CPUCL0_SWITCH>, + <&cmu_top CLK_DOUT_CMU_HPM>; + clock-names =3D "oscclk", + "dout_cmu_cpucl0_dbg", + "dout_cmu_cpucl0_switch", + "dout_cmu_hpm"; + }; + pinctrl_shub: pinctrl@11080000 { compatible =3D "samsung,exynos9610-pinctrl"; reg =3D <0x11080000 0x1000>; interrupts =3D ; }; =20 + cmu_g3d: clock-controller@11430000 { + compatible =3D "samsung,exynos9610-cmu-g3d"; + reg =3D <0x11430000 0x8000>; + #clock-cells =3D <1>; + + clocks =3D <&oscclk>, + <&cmu_top CLK_DOUT_CMU_G3D_SWITCH>, + <&cmu_top CLK_DOUT_CMU_HPM>; + clock-names =3D "oscclk", + "dout_cmu_g3d_switch", + "dout_cmu_hpm"; + }; + + cmu_apm: clock-controller@11800000 { + compatible =3D "samsung,exynos9610-cmu-apm"; + reg =3D <0x11800000 0x8000>; + #clock-cells =3D <1>; + + clocks =3D <&oscclk>, + <&dll_dco>, + <&cmu_top CLK_DOUT_CMU_APM_BUS>; + clock-names =3D "oscclk", + "dll_dco", + "dout_cmu_apm_bus"; + }; + pinctrl_alive: pinctrl@11850000 { compatible =3D "samsung,exynos9610-pinctrl"; reg =3D <0x11850000 0x1000>; @@ -191,11 +296,48 @@ wakeup-interrupt-controller { }; }; =20 + cmu_cmgp: clock-controller@11c00000 { + compatible =3D "samsung,exynos9610-cmu-cmgp"; + reg =3D <0x11c00000 0x8000>; + #clock-cells =3D <1>; + + clocks =3D <&oscclk>, + <&oscclk_rco_cmgp>, + <&cmu_apm CLK_GOUT_CMU_CMGP_BUS>; + clock-names =3D "oscclk", + "oscclk_rco", + "gout_cmu_cmgp_bus"; + }; + pinctrl_cmgp: pinctrl@11c20000 { compatible =3D "samsung,exynos9610-pinctrl"; reg =3D <0x11c20000 0x1000>; }; =20 + cmu_core: clock-controller@120f0000 { + compatible =3D "samsung,exynos9610-cmu-core"; + reg =3D <0x120f0000 0x8000>; + #clock-cells =3D <1>; + + clocks =3D <&oscclk>, + <&cmu_top CLK_DOUT_CMU_CORE_BUS>, + <&cmu_top CLK_DOUT_CMU_CORE_CCI>, + <&cmu_top CLK_DOUT_CMU_CORE_G3D>; + clock-names =3D "oscclk", + "dout_cmu_core_bus", + "dout_cmu_core_cci", + "dout_cmu_core_g3d"; + }; + + cmu_top: clock-controller@12100000 { + compatible =3D "samsung,exynos9610-cmu-top"; + reg =3D <0x12100000 0x8000>; + #clock-cells =3D <1>; + + clocks =3D <&oscclk>; + clock-names =3D "oscclk"; + }; + gic: interrupt-controller@12300000 { compatible =3D "arm,gic-400"; #interrupt-cells =3D <3>; @@ -209,6 +351,37 @@ gic: interrupt-controller@12300000 { IRQ_TYPE_LEVEL_HIGH)>; }; =20 + cmu_g2d: clock-controller@12e00000 { + compatible =3D "samsung,exynos9610-cmu-g2d"; + reg =3D <0x12e00000 0x8000>; + #clock-cells =3D <1>; + + clocks =3D <&oscclk>, + <&cmu_top CLK_DOUT_CMU_G2D_G2D>, + <&cmu_top CLK_DOUT_CMU_G2D_MSCL>; + + clock-names =3D "oscclk", + "dout_cmu_g2d_g2d", + "dout_cmu_g2d_mscl"; + }; + + cmu_fsys: clock-controller@13400000 { + compatible =3D "samsung,exynos9610-cmu-fsys"; + reg =3D <0x13400000 0x8000>; + #clock-cells =3D <1>; + + clocks =3D <&oscclk>, + <&cmu_top CLK_DOUT_CMU_FSYS_BUS>, + <&cmu_top CLK_DOUT_CMU_FSYS_MMC_CARD>, + <&cmu_top CLK_DOUT_CMU_FSYS_MMC_EMBD>, + <&cmu_top CLK_DOUT_CMU_FSYS_UFS_EMBD>; + clock-names =3D "oscclk", + "dout_cmu_fsys_bus", + "dout_cmu_fsys_mmc_card", + "dout_cmu_fsys_mmc_embd", + "dout_cmu_fsys_ufs_embd"; + }; + pinctrl_fsys: pinctrl@13490000 { compatible =3D "samsung,exynos9610-pinctrl"; reg =3D <0x13490000 0x1000>; @@ -221,6 +394,38 @@ pinctrl_top: pinctrl@139b0000 { interrupts =3D ; }; =20 + cmu_cam: clock-controller@14500000 { + compatible =3D "samsung,exynos9610-cmu-cam"; + reg =3D <0x14500000 0x8000>; + #clock-cells =3D <1>; + + clocks =3D <&oscclk>, + <&cmu_top CLK_DOUT_CMU_CAM_BUS>; + clock-names =3D "oscclk", + "dout_cmu_cam_bus"; + }; + + cmu_dispaud: clock-controller@14980000 { + compatible =3D "samsung,exynos9610-cmu-dispaud"; + reg =3D <0x14980000 0x8000>; + #clock-cells =3D <1>; + + clocks =3D <&oscclk>, + <&ioclk_audiocdclk0>, + <&ioclk_audiocdclk1>, + <&tick_usb>, + <&cmu_top CLK_DOUT_CMU_DISPAUD_AUD>, + <&cmu_top CLK_DOUT_CMU_DISPAUD_CPU>, + <&cmu_top CLK_DOUT_CMU_DISPAUD_DISP>; + clock-names =3D "oscclk", + "ioclk_audiocdclk0", + "ioclk_audiocdclk1", + "tick_usb", + "dout_cmu_dispaud_aud", + "dout_cmu_dispaud_cpu", + "dout_cmu_dispaud_disp"; + }; + pinctrl_dispaud: pinctrl@14a60000 { compatible =3D "samsung,exynos9610-pinctrl"; reg =3D <0x14a60000 0x1000>; --=20 2.47.3 From nobody Thu Oct 2 16:35:37 2025 Received: from mail-4317.protonmail.ch (mail-4317.protonmail.ch [185.70.43.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD7A92E5B36; Sun, 14 Sep 2025 21:20:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757884821; cv=none; b=bnJH3ua+rnF8jT+vatEWSZwupZ3CIP2UH8pfMOFQYO3fjO2nOhngLEsPLWlb4p0g7dsGH4dDsdRJVsUbYFfYbpjKoAPYDiehnD5+EUf8wKEJ84FpKRx4GzT5fOU66TJsntbUvKFuQjYdPZkQOhISSXWTQfbn+EVHrvpDj9DzKBE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757884821; c=relaxed/simple; bh=M2Gl0h1IbNc0ONXLAYgn4s7jZx5zqBBGfF+tL32SZ3w=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=BghBsOgtt4qbx39jz7JEsHAl6nmjIZ1MrCZqssGFy/IbSg4eLHc7XtDkNVABvNs5EOkvI/6wT7SFu6YGJRjIL3jYAIkWWA0ScUaWEE8O3qB3BfEG/yRI4fElACHdFpTHea1hGGxtvbxGP0ELgzl2TQwJJI+EcSf5TpiMAgR9D0k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=chimac.ro; spf=pass smtp.mailfrom=chimac.ro; dkim=pass (2048-bit key) header.d=chimac.ro header.i=@chimac.ro header.b=Zg3jQpfL; arc=none smtp.client-ip=185.70.43.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=chimac.ro Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chimac.ro Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=chimac.ro header.i=@chimac.ro header.b="Zg3jQpfL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chimac.ro; s=protonmail; t=1757884817; x=1758144017; bh=r6Y2Gkn706akrIKg6YESStK0AnOYg63HDq/ISSMQOuw=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=Zg3jQpfLTiNwnSTWvTuYzLoYFJY5wbKi6WuQ5nHrIXkpLfX13TSxMg8QQ639lGF3W c4WOinvEQjYbgzWczW6rpsm2Bl67kLoG+kc8y8J0gxjXQW9LdJGBnYi/4kpqfPNsV3 PCjFTsKlTsv0yS990AWMAGWSFbTLtxctVm/OgcUPRbYP3oQYA5AIoe8uwoFGkeTL6t 9YDX0/diEPlXTIy0JrpUo96tSx4BW8YGWfz9d9IfdV6HsJzXQd2Nfw1p5XfX3xso4v YpjqmKdK22Khoe8sLupBHnGcLIhCE5cWn/kWBCPxxgq53pt4WJyNsYKtZ89wT8aVAy h75FKtCqA1V2A== Date: Sun, 14 Sep 2025 21:20:09 +0000 To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Alexandru Chimac , Krzysztof Kozlowski From: Alexandru Chimac Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Alexandru Chimac Subject: [PATCH 5/8] dt-bindings: soc: exynos-sysreg: Add Exynos9610 SYSREG bindings Message-ID: <20250915-exynos9610-clocks-v1-5-3f615022b178@chimac.ro> In-Reply-To: <20250915-exynos9610-clocks-v1-0-3f615022b178@chimac.ro> References: <20250915-exynos9610-clocks-v1-0-3f615022b178@chimac.ro> Feedback-ID: 139133584:user:proton X-Pm-Message-ID: 0485798802bb0d7269f0f916ac2aa86437c9d201 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add bindings for SYSREG nodes, compatible with the standard syscon driver. Signed-off-by: Alexandru Chimac Acked-by: Rob Herring (Arm) --- .../bindings/soc/samsung/samsung,exynos-sysreg.yaml | 20 ++++++++++++++++= ++++ 1 file changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-s= ysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-s= ysreg.yaml index d8b302f975474a87e4886006cf0b21cf758e4479..9f759e457a0acc2870adfd077d3= 3870593cf7b83 100644 --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.y= aml +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.y= aml @@ -30,6 +30,16 @@ properties: - samsung,exynos8895-fsys1-sysreg - samsung,exynos8895-peric0-sysreg - samsung,exynos8895-peric1-sysreg + - samsung,exynos9610-apm-sysreg + - samsung,exynos9610-cam-sysreg + - samsung,exynos9610-core-sysreg + - samsung,exynos9610-cpucl0-sysreg + - samsung,exynos9610-cpucl1-sysreg + - samsung,exynos9610-dispaud-sysreg + - samsung,exynos9610-fsys-sysreg + - samsung,exynos9610-g2d-sysreg + - samsung,exynos9610-g3d-sysreg + - samsung,exynos9610-peri-sysreg - samsung,exynosautov920-hsi2-sysreg - samsung,exynosautov920-peric0-sysreg - samsung,exynosautov920-peric1-sysreg @@ -93,6 +103,16 @@ allOf: - samsung,exynos8895-fsys1-sysreg - samsung,exynos8895-peric0-sysreg - samsung,exynos8895-peric1-sysreg + - samsung,exynos9610-apm-sysreg + - samsung,exynos9610-cam-sysreg + - samsung,exynos9610-core-sysreg + - samsung,exynos9610-cpucl0-sysreg + - samsung,exynos9610-cpucl1-sysreg + - samsung,exynos9610-dispaud-sysreg + - samsung,exynos9610-fsys-sysreg + - samsung,exynos9610-g2d-sysreg + - samsung,exynos9610-g3d-sysreg + - samsung,exynos9610-peri-sysreg then: required: - clocks --=20 2.47.3 From nobody Thu Oct 2 16:35:37 2025 Received: from mail-24421.protonmail.ch (mail-24421.protonmail.ch [109.224.244.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2DA12E6CC2; Sun, 14 Sep 2025 21:20:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.224.244.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757884827; cv=none; b=XN3YeL4rM9exZOBSZmyXJxtvK0Zy/EVEIfcN0sBZpj4z2QEXt0w69rKfDNCpni/PP9DvsaO2eNDg7Zdi7/wGziXZ/x2nm2Bp/izDtYufO10HjnB9oTZlzROMwSO5jq8jyYAOSc/TRuwtrl26we68izv2Zx3Mu1HPuWz562lBWvs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757884827; c=relaxed/simple; bh=sU7BKaFw/8uJ1LBErEnc8iSqM1dk4mIUART/Y2NQtoA=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=d6hPBhjeYX4jT2JldwPo0SMULUl6Ngt89vgPyIy/klqjlWeFoF2qykrpWlHSDW7W8FS11BnLZ0vfDWp69/LxXGeLZQhcdGgiGlQ7SNcYZK6nqigqN2FigR90NUqkpSthgO/khTXnc0FPp+MIRNXc10UF69lOXDopAy+fy6B8HWo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=chimac.ro; spf=pass smtp.mailfrom=chimac.ro; dkim=pass (2048-bit key) header.d=chimac.ro header.i=@chimac.ro header.b=G6M2UqUG; arc=none smtp.client-ip=109.224.244.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=chimac.ro Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chimac.ro Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=chimac.ro header.i=@chimac.ro header.b="G6M2UqUG" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chimac.ro; s=protonmail; t=1757884823; x=1758144023; bh=bA/7FABn8a7pWXMpM2xcA7gy/SjjJShwWBDUuziXWHI=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=G6M2UqUGp7EYBFZAHUDRc++hqW3Ox5Ltcw5epvx0gpK6njbhd3EiTD0fL3lRNyCTE RAX6rafNS3uLuqmD8kZ/FjiWT9V/TtS3Xy5mmR+h7V86nUavVjdfmpvN+gU2FZlkFr hJx6mWdn6KWWA30voFzRtRE3aAv+6GqCqwT20zGlwl6LbNu/ZTuVKEKZ8rcyU1s7bG nUo+GBxLux5+pUS0KBpvpjKNYiHyJNXNxUmewO6x5Tygjsf+Sa25+eFol2QC4FacJl +7OEnwrzKWcDlYUHUxYr72DKGagdNtgoXagdeKp2JfEt6k3Zo1YdWUXYau/K9YKFWM 6rp03y9DJEz0Q== Date: Sun, 14 Sep 2025 21:20:20 +0000 To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Alexandru Chimac , Krzysztof Kozlowski From: Alexandru Chimac Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Alexandru Chimac Subject: [PATCH 6/8] arm64: dts: exynos9610: Add SYSREG nodes Message-ID: <20250915-exynos9610-clocks-v1-6-3f615022b178@chimac.ro> In-Reply-To: <20250915-exynos9610-clocks-v1-0-3f615022b178@chimac.ro> References: <20250915-exynos9610-clocks-v1-0-3f615022b178@chimac.ro> Feedback-ID: 139133584:user:proton X-Pm-Message-ID: a999af5f5abde04ff6dc9488d0fec36982f1cc2a Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add nodes for: - apm-sysreg - cam-sysreg - core-sysreg - cpucl0/1-sysreg - dispaud-sysreg - fsys-sysreg - g2d/g3d-sysreg - peri-sysreg Signed-off-by: Alexandru Chimac --- arch/arm64/boot/dts/exynos/exynos9610.dtsi | 60 ++++++++++++++++++++++++++= ++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos9610.dtsi b/arch/arm64/boot/d= ts/exynos/exynos9610.dtsi index 2a15986c459d6af9f83362c27cdcc3a2646c256b..8ac113ceddacc30b52fa35954c8= 5e1b8c320057d 100644 --- a/arch/arm64/boot/dts/exynos/exynos9610.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos9610.dtsi @@ -210,6 +210,12 @@ chipid@10000000 { reg =3D <0x10000000 0x100>; }; =20 + sysreg_peri: system-controller@10010000 { + compatible =3D "samsung,exynos9610-peri-sysreg", "syscon"; + reg =3D <0x10010000 0x10000>; + clocks =3D <&cmu_peri CLK_GOUT_PERI_SYSREG_PCLK>; + }; + cmu_peri: clock-controller@10030000 { compatible =3D "samsung,exynos9610-cmu-peri"; reg =3D <0x10030000 0x8000>; @@ -238,6 +244,12 @@ cmu_cpucl1: clock-controller@0x10800000 { "dout_cmu_hpm"; }; =20 + sysreg_cpucl1: system-controller@10810000 { + compatible =3D "samsung,exynos9610-cpucl1-sysreg", "syscon"; + reg =3D <0x10810000 0x10000>; + clocks =3D <&cmu_cpucl1 CLK_GOUT_CPUCL1_SYSREG_PCLK>; + }; + cmu_cpucl0: clock-controller@0x10900000 { compatible =3D "samsung,exynos9610-cmu-cpucl0"; reg =3D <0x10900000 0x8000>; @@ -253,12 +265,24 @@ cmu_cpucl0: clock-controller@0x10900000 { "dout_cmu_hpm"; }; =20 + sysreg_cpucl0: system-controller@10910000 { + compatible =3D "samsung,exynos9610-cpucl0-sysreg", "syscon"; + reg =3D <0x10910000 0x10000>; + clocks =3D <&cmu_cpucl0 CLK_GOUT_CPUCL0_SYSREG_PCLK>; + }; + pinctrl_shub: pinctrl@11080000 { compatible =3D "samsung,exynos9610-pinctrl"; reg =3D <0x11080000 0x1000>; interrupts =3D ; }; =20 + sysreg_g3d: system-controller@11410000 { + compatible =3D "samsung,exynos9610-g3d-sysreg", "syscon"; + reg =3D <0x11410000 0x10000>; + clocks =3D <&cmu_g3d CLK_GOUT_G3D_SYSREG_PCLK>; + }; + cmu_g3d: clock-controller@11430000 { compatible =3D "samsung,exynos9610-cmu-g3d"; reg =3D <0x11430000 0x8000>; @@ -285,6 +309,12 @@ cmu_apm: clock-controller@11800000 { "dout_cmu_apm_bus"; }; =20 + sysreg_apm: system-controller@11810000 { + compatible =3D "samsung,exynos9610-apm-sysreg", "syscon"; + reg =3D <0x11810000 0x10000>; + clocks =3D <&cmu_apm CLK_GOUT_APM_SYSREG_PCLK>; + }; + pinctrl_alive: pinctrl@11850000 { compatible =3D "samsung,exynos9610-pinctrl"; reg =3D <0x11850000 0x1000>; @@ -314,6 +344,12 @@ pinctrl_cmgp: pinctrl@11c20000 { reg =3D <0x11c20000 0x1000>; }; =20 + sysreg_core: system-controller@12010000 { + compatible =3D "samsung,exynos9610-core-sysreg", "syscon"; + reg =3D <0x12010000 0x10000>; + clocks =3D <&cmu_core CLK_GOUT_CORE_SYSREG_PCLK>; + }; + cmu_core: clock-controller@120f0000 { compatible =3D "samsung,exynos9610-cmu-core"; reg =3D <0x120f0000 0x8000>; @@ -365,6 +401,12 @@ cmu_g2d: clock-controller@12e00000 { "dout_cmu_g2d_mscl"; }; =20 + sysreg_g2d: system-controller@12e10000 { + compatible =3D "samsung,exynos9610-g2d-sysreg", "syscon"; + reg =3D <0x12e10000 0x10000>; + clocks =3D <&cmu_g2d CLK_GOUT_G2D_SYSREG_PCLK>; + }; + cmu_fsys: clock-controller@13400000 { compatible =3D "samsung,exynos9610-cmu-fsys"; reg =3D <0x13400000 0x8000>; @@ -382,6 +424,12 @@ cmu_fsys: clock-controller@13400000 { "dout_cmu_fsys_ufs_embd"; }; =20 + sysreg_fsys: system-controller@13410000 { + compatible =3D "samsung,exynos9610-fsys-sysreg", "syscon"; + reg =3D <0x13410000 0x10000>; + clocks =3D <&cmu_fsys CLK_GOUT_FSYS_SYSREG_PCLK>; + }; + pinctrl_fsys: pinctrl@13490000 { compatible =3D "samsung,exynos9610-pinctrl"; reg =3D <0x13490000 0x1000>; @@ -405,6 +453,18 @@ cmu_cam: clock-controller@14500000 { "dout_cmu_cam_bus"; }; =20 + sysreg_cam: system-controller@14510000 { + compatible =3D "samsung,exynos9610-cam-sysreg", "syscon"; + reg =3D <0x14510000 0x10000>; + clocks =3D <&cmu_cam CLK_GOUT_CAM_SYSREG_PCLK>; + }; + + sysreg_dispaud: system-controller@14810000 { + compatible =3D "samsung,exynos9610-dispaud-sysreg", "syscon"; + reg =3D <0x14810000 0x10000>; + clocks =3D <&cmu_dispaud CLK_GOUT_DISPAUD_SYSREG_PCLK>; + }; + cmu_dispaud: clock-controller@14980000 { compatible =3D "samsung,exynos9610-cmu-dispaud"; reg =3D <0x14980000 0x8000>; --=20 2.47.3 From nobody Thu Oct 2 16:35:37 2025 Received: from mail-24420.protonmail.ch (mail-24420.protonmail.ch [109.224.244.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6645E2E62CB; Sun, 14 Sep 2025 21:20:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.224.244.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757884843; cv=none; b=A07i8lPzf9rqK9b4iILcFk27RmbfFk+jZvtgRdywMCQfrU6N5+au2SNJ4xn+gQIWNIYposHgkY2m3YbkTXoRbX8DHwSrec+ZgZLPFmesi1UbeGXvb1JPlVyHyhvQhtOKv3cdmD8hHHPMITpqHjklcJklmWowJR0PjdvFCO6lVPo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757884843; c=relaxed/simple; bh=n8ed6ZgNTYQSpv3lZaLRY2mtiSkCkEeoGCHf236I0Kg=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=p3jhycjRp+ogJmMjMMMcAKGM5Oy/bz8APxSDpafPHoninsXprx4NGk7vWu1ACHKyEjIF9/ykHRC/lHcUSLjDicxAjnH2LXlAsZPDS/PDTC9OG82XsGhstiH3B6D3laJI+dH/z7Kv5ff++XH27Q+Bm9m7VGzzFP1a81wu3n6SrD8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=chimac.ro; spf=pass smtp.mailfrom=chimac.ro; dkim=pass (2048-bit key) header.d=chimac.ro header.i=@chimac.ro header.b=OHpyasHg; arc=none smtp.client-ip=109.224.244.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=chimac.ro Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chimac.ro Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=chimac.ro header.i=@chimac.ro header.b="OHpyasHg" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chimac.ro; s=protonmail; t=1757884838; x=1758144038; bh=MuYJPjqO369cLtT78pu4q0h8jWBIkb6EelOSKhjt1So=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=OHpyasHghddSwMxti/2xQUmZSn7VMYXCUj52PeyQLUMrRnDjQYcWTuTCKXVe3q73c 1IpUZX//AYFSlgXkzytlRMk1ku+JZDmx7NOTnEwlC72RNdGbSJ2O7n6CrRY/mNXJvJ nLNKJigFdwnzn6dtMzwyCgFkEGf/wdwjxBFDFRlz34uQndkozZz8NFJa96ZbpjXBn9 cGUtrCGLokviFilbNkm4dHCrIFhZvgVY0rfSYUatgfbj4seZQbmySFqRtC6ztpnXX5 hM1jgxs+U3gRzhHoTxDFx+M+SzjqNkMq7WqJ3DSFY3qL/QhuGQx6jx0HLtBYEsF37X ugl8FYyUgpXng== Date: Sun, 14 Sep 2025 21:20:30 +0000 To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Alexandru Chimac , Krzysztof Kozlowski From: Alexandru Chimac Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Alexandru Chimac Subject: [PATCH 7/8] arm64: dts: exynos9610: Assign clocks to existing nodes Message-ID: <20250915-exynos9610-clocks-v1-7-3f615022b178@chimac.ro> In-Reply-To: <20250915-exynos9610-clocks-v1-0-3f615022b178@chimac.ro> References: <20250915-exynos9610-clocks-v1-0-3f615022b178@chimac.ro> Feedback-ID: 139133584:user:proton X-Pm-Message-ID: 4ccc2d5e2d6824a04c8c279d5349b2744e279e32 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Required in order to have these parts work while the clock driver is enabled (without clk_ignore_unused). Signed-off-by: Alexandru Chimac --- arch/arm64/boot/dts/exynos/exynos9610.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos9610.dtsi b/arch/arm64/boot/d= ts/exynos/exynos9610.dtsi index 8ac113ceddacc30b52fa35954c85e1b8c320057d..2dc7cdda83d9357cb2a44d58d66= 6a75674c83ec4 100644 --- a/arch/arm64/boot/dts/exynos/exynos9610.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos9610.dtsi @@ -319,6 +319,9 @@ pinctrl_alive: pinctrl@11850000 { compatible =3D "samsung,exynos9610-pinctrl"; reg =3D <0x11850000 0x1000>; =20 + clocks =3D <&cmu_apm CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK>; + clock-names =3D "pclk"; + wakeup-interrupt-controller { compatible =3D "samsung,exynos9610-wakeup-eint", "samsung,exynos850-wakeup-eint", @@ -342,6 +345,9 @@ cmu_cmgp: clock-controller@11c00000 { pinctrl_cmgp: pinctrl@11c20000 { compatible =3D "samsung,exynos9610-pinctrl"; reg =3D <0x11c20000 0x1000>; + + clocks =3D <&cmu_cmgp CLK_GOUT_CMGP_GPIO_PCLK>; + clock-names =3D "pclk"; }; =20 sysreg_core: system-controller@12010000 { @@ -385,6 +391,8 @@ gic: interrupt-controller@12300000 { <0x12306000 0x2000>; interrupts =3D ; + clocks =3D <&cmu_core CLK_GOUT_CORE_GIC_CLK>; + clock-names =3D "clk"; }; =20 cmu_g2d: clock-controller@12e00000 { @@ -434,6 +442,8 @@ pinctrl_fsys: pinctrl@13490000 { compatible =3D "samsung,exynos9610-pinctrl"; reg =3D <0x13490000 0x1000>; interrupts =3D ; + clocks =3D <&cmu_fsys CLK_GOUT_FSYS_GPIO_PCLK>; + clock-names =3D "pclk"; }; =20 pinctrl_top: pinctrl@139b0000 { @@ -489,6 +499,8 @@ cmu_dispaud: clock-controller@14980000 { pinctrl_dispaud: pinctrl@14a60000 { compatible =3D "samsung,exynos9610-pinctrl"; reg =3D <0x14a60000 0x1000>; + clocks =3D <&cmu_dispaud CLK_GOUT_DISPAUD_GPIO_DISPAUD_PCLK>; + clock-names =3D "pclk"; }; }; =20 --=20 2.47.3 From nobody Thu Oct 2 16:35:37 2025 Received: from mail-10627.protonmail.ch (mail-10627.protonmail.ch [79.135.106.27]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D3F62E7F15; Sun, 14 Sep 2025 21:20:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=79.135.106.27 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757884853; cv=none; b=WQiKHR8+mnk6/FrQyWpNMmkaXEfByntiC6/IkruNmLH1vVwPdT1SIzFidV3kUAhw99kCBc/UL5AbxnRgOuiTgotKfGkUxwT/1bAFVAbrvN4GqHQ5N5LciAvqhtdZ68CicpKwQ0rnTa3YoJDT9NXuRjaQ3cjjN8wORxGI4gIZMWg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757884853; c=relaxed/simple; bh=mmgJCfUyGE59PSXhluohTFxk2CSFp51DzKWgMlshUko=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MYeR9MUC/SeF0LXGlw/eoKvwnSHxPUENL/G5Klixvt6hUAhqePcCbV4qvww1sSvvkcfHSwRdMFOsFN3rMUD8nMvBWvMVttOREOrEtkswSQQ5wNBJmJTHvsW1ZrU2uMLA+QooHYUkJwh4egHEyJ7lK6y92jvSBkcvT/eV2q3iq5Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=chimac.ro; spf=pass smtp.mailfrom=chimac.ro; dkim=pass (2048-bit key) header.d=chimac.ro header.i=@chimac.ro header.b=EFjT+GYP; arc=none smtp.client-ip=79.135.106.27 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=chimac.ro Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=chimac.ro Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=chimac.ro header.i=@chimac.ro header.b="EFjT+GYP" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chimac.ro; s=protonmail; t=1757884848; x=1758144048; bh=mmgJCfUyGE59PSXhluohTFxk2CSFp51DzKWgMlshUko=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=EFjT+GYPLf7Fuy9LBws+HTJ22YxKwa15I1oUIQSH2bStoj0Prtx9I6TSv40dVAifj mCT2qcc0lZTDeypszc+eBlOmJGRAyeA9furSO7n5APntt741nVGFkLg6pnAW7OBSHH QsOj1R4pnxojfEo0QGrO1K5YxUrjqqyJ8tTXGNbsrUUaHxW1vHzjCjVy26Q0Y1TJHM +iYJ/+fLSnCBqhkHrxEXkN5KObtYJZOXXJX+sdwwVMASaNF9n8ygp3tsnVpkOWcJRL hQLm+sf/n7q62Z+7XDeT1LZMcjMbV0lkeL+bkVtAUUOfz5XW/y1l+GVYfOWHRLKSzE LBPWIiFJhcDfA== Date: Sun, 14 Sep 2025 21:20:42 +0000 To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley , Alexandru Chimac , Krzysztof Kozlowski From: Alexandru Chimac Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Alexandru Chimac Subject: [PATCH 8/8] arm64: dts: exynos9610-gta4xl: Assign clocks to existing nodes Message-ID: <20250915-exynos9610-clocks-v1-8-3f615022b178@chimac.ro> In-Reply-To: <20250915-exynos9610-clocks-v1-0-3f615022b178@chimac.ro> References: <20250915-exynos9610-clocks-v1-0-3f615022b178@chimac.ro> Feedback-ID: 139133584:user:proton X-Pm-Message-ID: 817b1c8826d8fad866384fcd032225ea749d553a Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Temporarily assign DISPAUD_DISP gate to simplefb node, until the Exynos DRM driver will support this SoC. Signed-off-by: Alexandru Chimac --- arch/arm64/boot/dts/exynos/exynos9610-gta4xl.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/exynos/exynos9610-gta4xl.dts b/arch/arm64/= boot/dts/exynos/exynos9610-gta4xl.dts index 1a09d5e8ebaa130e9cd0b7f3266ee2c9dac4cf9a..e08a3603c27396c96dc2e9d5186= be504ff7ce3aa 100644 --- a/arch/arm64/boot/dts/exynos/exynos9610-gta4xl.dts +++ b/arch/arm64/boot/dts/exynos/exynos9610-gta4xl.dts @@ -29,6 +29,7 @@ framebuffer0: framebuffer@ca000000 { height =3D <2000>; stride =3D <(1200 * 4)>; format =3D "a8r8g8b8"; + clocks =3D <&cmu_dispaud CLK_GOUT_DISPAUD_CLK_DISPAUD_DISP>; }; }; =20 --=20 2.47.3