From nobody Thu Oct 2 15:33:04 2025 Received: from mail-lf1-f45.google.com (mail-lf1-f45.google.com [209.85.167.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2998D2C3263 for ; Mon, 15 Sep 2025 07:12:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757920354; cv=none; b=V/lZx6UDSwXlxTTGwm5PAhFPm4lZIzw1H5Cz9nu8RK/F/EVa68e9wQ2u7Z/MooVpGKlQ/cNTDsOGvbMnFD0X8eFngLbAXbjQGMPx4NauOok21eTxrrpCrJUhGQeYgYvPR6TYncduS/RuNJ1NkiwkN6QCe7FpaIk2W5BrCbrwyN0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757920354; c=relaxed/simple; bh=A/pvIm8LIuK60+1hR9C0NY5zWTyTKfhuv51MAMU58ik=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=D9TN9z80BZDY3hciwcWNAsRaTSG+aN+7Hc1iNIGHfOnqqBHsX8g5wpMj6bEGAhYjl6G3IBrxFIx35T55+kDRD40ilC1IxxTGtaOXBFGDQOp9YfCdMmaIYKCpI6xYkgLVBUGSrAH7AZ2iJvMSPL5EsYrFaTIT+I37nn0PD5Rr7wQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=X6D8tncG; arc=none smtp.client-ip=209.85.167.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="X6D8tncG" Received: by mail-lf1-f45.google.com with SMTP id 2adb3069b0e04-55f6b0049fbso4385626e87.0 for ; Mon, 15 Sep 2025 00:12:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1757920351; x=1758525151; darn=vger.kernel.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=BCTGsKnEAhIcIWggtSqgF0UGR2T7jy2XV44IdHUz0qs=; b=X6D8tncG+PXQxBhFu8x7cusqpaxXdAyJMKkfAH1aDDw3b5Hs0bjZrIl8l+8YQ4ocRx 919YX9OLb8ntm7GDQblrg23gBOKJoK8fmedV14lGpPzvgO7l5wgvcRKOYfiTST4uPKkM gPkejqR1mbP7Q+fCsVCMh95sEhtXREXhK9LP8g4LzzxNI9x5zX8qBJ7Wv7fYZN3iJ4aK zemMw9rh9RHeyznmuvJskgW+lG/ABkhnx27tPg2LlM2WGSZIV5ba3cDJZMC0RWs8omoQ w2X9m5DxSobjmnEvs1aWEbIvsEG9EgZBEvjO8FuhA87eURX97I9JJ8rItO82wL9+ujfv HLfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757920351; x=1758525151; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=BCTGsKnEAhIcIWggtSqgF0UGR2T7jy2XV44IdHUz0qs=; b=PhC6HBlNUEXFd8UxiaJKuMjaUvgZ7EqBdhMQGZGqjbbU0JoTXPsZh2s1SRiMqJjcXg LMNCFTkuDfF4kE+02xcNHVHKjCx1G2ocMWhEOBLZVUf47sTpa2xEdzKf+RteKehNi8cU 0OVZhedkY6hseZASox3IJ2rEbrkka5wcGJ1IwEYou0QSMjR4OmQciElaOvNyqlK1XAB6 QwUDwgqTXjazxbY7aF/JdDrt24NIO/f5loZW380nL32jsHp39J58b30Ug5wOPvKyTQik 4vIc2xCjSHdcuxY9CPjOs4thGoJBGffyxIt0mRNruIYUnRN7ecd/M1Nq1qCjh+mSHR8l QvDg== X-Forwarded-Encrypted: i=1; AJvYcCXVfFkAiSjFe1zzKgKXsbWTPTwL0CGIMJ6NCvY9CZnEN34DAubYB9/sLy2UIryWVSpGOscMYeAvJli1Fj8=@vger.kernel.org X-Gm-Message-State: AOJu0Yw/S6TB61SRp82dl1/Xrul0FNEtirvWFq2qlyQtwxZPA4AfcOZw kyqAdMhqCVRekjS/7EsWt22lQcEDgMyw/4aOMQsv6qJp4pOrLk/GSfWz X-Gm-Gg: ASbGncuctuedRKqKFXC0VxTUQB5nd+hyzm7s2AXeGcAEJGwCe2kxRg5YApST/oEZkkh r5OG+Znr2BxYdGO9AnxXct2jwRBFDQmdjeTNXeExgkzbMcTCtX/Y3FX819XRFdQoqXRmg2iitys uzmryKbV1yTMwvbGffNYVQ9LdX980uOSPdkR45NNVTCADqxst8dqdKBolMsR6m1X9qqUSJrjkl/ 9YN/Ikn/DhDxxoIx9Cy5pLz/6Pq/LpBvW5YREDe4WOqIqP15P+9+KGGdYwMsR4TGd7MU35CM2M8 j5+9tgBsHjUrX5Yai3X4VY+c3MsBMYBkQSmG1A79G5Ihj8Gy7v7XJrVNoSIYTLEP+QwwLlQxXbl UYlpKfPjJQJOse1YXn8D/Pf57AA== X-Google-Smtp-Source: AGHT+IE6viEWBo0Up/kAqkcXMNpwo71/XLp84RYtnhqNjvB3tJoxPxNBcrMFpiOLJW3K15VCZMsb8Q== X-Received: by 2002:ac2:4e12:0:b0:55f:4839:d059 with SMTP id 2adb3069b0e04-5704b52f28fmr2676811e87.13.1757920351004; Mon, 15 Sep 2025 00:12:31 -0700 (PDT) Received: from mva-rohm ([213.255.186.37]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-56e64dbbf7bsm3284576e87.118.2025.09.15.00.12.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Sep 2025 00:12:30 -0700 (PDT) Date: Mon, 15 Sep 2025 10:12:26 +0300 From: Matti Vaittinen To: Jonathan Cameron , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matti Vaittinen , Linus Walleij , Bartosz Golaszewski Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Conor Dooley Subject: [PATCH v5 1/3] dt-bindings: iio: adc: ROHM BD79112 ADC/GPIO Message-ID: <20250915-bd79112-v5-1-a74e011a0560@gmail.com> References: <20250915-bd79112-v5-0-a74e011a0560@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="C43v0lf9gbjbyPJ9" Content-Disposition: inline In-Reply-To: <20250915-bd79112-v5-0-a74e011a0560@gmail.com> X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3384; i=mazziesaccount@gmail.com; h=from:subject:message-id; bh=q+PdYztni/yNFMmXAS+zMK1I2vs1JpjrImQBvaSjEjs=; b=owEBbQGS/pANAwAKAXhQN/9N2qHFAcsmYgBox7tkCRgoCdUzbqg7cAGhthvGC/OCorK969Rdc hRFUcYJLsiJATMEAAEKAB0WIQQjH5/zBlvbx8soSFN4UDf/TdqhxQUCaMe7ZAAKCRB4UDf/Tdqh xbpXCACnuR9mEhXMBLEsL7UwJtAtO7FmMGxLZM7CN3j8ByXUyhVeeMk8UMbmIrdiq0teEHg2NoC FQr6ZvxqPhuXfBJqL+WobE9Ojsc9MoPFEQJiz+ojzLvy+Vy3ielr0SNbJjbPmxb5wOYyieCWxWW A8MYqVxAmTJDN1sPMMiSweRpHxNlKWx94fbUs90ZKtE7jRL7KzFjqEmGeliFN1pqPR6knbZQF+J HBakCLU0i8OZxUCeyxbk5H5bpkqO4hJgEHyI1FOp1zOfaRG8ySQbNRM4a9p7BBIkzSVu4v2sdtf knZ4QBig1zHu4MMZVmlQX0AJtTV9PYm/L1tlVrp/Dd65LOcI X-Developer-Key: i=mazziesaccount@gmail.com; a=openpgp; fpr=83351EE69759B11AF0A3107B40497F0C4693EF47 --C43v0lf9gbjbyPJ9 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ROHM BD79112 is an ADC/GPIO with 32 channels. The channel inputs can be used as ADC or GPIO. Using the GPIOs as IRQ sources isn't supported. The ADC is 12-bit, supporting input voltages up to 5.7V, and separate I/O voltage supply. Maximum SPI clock rate is 20 MHz (10 MHz with daisy-chain configuration) and maximum sampling rate is 1MSPS. Add a device tree binding document for the ROHM BD79112. Signed-off-by: Matti Vaittinen Acked-by: Conor Dooley Reviewed-by: Linus Walleij --- Revision history: v4 =3D> : - No changes v3 =3D> v4: - shorten the example by dropping some channels. v1 =3D> v2: - BD79112 can act as a GPIO controller. --- .../devicetree/bindings/iio/adc/rohm,bd79112.yaml | 104 +++++++++++++++++= ++++ 1 file changed, 104 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/rohm,bd79112.yaml b/= Documentation/devicetree/bindings/iio/adc/rohm,bd79112.yaml new file mode 100644 index 0000000000000000000000000000000000000000..aa8b07c3fac1096c0d48ec64361= 263624f2bb9fc --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/rohm,bd79112.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/rohm,bd79112.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ROHM BD79112 ADC/GPO + +maintainers: + - Matti Vaittinen + +description: | + The ROHM BD79112 is a 12-bit, 32-channel, SAR ADC. ADC input pins can be + also configured as general purpose inputs/outputs. SPI should use MODE 3. + +properties: + compatible: + const: rohm,bd79112 + + reg: + maxItems: 1 + + spi-cpha: true + spi-cpol: true + + gpio-controller: true + "#gpio-cells": + const: 2 + + vdd-supply: true + + iovdd-supply: true + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^channel@([0-9]|[12][0-9]|3[01])$": + type: object + $ref: /schemas/iio/adc/adc.yaml# + description: Represents ADC channel. Omitted channels' inputs are GPIO= s. + + properties: + reg: + description: AIN pin number + minimum: 0 + maximum: 31 + + required: + - reg + + additionalProperties: false + +required: + - compatible + - reg + - iovdd-supply + - vdd-supply + - spi-cpha + - spi-cpol + +additionalProperties: false + +examples: + - | + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + adc: adc@0 { + compatible =3D "rohm,bd79112"; + reg =3D <0x0>; + + spi-cpha; + spi-cpol; + + vdd-supply =3D <&dummyreg>; + iovdd-supply =3D <&dummyreg>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + gpio-controller; + #gpio-cells =3D <2>; + + channel@0 { + reg =3D <0>; + }; + channel@1 { + reg =3D <1>; + }; + channel@2 { + reg =3D <2>; + }; + channel@16 { + reg =3D <16>; + }; + channel@20 { + reg =3D <20>; + }; + }; + }; --=20 2.51.0 --C43v0lf9gbjbyPJ9 Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCgAdFiEEIx+f8wZb28fLKEhTeFA3/03aocUFAmjHvFoACgkQeFA3/03a ocWJhQf/aLfWbTiT1P8QC0ouMUYc5UR6otQWOr3Q8R8TZWxp32yNu3E2xYUIDEod PsZspw7gASfNsoMCU44kvCJcGwqgp9xevprySzPzCz1RDMObi90o+yYGa7RZNujt XSPA/GwgCqGLOv+BeXldOiT2NmVNcZTYybC6dMkvk0QKQsboAwnY5Tz2JSNaDUEj z9KkjchiGMvg/JyDYZV93bz0TrDPKUCE2iOPXU42WWFJxQU5cwBjWcZI/WnQ96qb tANBnEkiHYXrpapuANPxBejKUaYlv6ADFuEFgB1tYkcHr0Tb1GN8PtR0GD1MWr3Q PtVfuq7kRBGJ9MuBh8OoQAh1P1GI7w== =sn/E -----END PGP SIGNATURE----- --C43v0lf9gbjbyPJ9-- From nobody Thu Oct 2 15:33:04 2025 Received: from mail-lf1-f45.google.com (mail-lf1-f45.google.com [209.85.167.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95B032D2491 for ; Mon, 15 Sep 2025 07:12:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757920374; cv=none; b=l0z6NRhnMTDYcNy0ISIqjhhgLPzGaRIiC7bBgAKRRvMZ0wTgZo9VfB0GZGidcF3eqvsOLXubPkgnWPGHFKasnWRqjxSVSK6Wj+BHJ7nD7k4L4oQkEpLmfmyPvK8NS/GXD7nzz3Ya0NJO6s0Zwd40lGK8U3pWG5O6rNdDfzfWbMs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757920374; c=relaxed/simple; bh=d4DOAmhQ/zWM7N5d8zhXOncd6up2q432TwTde42kAME=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=s6n+ArPmjpcUmm0XvTuCpwbZz1+gBPiN2gPjHf0nFWtR/YyuCv+ooiVQ+J6GF6f+HBCQy3hu+QLfQ9J6GHOQkC3NOkqcXfzdgwLaOMXeQx9bjenb/4vfP+A9JBri+dQ3obUfisx2pbmh7DddNhRsaTfUXqr9nZytSpcP+x2rDfM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=UsATyPyU; arc=none smtp.client-ip=209.85.167.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="UsATyPyU" Received: by mail-lf1-f45.google.com with SMTP id 2adb3069b0e04-560888dc903so4622900e87.2 for ; Mon, 15 Sep 2025 00:12:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1757920370; x=1758525170; darn=vger.kernel.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=cGqDZmAFJZ2MeJadIvWxYXKHkuiaKbqgyPd2MUCUbVA=; b=UsATyPyU4Sk9CkGh2Bl3IskYG3Jmi04IB1gVnYqHZX0ABcJLENodUQ8XzegeFlWSDS qFeLD/9UdEOxz9klCTuTmdH2aHI/qYpFw/NUZMJYCV0Xhhffrx2m+1rJs9dJKMhCneZM mz/PIp3w8SMUrkWC9+iTDDWA/v35kinV8+lQyhfuONmvUohQfXiRmp8zuTqIWG/IkwFX ujRDNfBS2zN0IAqiGcMZQ9kg4qOE/cnfWUtA2QMzGwgkqDof9h7I07MrAGuMONKNpsZ9 V0Vp6iIrfuSEZBrXtsQK+35iq0zUqVtRBE+dGsrADdVpao+2wd7rV1xYVaUrkTnxC4yu U7Yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757920370; x=1758525170; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=cGqDZmAFJZ2MeJadIvWxYXKHkuiaKbqgyPd2MUCUbVA=; b=o3kGbQOtMWYSU6d82Y2U7TrDd9dOnOU8X1Iqh/Olv6C2kRFq+bwnq5bCqgK1xCGZyE nGePFW3DYKI7mxbvc+awKBz9EQxMiTETnSxUrimv6byeyh7uP2CuxzFhsbjzNy1eE0t9 90rntAGx8C3A30iTcr6s6f2FEwxkvfHienSwIDs0+a1clABfFhoOesz85usQhwWMITVm ZZk4CXiK9nuL8FOjRhBuEknL4qgQwycofh9CsiR+AZRnoCaSST1eJrNHgJ9bgHHZps5T m4iif6nuv+KOjFV1sYp9ufymvBaBc8K+q63E1zg/KArk8/R7uOuTE/IkeXatImYm57t2 NW6Q== X-Forwarded-Encrypted: i=1; AJvYcCV8GuOAbh6UASViZ6EyPnxRcNIxzq6QHoQgMpOhMsJDGYiZwHSNNDtZWZ3Au50xfVQtNkPQty36VsAk20s=@vger.kernel.org X-Gm-Message-State: AOJu0Yz/scmzqrZOv3/esERC+KEHR+hbF4hGJmbVvfozmapKqpr49cHP QTL0uky/dKG1aJggZ0vHuen9rDMvL2mj8LJeRBqMnvr/CG4rdoojXfVt X-Gm-Gg: ASbGncsdqW7sq0IBCD1S3uAnDhtUBsgTa5CXGnEMiiI/kKjMLq+r1YpRlyuVMUGe7Bs aVZnQHpEV3CcY2F5ZRwJs9sP98L3c639omb3I2lqeG1yyISrZnWp+cxJnB7sy0nZUcb7BwX1WDy 1wa95A1Aml9xhA3mwoEDv0ORSBwlMBxkGzvyfVOGZlUEaLNcGW1lz0N0uVYpEGG3sMJXnzLERY4 90NtVxu0u0ijdtD6Z4zUTLNN8x0WDnl4E/aDM/yQmju2/CbKFrBdvuHJ/WNTPRhg4wNpq9c3Kuo 6wTGjikjODR8YvBbDeWt6memlfocU364jNv3hhk2SxfLX2DHi3FOWWGhyR7Z5T6mpv7r4dSDDW8 6hVdzuB/NoYNovk8UZZwPcNmQuO2Iu3E9EXomS1uDWESF1ME= X-Google-Smtp-Source: AGHT+IHGOSBv+aqKsqFORjzcdqTmRl/KvlE4X2ujT2GOdURXKu2LjWGzbp8qK9/6k45/511Ma9i+1g== X-Received: by 2002:a05:6512:3043:b0:560:956e:4392 with SMTP id 2adb3069b0e04-570489fca64mr3398591e87.9.1757920369338; Mon, 15 Sep 2025 00:12:49 -0700 (PDT) Received: from mva-rohm ([213.255.186.37]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-56e6460d741sm3415054e87.101.2025.09.15.00.12.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Sep 2025 00:12:48 -0700 (PDT) Date: Mon, 15 Sep 2025 10:12:43 +0300 From: Matti Vaittinen To: Jonathan Cameron , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matti Vaittinen , Linus Walleij , Bartosz Golaszewski Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH v5 2/3] iio: adc: Support ROHM BD79112 ADC/GPIO Message-ID: <20250915-bd79112-v5-2-a74e011a0560@gmail.com> References: <20250915-bd79112-v5-0-a74e011a0560@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="Iw1KzgU7X+s1ipVg" Content-Disposition: inline In-Reply-To: <20250915-bd79112-v5-0-a74e011a0560@gmail.com> X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=20067; i=mazziesaccount@gmail.com; h=from:subject:message-id; bh=+e4+ukZoY7b61V7Hvl7SwI9xaxAbyoLENd1sZI8UYLA=; b=owEBbQGS/pANAwAKAXhQN/9N2qHFAcsmYgBox7tkYQjv98fPddjPhmDc0Z0wvGvT6Us8yBl8f kqxrA1QSq+JATMEAAEKAB0WIQQjH5/zBlvbx8soSFN4UDf/TdqhxQUCaMe7ZAAKCRB4UDf/Tdqh xTy3CADIRl2xVzcSdAqcIjnUfu+QiwD/DNRLKuvexy5i+EamGjMfEyoSfKKc4yG/vPkZGh+Bg7q rf2ENaMJjNHqQIdCc6JAvua0W1HY3rKq3imMj4guzjOiBOYxTNDRs7F5hl23r0m0s7/ggCxhXw4 r4q71/c/fwRHk/N/DPRuPauSZLfYtpJr4QY9owBUitbSbFOwAKhfyxQvaIe64XehZuwa8VPXNAn HlKxNThjufUUSJGTIfmpm0dvRD9oZ864XiVBBF19QFnsF3bj+llk1GKwZOgj/MxkoBJo17La76d EeVrimTvRpzxKgCjLrQyvNfBEh2aQXyzppggXq8S6VQO4BYo X-Developer-Key: i=mazziesaccount@gmail.com; a=openpgp; fpr=83351EE69759B11AF0A3107B40497F0C4693EF47 --Iw1KzgU7X+s1ipVg Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ROHM BD79112 is an ADC/GPIO with 32 channels. The channel inputs can be used as ADC or GPIO. Using the GPIOs as IRQ sources isn't supported. The ADC is 12-bit, supporting input voltages up to 5.7V, and separate I/O voltage supply. Maximum SPI clock rate is 20 MHz (10 MHz with daisy-chain configuration) and maximum sampling rate is 1MSPS. The IC does also support CRC but it is not implemented in the driver. Signed-off-by: Matti Vaittinen --- Revision history: v4 =3D> v5: - improve ADC read doc - drop debug check from the read function - styling - optimize SPI messages v3 =3D> v4: - Fix Kconfig dependency (I2C =3D> SPI) - Styling as suggested by Andy and Jonathan - Moved I/O documentation comment and read/write functions next to each other and tried clarifying the comment v2 =3D> v3: (mainly based on review by Andy, thanks!) - fix broken indentiation - re-order includes - drop useless < 0 check for an unsigned offset - use gc->ngpios instead of hard coded pincount in for_each_set_clump8() - drop useless check for zero mask inside for_each_set_clump8() body - reorder return value checks for the devm_iio_adc_device_alloc_chaninfo_se() as suggested by Andy. (Well, I am not 100% happy with it as it results an extra check in the hopefully most common 'success' -case. But yeah, probe is not exactly a fast path). v1 =3D> v2 (mainly based on reviews by Andy and David, thanks!) - Fix Kconfig dependency to REGMAP_SPI instead of REGMAP_I2C - Add a few header includes - Drop unnecessary alignments - plenty of styling - use for_each_set_clump8 instead of open-coding it - change order of direction setting writes to avoid receiving 'event' when direction is changed from input to output. - fix data-sheet names and assigning of them to iio_dev --- drivers/iio/adc/Kconfig | 10 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/rohm-bd79112.c | 550 +++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 561 insertions(+) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index e3d3826c335714652726f012018aa5ecb9124a6d..984246b6f57f34e8c097fb92b59= df158dd2a14a4 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -1309,6 +1309,16 @@ config RN5T618_ADC This driver can also be built as a module. If so, the module will be called rn5t618-adc. =20 +config ROHM_BD79112 + tristate "Rohm BD79112 ADC driver" + depends on SPI && GPIOLIB + select REGMAP_SPI + select IIO_ADC_HELPER + help + Say yes here to build support for the ROHM BD79112 ADC. The + ROHM BD79112 is a 12-bit, 32-channel, SAR ADC. Analog inputs + can also be used for GPIO. + config ROHM_BD79124 tristate "Rohm BD79124 ADC driver" depends on I2C diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index 89d72bf9ce70ac1e225fbef83a83dd1a13aef27c..34b40c34cf7191c3367c6c57dca= d6d1dbe374824 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -117,6 +117,7 @@ obj-$(CONFIG_QCOM_VADC_COMMON) +=3D qcom-vadc-common.o obj-$(CONFIG_RCAR_GYRO_ADC) +=3D rcar-gyroadc.o obj-$(CONFIG_RICHTEK_RTQ6056) +=3D rtq6056.o obj-$(CONFIG_RN5T618_ADC) +=3D rn5t618-adc.o +obj-$(CONFIG_ROHM_BD79112) +=3D rohm-bd79112.o obj-$(CONFIG_ROHM_BD79124) +=3D rohm-bd79124.o obj-$(CONFIG_ROCKCHIP_SARADC) +=3D rockchip_saradc.o obj-$(CONFIG_RZG2L_ADC) +=3D rzg2l_adc.o diff --git a/drivers/iio/adc/rohm-bd79112.c b/drivers/iio/adc/rohm-bd79112.c new file mode 100644 index 0000000000000000000000000000000000000000..b406d4ee54119429e891a594749= 9c2c9155a0aae --- /dev/null +++ b/drivers/iio/adc/rohm-bd79112.c @@ -0,0 +1,550 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * ROHM ADC driver for BD79112 signal monitoring hub. + * Copyright (C) 2025, ROHM Semiconductor. + * + * SPI communication derived from ad7923.c and ti-ads7950.c + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define BD79112_MAX_NUM_CHANNELS 32 + +struct bd79112_data { + struct spi_device *spi; + struct regmap *map; + struct device *dev; + struct gpio_chip gc; + unsigned long gpio_valid_mask; + unsigned int vref_mv; + struct spi_transfer read_xfer[2]; + struct spi_transfer write_xfer; + struct spi_message read_msg; + struct spi_message write_msg; + /* 16-bit TX, valid data in high byte */ + u8 read_tx[2] __aligned(IIO_DMA_MINALIGN); + /* 8-bit address followed by 8-bit data */ + u8 reg_write_tx[2]; + /* 12-bit of ADC data or 8 bit of reg data */ + __be16 read_rx; +}; + +/* + * The ADC data is read issuing SPI-command matching the channel number. + * We treat this as a register address. + */ +#define BD79112_REG_AGIO0A 0x00 +#define BD79112_REG_AGIO15B 0x1f + +/* + * ADC STATUS_FLAG appended to ADC data will be set, if the ADC result is = being + * read for a channel, which input pin is muxed to be a GPIO. + */ +#define BD79112_ADC_STATUS_FLAG BIT(14) + +/* + * The BD79112 requires "R/W bit" to be set for SPI register (not ADC data) + * reads and an "IOSET bit" to be set for read/write operations (which are= n't + * reading the ADC data). + */ +#define BD79112_BIT_RW BIT(4) +#define BD79112_BIT_IO BIT(5) + +#define BD79112_REG_GPI_VALUE_B8_15 (BD79112_BIT_IO | 0x0) +#define BD79112_REG_GPI_VALUE_B0_B7 (BD79112_BIT_IO | 0x1) +#define BD79112_REG_GPI_VALUE_A8_15 (BD79112_BIT_IO | 0x2) +#define BD79112_REG_GPI_VALUE_A0_A7 (BD79112_BIT_IO | 0x3) + +#define BD79112_REG_GPI_EN_B7_B15 (BD79112_BIT_IO | 0x4) +#define BD79112_REG_GPI_EN_B0_B7 (BD79112_BIT_IO | 0x5) +#define BD79112_REG_GPI_EN_A8_A15 (BD79112_BIT_IO | 0x6) +#define BD79112_REG_GPI_EN_A0_A7 (BD79112_BIT_IO | 0x7) + +#define BD79112_REG_GPO_EN_B7_B15 (BD79112_BIT_IO | 0x8) +#define BD79112_REG_GPO_EN_B0_B7 (BD79112_BIT_IO | 0x9) +#define BD79112_REG_GPO_EN_A8_A15 (BD79112_BIT_IO | 0xa) +#define BD79112_REG_GPO_EN_A0_A7 (BD79112_BIT_IO | 0xb) + +#define BD79112_NUM_GPIO_EN_REGS 8 +#define BD79112_FIRST_GPIO_EN_REG BD79112_REG_GPI_EN_B7_B15 + +#define BD79112_REG_GPO_VALUE_B8_15 (BD79112_BIT_IO | 0xc) +#define BD79112_REG_GPO_VALUE_B0_B7 (BD79112_BIT_IO | 0xd) +#define BD79112_REG_GPO_VALUE_A8_15 (BD79112_BIT_IO | 0xe) +#define BD79112_REG_GPO_VALUE_A0_A7 (BD79112_BIT_IO | 0xf) + +#define BD79112_REG_MAX BD79112_REG_GPO_VALUE_A0_A7 + +/* + * Read transaction consists of two 16-bit sequences separated by CSB. + * For register read, 'IOSET' bit must be set. For ADC read, IOSET is clea= red + * and ADDR equals the channel number (0 ... 31). + * + * First 16-bit sequence, MOSI as below, MISO data ignored: + * - SCK: | 1 | 2 | 3 | 4 | 5 .. 8 | 9 .. 16 | + * - MOSI:| 0 | 0 | IOSET | RW (1) | ADDR | 8'b0 | + * + * CSB released and re-acquired between these sequences + * + * Second 16-bit sequence, MISO as below, MOSI data ignored: + * For Register read data is 8 bits: + * - SCK: | 1 .. 8 | 9 .. 16 | + * - MISO:| 8'b0 | 8-bit data | + * + * For ADC read data is 12 bits: + * - SCK: | 1 | 2 | 3 4 | 4 .. 16 | + * - MISO:| 0 | STATUS_FLAG | 2'b0 | 12-bit data | + * The 'STATUS_FLAG' is set if the read input pin was configured as a = GPIO. + */ +static int bd79112_reg_read(void *context, unsigned int reg, unsigned int = *val) +{ + struct bd79112_data *data =3D context; + int ret; + + if (reg & BD79112_BIT_IO) + reg |=3D BD79112_BIT_RW; + + data->read_tx[0] =3D reg; + + ret =3D spi_sync(data->spi, &data->read_msg); + if (!ret) + *val =3D be16_to_cpu(data->read_rx); + + return ret; +} + +/* + * Write, single 16-bit sequence (broken down below): + * + * First 8-bit, MOSI as below, MISO data ignored: + * - SCK: | 1 | 2 | 3 | 4 | 5 .. 8 | + * - MOSI:| 0 | 0 |IOSET| RW(0) | ADDR | + * + * Last 8 SCK cycles (b8 ... b15), MISO contains register data, MOSI ignor= ed. + * - SCK: | 9 .. 16 | + * - MISO:| data | + */ +static int bd79112_reg_write(void *context, unsigned int reg, unsigned int= val) +{ + struct bd79112_data *data =3D context; + + data->reg_write_tx[0] =3D reg; + data->reg_write_tx[1] =3D val; + + return spi_sync(data->spi, &data->write_msg); +} + +static int _get_gpio_reg(unsigned int offset, unsigned int base) +{ + int regoffset =3D offset / 8; + + if (offset > 31) + return -EINVAL; + + return base - regoffset; +} + +#define GET_GPIO_BIT(offset) BIT((offset) % 8) +#define GET_GPO_EN_REG(offset) _get_gpio_reg((offset), BD79112_REG_GPO_EN= _A0_A7) +#define GET_GPI_EN_REG(offset) _get_gpio_reg((offset), BD79112_REG_GPI_EN= _A0_A7) +#define GET_GPO_VAL_REG(offset) _get_gpio_reg((offset), BD79112_REG_GPO_V= ALUE_A0_A7) +#define GET_GPI_VAL_REG(offset) _get_gpio_reg((offset), BD79112_REG_GPI_V= ALUE_A0_A7) + +static const struct regmap_range bd71815_volatile_ro_ranges[] =3D { + { + /* Read ADC data */ + .range_min =3D BD79112_REG_AGIO0A, + .range_max =3D BD79112_REG_AGIO15B, + }, { + /* GPI state */ + .range_min =3D BD79112_REG_GPI_VALUE_B8_15, + .range_max =3D BD79112_REG_GPI_VALUE_A0_A7, + }, +}; + +static const struct regmap_access_table bd79112_volatile_regs =3D { + .yes_ranges =3D &bd71815_volatile_ro_ranges[0], + .n_yes_ranges =3D ARRAY_SIZE(bd71815_volatile_ro_ranges), +}; + +static const struct regmap_access_table bd79112_ro_regs =3D { + .no_ranges =3D &bd71815_volatile_ro_ranges[0], + .n_no_ranges =3D ARRAY_SIZE(bd71815_volatile_ro_ranges), +}; + +static const struct regmap_config bd79112_regmap =3D { + .reg_read =3D bd79112_reg_read, + .reg_write =3D bd79112_reg_write, + .volatile_table =3D &bd79112_volatile_regs, + .wr_table =3D &bd79112_ro_regs, + .cache_type =3D REGCACHE_MAPLE, + .max_register =3D BD79112_REG_MAX, +}; + +static int bd79112_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, + int *val2, long m) +{ + struct bd79112_data *data =3D iio_priv(indio_dev); + int ret; + + switch (m) { + case IIO_CHAN_INFO_RAW: + ret =3D regmap_read(data->map, chan->channel, val); + if (ret < 0) + return ret; + + return IIO_VAL_INT; + + case IIO_CHAN_INFO_SCALE: + *val =3D data->vref_mv; + *val2 =3D 12; + + return IIO_VAL_FRACTIONAL_LOG2; + default: + return -EINVAL; + } +} + +static const struct iio_info bd79112_info =3D { + .read_raw =3D bd79112_read_raw, +}; + +static const struct iio_chan_spec bd79112_chan_template =3D { + .type =3D IIO_VOLTAGE, + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), + .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE), + .indexed =3D 1, +}; + +static int bd79112_gpio_init_valid_mask(struct gpio_chip *gc, + unsigned long *valid_mask, + unsigned int ngpios) +{ + struct bd79112_data *data =3D gpiochip_get_data(gc); + + *valid_mask =3D data->gpio_valid_mask; + + return 0; +} + +static int bd79112_gpio_dir_get(struct gpio_chip *gc, unsigned int offset) +{ + struct bd79112_data *data =3D gpiochip_get_data(gc); + unsigned int reg, bit, val; + int ret; + + bit =3D GET_GPIO_BIT(offset); + reg =3D GET_GPO_EN_REG(offset); + + ret =3D regmap_read(data->map, reg, &val); + if (ret) + return ret; + + if (bit & val) + return GPIO_LINE_DIRECTION_OUT; + + reg =3D GET_GPI_EN_REG(offset); + ret =3D regmap_read(data->map, reg, &val); + if (ret) + return ret; + + if (bit & val) + return GPIO_LINE_DIRECTION_IN; + + /* + * Ouch. Seems the pin is ADC input - shouldn't happen as changing mux + * at runtime is not supported and non GPIO pins should be invalidated + * by the valid_mask at probe. Maybe someone wrote a register bypassing + * the driver? + */ + dev_err(data->dev, "Pin not a GPIO\n"); + + return -EINVAL; +} + +static int bd79112_gpio_get(struct gpio_chip *gc, unsigned int offset) +{ + struct bd79112_data *data =3D gpiochip_get_data(gc); + unsigned int reg, bit, val; + int ret; + + bit =3D GET_GPIO_BIT(offset); + reg =3D GET_GPI_VAL_REG(offset); + + ret =3D regmap_read(data->map, reg, &val); + if (ret) + return ret; + + return !!(val & bit); +} + +static int bd79112_gpio_set(struct gpio_chip *gc, unsigned int offset, + int value) +{ + struct bd79112_data *data =3D gpiochip_get_data(gc); + unsigned int reg, bit; + + bit =3D GET_GPIO_BIT(offset); + reg =3D GET_GPO_VAL_REG(offset); + + return regmap_assign_bits(data->map, reg, bit, value); +} + +static int bd79112_gpio_set_multiple(struct gpio_chip *gc, unsigned long *= mask, + unsigned long *bits) +{ + struct bd79112_data *data =3D gpiochip_get_data(gc); + unsigned long i, bank_mask; + + for_each_set_clump8(i, bank_mask, mask, gc->ngpio) { + unsigned long bank_bits; + unsigned int reg; + int ret; + + bank_bits =3D bitmap_get_value8(bits, i); + reg =3D BD79112_REG_GPO_VALUE_A0_A7 - i / 8; + ret =3D regmap_update_bits(data->map, reg, bank_mask, bank_bits); + if (ret) + return ret; + } + + return 0; +} + +static int bd79112_gpio_dir_set(struct bd79112_data *data, unsigned int of= fset, + int dir) +{ + unsigned int gpi_reg, gpo_reg, bit; + int ret; + + bit =3D GET_GPIO_BIT(offset); + gpi_reg =3D GET_GPI_EN_REG(offset); + gpo_reg =3D GET_GPO_EN_REG(offset); + + if (dir =3D=3D GPIO_LINE_DIRECTION_OUT) { + ret =3D regmap_clear_bits(data->map, gpi_reg, bit); + if (ret) + return ret; + + return regmap_set_bits(data->map, gpo_reg, bit); + } + + ret =3D regmap_set_bits(data->map, gpi_reg, bit); + if (ret) + return ret; + + return regmap_clear_bits(data->map, gpo_reg, bit); +} + +static int bd79112_gpio_input(struct gpio_chip *gc, unsigned int offset) +{ + struct bd79112_data *data =3D gpiochip_get_data(gc); + + return bd79112_gpio_dir_set(data, offset, GPIO_LINE_DIRECTION_IN); +} + +static int bd79112_gpio_output(struct gpio_chip *gc, unsigned int offset, + int value) +{ + struct bd79112_data *data =3D gpiochip_get_data(gc); + int ret; + + ret =3D bd79112_gpio_set(gc, offset, value); + if (ret) + return ret; + + return bd79112_gpio_dir_set(data, offset, GPIO_LINE_DIRECTION_OUT); +} + +static const struct gpio_chip bd79112_gpio_chip =3D { + .label =3D "bd79112-gpio", + .get_direction =3D bd79112_gpio_dir_get, + .direction_input =3D bd79112_gpio_input, + .direction_output =3D bd79112_gpio_output, + .get =3D bd79112_gpio_get, + .set =3D bd79112_gpio_set, + .set_multiple =3D bd79112_gpio_set_multiple, + .init_valid_mask =3D bd79112_gpio_init_valid_mask, + .can_sleep =3D true, + .ngpio =3D 32, + .base =3D -1, +}; + +static unsigned int bd79112_get_gpio_pins(const struct iio_chan_spec *cs, = int num_channels) +{ + unsigned int i, gpio_channels; + + /* + * Let's initialize the mux config to say that all 32 channels are + * GPIOs. Then we can just loop through the iio_chan_spec and clear the + * bits for found ADC channels. + */ + gpio_channels =3D GENMASK(31, 0); + for (i =3D 0; i < num_channels; i++) + gpio_channels &=3D ~BIT(cs[i].channel); + + return gpio_channels; +} + +/* ADC channels as named in the data-sheet */ +static const char * const bd79112_chan_names[] =3D { + "AGIO0A", "AGIO1A", "AGIO2A", "AGIO3A", /* 0 - 3 */ + "AGIO4A", "AGIO5A", "AGIO6A", "AGIO7A", /* 4 - 7 */ + "AGIO8A", "AGIO9A", "AGIO10A", "AGIO11A", /* 8 - 11 */ + "AGIO12A", "AGIO13A", "AGIO14A", "AGIO15A", /* 12 - 15 */ + "AGIO0B", "AGIO1B", "AGIO2B", "AGIO3B", /* 16 - 19 */ + "AGIO4B", "AGIO5B", "AGIO6B", "AGIO7B", /* 20 - 23 */ + "AGIO8B", "AGIO9B", "AGIO10B", "AGIO11B", /* 24 - 27 */ + "AGIO12B", "AGIO13B", "AGIO14B", "AGIO15B", /* 28 - 31 */ +}; + +static int bd79112_probe(struct spi_device *spi) +{ + struct bd79112_data *data; + struct iio_dev *iio_dev; + struct iio_chan_spec *cs; + struct device *dev =3D &spi->dev; + unsigned long gpio_pins, pin; + unsigned int i; + int ret; + + iio_dev =3D devm_iio_device_alloc(dev, sizeof(*data)); + if (!iio_dev) + return -ENOMEM; + + data =3D iio_priv(iio_dev); + data->spi =3D spi; + data->dev =3D dev; + data->map =3D devm_regmap_init(dev, NULL, data, &bd79112_regmap); + if (IS_ERR(data->map)) + return dev_err_probe(dev, PTR_ERR(data->map), + "Failed to initialize Regmap\n"); + + ret =3D devm_regulator_get_enable_read_voltage(dev, "vdd"); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to get the Vdd\n"); + + data->vref_mv =3D ret / 1000; + + ret =3D devm_regulator_get_enable(dev, "iovdd"); + if (ret < 0) + return dev_err_probe(dev, ret, "Failed to enable I/O voltage\n"); + + data->read_xfer[0].tx_buf =3D &data->read_tx[0]; + data->read_xfer[0].len =3D sizeof(data->read_tx); + data->read_xfer[0].cs_change =3D 1; + data->read_xfer[1].rx_buf =3D &data->read_rx; + data->read_xfer[1].len =3D sizeof(data->read_rx); + spi_message_init_with_transfers(&data->read_msg, data->read_xfer, 2); + devm_spi_optimize_message(dev, spi, &data->read_msg); + + data->write_xfer.tx_buf =3D &data->reg_write_tx[0]; + data->write_xfer.len =3D sizeof(data->reg_write_tx); + spi_message_init_with_transfers(&data->write_msg, &data->write_xfer, 1); + devm_spi_optimize_message(dev, spi, &data->write_msg); + + ret =3D devm_iio_adc_device_alloc_chaninfo_se(dev, &bd79112_chan_template, + BD79112_MAX_NUM_CHANNELS - 1, + &cs); + + /* Register all pins as GPIOs if there are no ADC channels */ + if (ret =3D=3D -ENOENT) + goto register_gpios; + + if (ret < 0) + return ret; + + iio_dev->num_channels =3D ret; + iio_dev->channels =3D cs; + + for (i =3D 0; i < iio_dev->num_channels; i++) + cs[i].datasheet_name =3D bd79112_chan_names[cs[i].channel]; + + iio_dev->info =3D &bd79112_info; + iio_dev->name =3D "bd79112"; + iio_dev->modes =3D INDIO_DIRECT_MODE; + + /* + * Ensure all channels are ADCs. This allows us to register the IIO + * device early (before checking which pins are to be used for GPIO) + * without having to worry about some pins being initially used for + * GPIO. + */ + for (i =3D 0; i < BD79112_NUM_GPIO_EN_REGS; i++) { + ret =3D regmap_write(data->map, BD79112_FIRST_GPIO_EN_REG + i, 0); + if (ret) + return dev_err_probe(dev, ret, + "Failed to initialize channels\n"); + } + + ret =3D devm_iio_device_register(data->dev, iio_dev); + if (ret) + return dev_err_probe(data->dev, ret, "Failed to register ADC\n"); + +register_gpios: + gpio_pins =3D bd79112_get_gpio_pins(iio_dev->channels, + iio_dev->num_channels); + + /* If all channels are reserved for ADC, then we're done. */ + if (!gpio_pins) + return 0; + + /* Default all the GPIO pins to GPI */ + for_each_set_bit(pin, &gpio_pins, BD79112_MAX_NUM_CHANNELS) { + ret =3D bd79112_gpio_dir_set(data, pin, GPIO_LINE_DIRECTION_IN); + if (ret) + return dev_err_probe(dev, ret, + "Failed to mark pin as GPI\n"); + } + + data->gpio_valid_mask =3D gpio_pins; + data->gc =3D bd79112_gpio_chip; + data->gc.parent =3D dev; + + return devm_gpiochip_add_data(dev, &data->gc, data); +} + +static const struct of_device_id bd79112_of_match[] =3D { + { .compatible =3D "rohm,bd79112" }, + { } +}; +MODULE_DEVICE_TABLE(of, bd79112_of_match); + +static const struct spi_device_id bd79112_id[] =3D { + { "bd79112" }, + { } +}; +MODULE_DEVICE_TABLE(spi, bd79112_id); + +static struct spi_driver bd79112_driver =3D { + .driver =3D { + .name =3D "bd79112", + .of_match_table =3D bd79112_of_match, + }, + .probe =3D bd79112_probe, + .id_table =3D bd79112_id, +}; +module_spi_driver(bd79112_driver); + +MODULE_AUTHOR("Matti Vaittinen "); +MODULE_DESCRIPTION("Driver for ROHM BD79112 ADC/GPIO"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("IIO_DRIVER"); --=20 2.51.0 --Iw1KzgU7X+s1ipVg Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCgAdFiEEIx+f8wZb28fLKEhTeFA3/03aocUFAmjHvGsACgkQeFA3/03a ocVLdQf9Hw0jCPYRGbx9c7oewUXy7QCvrLXjo20uOp04Hg2ubjmfQx5Ov3DEOqVx 4vFXooVxD/BLDwS7ZGuF+Vk9lMIi1xximmA4QjsAsIsLKKKtpoxpJ99GL1nZqKIh K74/mUZFuPifQz3f9Gv8ebvz0XTYkJ5UC4btXwjLCj+jVCrJldwnTEBpZNVtNMWC +tA2I6YUMBxO70UjZJsJzSNs/Su9nQWp3MXFJB8r4yPC/exaSTfGVW6Mqoeu/X0l u6cxwgt/6aO8ntagtg6Zbi3tNBXJ3wyLWt0uOJJv7IF3auyhnFYHAOHfZ1xN/1sB RxDxdu9NWq3rQARYy/eXf9QICW2IHA== =IKHA -----END PGP SIGNATURE----- --Iw1KzgU7X+s1ipVg-- From nobody Thu Oct 2 15:33:04 2025 Received: from mail-lj1-f177.google.com (mail-lj1-f177.google.com [209.85.208.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 504B22D24B0 for ; Mon, 15 Sep 2025 07:13:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757920386; cv=none; b=S/q1h8QL2DXwACygcN46he94VKiZWWS6ZcagpzxtcvHlGWaf4rzVfTGRf94dCc/Kfi/mggURz6ya/VB4pmtKNstKAd2be/fyXfKs3uWI6pil6VX8W9z/YsY4UnLBU83DHpcuMpvxstqJtJI9lscnEaxUWVwdd48MDzfRwXrCUkQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757920386; c=relaxed/simple; bh=L+O8dP+NoaSvco/dHI8EdGARObzbo2tfHErlsbYjBq8=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=kkxw1TCLmXZlWLHhM/LtweCrWRBL/l48S5miCUcf8c9c3jwAAcwYljhYX/wZKudsgXchAwpn8NvgBs1WJr3yx3v0TqomJHdPoMAHOaVURc5EECmGsxwMhkTy5tnjgVCHpovHxjaSnlPLJE9bIuOCzIcHzaR24x1LO6fixEu/frg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Jz6i/ODU; arc=none smtp.client-ip=209.85.208.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Jz6i/ODU" Received: by mail-lj1-f177.google.com with SMTP id 38308e7fff4ca-3515a0bca13so25984051fa.1 for ; Mon, 15 Sep 2025 00:13:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1757920382; x=1758525182; darn=vger.kernel.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=nperUovJGBRN4p1U9Cqmddf2EFz0RAhcOgsrNCHsdsk=; b=Jz6i/ODUvyDGBmdjft2+KcZlVeVSM/Fc2Fc9PEsfaf6iS0fLt++ffCOdlAAfsU54MY w9P0jfPUzsIUOUwW4eeP0nCKUbrU3VNiHhpV/2FBDHfBppliQ2te2F7CugJAXnMhlasX SPVMQReN/ncArY0PG8Q9RKP+2r25AcEehn7ztMeW3KVjPQrgi8CZ70tniiWtTmCQC/kC SmVvvRht2Sga+vajuPtOrUwcVyTALbXNuse2s/dNsGK3xzSvJUZVdUzMlfL1sM7X56ZK O2UgzLszFH8hGsu7aNoVCsIjG4rXXh2a+nJSdJT13f8A0AVl+034PCztgLxyUKTxpSRW 809g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757920382; x=1758525182; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=nperUovJGBRN4p1U9Cqmddf2EFz0RAhcOgsrNCHsdsk=; b=NgmbSohf0HIofwhIBwuzCWmY3EXCrWIXS4HfMk3Hgsg3m7p9o7jm6o/XijtwlvtzW7 fCkBQD5cEb8MSPNq51n5uPm7n/qgbhdu6Vpk6+P1ynt+m7GMvMSkrpPF1PvxFmQ1612s v7ThTaolNcCHbTk1+OwB0YaUAWh3UQuw5UM0C4jAvCXDzrib/yklC+C6xq8JwStniDpj MOIcCWA3WcaiKjsfeWSUf540TyWfQ0TzD/S5RsYQvZIQtRHMe4pxV0LrFkaQqoJHToZ8 fsYgFDCimJ6YPuqf+g127bIcwYP6mlF2n+SYc8gwWDKSd6hdo4YYIjJ5PAFT3ktkYggl NiaQ== X-Forwarded-Encrypted: i=1; AJvYcCUDbmupmb7baoptVt49hyjzOb0JtF+vOrvpl0cHnDwAuaHtVzT9LHCHd6GXLaXvgB1AawGzWCUJjN6HZCU=@vger.kernel.org X-Gm-Message-State: AOJu0YyTMBqavcew9e1ayjuNRLorwRXTwYQ9j3QzVL8HUT31wl24y5Zg rwYJaUy0x314e6oNALo4iDdT9Vfo7X6FrDG0953rUTTcNzdyKhLMKglE X-Gm-Gg: ASbGncvBpX3vKFf8W6dujYnZCGAtKn4Vc5UEvx1TtdUCwj953p3L3X6WqYASKP1rE/7 RZtieoEhoE9g17pRfR3BHuWHnaOSfnVEEfIxeb3RMJpqxDdPL8VgBgmoq04WzfkAnv2y3hSGdyg oPgJ9tzojXbcSLcKqKf0xfSVakuIzxadQDUfPmUmBNrfzT6S+CNjoh2T9dsnazi1YE4OQa2Rjhc rrQilLJbN4McG7eIFYURwOI0hGzpJIwjwHcZZ9EwGw2iKOgufS/pGAJD0P0h/Mu7BEo9PY+68+d G5zcsMe2Z/RE1lelhojMeo7Rsq24EmPI5dB6Fwovp7iepzbXD1qqZA428M9uXs7It2Fg6iX468H bCTSZJOHoB+cvfWCgU3f+PFum0w== X-Google-Smtp-Source: AGHT+IFtHLrp6nDSFIjlQ8dE2HKGNN3wt0ejQZEvh9/tOfDi0dZB1430X3qA0RvmHQEWq0Llk7+qyg== X-Received: by 2002:a05:651c:b08:b0:336:b891:18db with SMTP id 38308e7fff4ca-3511487945dmr38768791fa.2.1757920382159; Mon, 15 Sep 2025 00:13:02 -0700 (PDT) Received: from mva-rohm ([213.255.186.37]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-34f163f401bsm26932681fa.19.2025.09.15.00.13.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Sep 2025 00:13:01 -0700 (PDT) Date: Mon, 15 Sep 2025 10:12:57 +0300 From: Matti Vaittinen To: Jonathan Cameron , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matti Vaittinen , Linus Walleij , Bartosz Golaszewski Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH v5 3/3] MAINTAINERS: Support ROHM BD79112 ADC Message-ID: <20250915-bd79112-v5-3-a74e011a0560@gmail.com> References: <20250915-bd79112-v5-0-a74e011a0560@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="XriNK4zL7+BKWUIz" Content-Disposition: inline In-Reply-To: <20250915-bd79112-v5-0-a74e011a0560@gmail.com> X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=834; i=mazziesaccount@gmail.com; h=from:subject:message-id; bh=rWC+YvC4JADy5afIx4GhMrizCQAlp5Zfa8zbihvqrIk=; b=owEBbQGS/pANAwAKAXhQN/9N2qHFAcsmYgBox7tkfo4fS+eVy4+fm0x4lni07xLl1ttSIfNcY 1wz2X0eTTqJATMEAAEKAB0WIQQjH5/zBlvbx8soSFN4UDf/TdqhxQUCaMe7ZAAKCRB4UDf/Tdqh xUQiCACf3Q3fYUvZjJpHNsGrzfMpdlThHm0cZH+rHmuosrtAO7JJwN11DjrDxFYjYZdf435yWIg kj4pYcGCHfxuvJeUOsFWyOrvgh6e8LEDNM7iQImwSceBTfOZLrf+5AA1dy5Htd1QmLVcdkSK7Ay pRwG426FpwEgXmG+6cz1fPwl8QyufgeJ35fxtCPINDyHNrmGTvB2P73ei4gGX7MC+N8tQlhH7x9 I6ZCH4mOp0cb8fexzFZsKF8Uz2RRov8ioqDEaUn3IZPNSOFZDPzSWIC0QFzLsjfghdKAdapMNZK zADdXITkPVmYNOexupeOcT9B7Stf3qgVR1kF12xi5yNc426f X-Developer-Key: i=mazziesaccount@gmail.com; a=openpgp; fpr=83351EE69759B11AF0A3107B40497F0C4693EF47 --XriNK4zL7+BKWUIz Content-Disposition: inline Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add the ROHM BD79112 ADC in the list of the BD791xx ADC drivers which are maintained by undersigned. Signed-off-by: Matti Vaittinen --- Revision history: v1 =3D> : - no changes --- MAINTAINERS | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index af1c8d2bfb3deb870d8df44b8bae22e7cffb5aca..8e78a1168c17d8c2c7056e99e19= 1d542ef0b95a6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21864,9 +21864,10 @@ S: Supported F: drivers/power/supply/bd99954-charger.c F: drivers/power/supply/bd99954-charger.h =20 -ROHM BD79124 ADC / GPO IC +ROHM BD791xx ADC / GPO IC M: Matti Vaittinen S: Supported +F: drivers/iio/adc/rohm-bd79112.c F: drivers/iio/adc/rohm-bd79124.c =20 ROHM BH1745 COLOUR SENSOR --=20 2.51.0 --XriNK4zL7+BKWUIz Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iQEzBAEBCgAdFiEEIx+f8wZb28fLKEhTeFA3/03aocUFAmjHvHkACgkQeFA3/03a ocWGkQf7BApMorYRm2N9zKifAYTH7Y1kBZcVOy+cQU2kCWn9rHtkbmiv4lXOlCdW ijLitSt/W+g2gO4DxPFasUjMIexvrSK1e0YpEW9qr+p3ZrB3sRyRP0Dapt/QmaFH BmuO2kDObyfTS6yxKP0zk3TGVOY/AbJVpYVa2X3p7DRw3yQJfOx9F3VrETy4wkVb oZfz+pHgv3QdVaYdUVGpe1lmBuIF0xBtZkKi00TO/r9rsbON5k4mxxThdHzALTKK 2ckqzJIYRIOKXFmVlGdLjTSgn1DmURKzeSkwKP+JpCQApC31mSRZqppLufa5nyBd 1KyizdZHf1C0XaChOVGsKrPPzOdNXA== =KpM/ -----END PGP SIGNATURE----- --XriNK4zL7+BKWUIz--