From nobody Thu Oct 2 16:35:37 2025 Received: from mail-ed1-f53.google.com (mail-ed1-f53.google.com [209.85.208.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 046502749DA for ; Sun, 14 Sep 2025 17:16:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757870180; cv=none; b=Fr6dH0+cIfcP8EQ/8bZYxJ/HTzgmcI+WBBso0YIMpWGPnRj+Z1YhfEptkW8Trvrzmf68avPPm4fuU+QMMRm71nNiPeRVwXRI6wKvjYvGAKBUzzHPHUQbmXXDs64eHNGuCHpcQNEeI3GI4yN75SxEGc4uXqCJ12wBLX9jHxw96mI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757870180; c=relaxed/simple; bh=ipys+sa9gnvK/DvJjMtWh3ebWZIbOPBtZHEYTv7XZLI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sV0CVa8/Go12eyTsqVMS0cm79hXUi/OdYFuqUd2bCn9v3n5gr8sozo5+LE03D4/ZgMlYHNElU7EsbWGvYmycARsRqSwS6gjAl35z2Mdh0D4eUZqiz1eCjxkHozEEdat6yQuYtUh2MhIGDYcZg5hfCvL/maYmadhdfZzYMHN/2SU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=Nw5Jg+jb; arc=none smtp.client-ip=209.85.208.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="Nw5Jg+jb" Received: by mail-ed1-f53.google.com with SMTP id 4fb4d7f45d1cf-62f4273a404so127755a12.0 for ; Sun, 14 Sep 2025 10:16:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1757870177; x=1758474977; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=v0a/vjTQEtX+/yGwy3GQfrzKjZgyz27Pw8rW7Pi3j2A=; b=Nw5Jg+jbOFbWUksSwkY0mb6B6Q038Q5TZhYDW3v5l2psvaMLMN6unRyWC2LJNrxogc nznuaSqQAPkjfdGprabEvMHN0w1nXzuDdPgfqw0Cd9Uc5VPM7SdvaPVhXXJ2XNgt19co iq0FuX8HesrhSjhTP0GYm+ar7ToHiEALl5/zo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757870177; x=1758474977; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v0a/vjTQEtX+/yGwy3GQfrzKjZgyz27Pw8rW7Pi3j2A=; b=VB9+2dWUfjIYK7RyQmkUjmbI0iGD3n7q/g9AAKzAlr+TxyvHCNom38oSPYlHqMrpHL IfaKwzMkw7K1U3X83fgSH2egCsz+7RXgRjww+vCgd6XltqVgwFrQePx1eVJCfkV5hPyX rVv2EL6Nxd2SykOWt/X8Zhf6ZjoCEwQllnNy3mtDxjQBmSV2EnRpbShPq37ecjr0DUzV KmMiIu/DCT5Opz1TZqkXoSxHMYxrIfD6uZQ50m9W3esgjn2RHILWav0TwOfjeD/wi3S0 LAsWmLFeV9TcE+dZgKuT752BJ7v74+d0j3Q0LGHJ0eo+hFK2f3rWCKv8shFu8bEfBORZ kT9g== X-Gm-Message-State: AOJu0Yzf2/BlEhhMlyDdbHF5ZZsULaHzy0USivm8K4mleTtjAPLa83yh 9YUh7UazdEBhgEOqm0wL1h9okc80wfQDDZY7QyZgprQJM3CpSzhd4iD/2V3IaOvJXs77bNlAJtH YMnJe X-Gm-Gg: ASbGncvZ7a0nTgw7xg7bp/KECzQuj60hSg8jiGH5B36bEQquu6SCdtrO1VPtYagmlxO vzKC3WkrWERyednlaJhfSPtq+LIRDYVSGBWr3sl5gqpYt8U1n+el90Bi3l3egIoPBzOMkbHgEJy onAazUG3dHpYxccOd0U7YIQUDnIGyT6WKXEvyU2J7+f4mdHZY+7TefV1vIJ91cYdpKoHqfAchKs 1pQ6z7o+XO7EW1TajP0LVHPP5rhUMk4Dad65D/m8ZWbw50/nSlmHww+Kk+ngMcjEwQ091R4ybb6 jtunNxjWXlRYxNkAegbPvxeK8ad/cX8SqCIRRG7/oUTGvm1YGnVXOLdhZ2Q/ghle8wjegNhcL74 fdZQazB+6bN65vMB2ZEKD0QBj86eNY3tv6X9SETXzJROnU2Ib6NCQN+9Fefmvy2zY9hfK5H7Yea SONEUzyGbypFJ8+eNlp3Ba9K/Zk60b92iA2TLNJp522L/jpepZVFUx8iLe+KVmrirj X-Google-Smtp-Source: AGHT+IEvX+quO6ICKhJRdf8NKT/j6OYJ6Pe+ZtB6ww1NFEvD0skqRYkw1DUilScz0LuELvehDfDMmw== X-Received: by 2002:a17:907:971d:b0:b0c:7269:8459 with SMTP id a640c23a62f3a-b0c726986afmr363002766b.7.1757870177023; Sun, 14 Sep 2025 10:16:17 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-82-56-38-125.retail.telecomitalia.it. [82.56.38.125]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b07b334e76dsm776980466b.102.2025.09.14.10.16.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Sep 2025 10:16:16 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Frank Li , linux-amarula@amarulasolutions.com, Michael Trimarchi , Dario Binacchi , Dmitry Torokhov , Fabio Estevam , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org Subject: [PATCH v2 1/6] Input: imx6ul_tsc - fix typo in register name Date: Sun, 14 Sep 2025 19:15:58 +0200 Message-ID: <20250914171608.1050401-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250914171608.1050401-1-dario.binacchi@amarulasolutions.com> References: <20250914171608.1050401-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Michael Trimarchi Replace 'SETING' with 'SETTING'. Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi Reviewed-by: Frank Li --- Changes in v2: - Add Reviewed-by tag of Frank Li. drivers/input/touchscreen/imx6ul_tsc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/input/touchscreen/imx6ul_tsc.c b/drivers/input/touchsc= reen/imx6ul_tsc.c index 6ac8fa84ed9f..c2c6e50efc54 100644 --- a/drivers/input/touchscreen/imx6ul_tsc.c +++ b/drivers/input/touchscreen/imx6ul_tsc.c @@ -55,7 +55,7 @@ #define ADC_TIMEOUT msecs_to_jiffies(100) =20 /* TSC registers */ -#define REG_TSC_BASIC_SETING 0x00 +#define REG_TSC_BASIC_SETTING 0x00 #define REG_TSC_PRE_CHARGE_TIME 0x10 #define REG_TSC_FLOW_CONTROL 0x20 #define REG_TSC_MEASURE_VALUE 0x30 @@ -192,7 +192,7 @@ static void imx6ul_tsc_set(struct imx6ul_tsc *tsc) =20 basic_setting |=3D tsc->measure_delay_time << 8; basic_setting |=3D DETECT_4_WIRE_MODE | AUTO_MEASURE; - writel(basic_setting, tsc->tsc_regs + REG_TSC_BASIC_SETING); + writel(basic_setting, tsc->tsc_regs + REG_TSC_BASIC_SETTING); =20 writel(DE_GLITCH_2, tsc->tsc_regs + REG_TSC_DEBUG_MODE2); =20 --=20 2.43.0 From nobody Thu Oct 2 16:35:37 2025 Received: from mail-ej1-f43.google.com (mail-ej1-f43.google.com [209.85.218.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 657FA2DE6EF for ; Sun, 14 Sep 2025 17:16:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757870182; cv=none; b=Wx9o+xiZ4AE7v8nFsIrw3ilx+yg54hagOdV8s1mRwtW1RZ9X2Jvn+1esW7Ti6bOgLl895xFTbnBG7Cw/USzesi+2sol/6FMwmdavHadEIrmpQ2IfOesObjGKGAvB6miE+c9svE9y6fxJyvzmLmdZ1Va+dochhZdD3JCIGLAC+fY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757870182; c=relaxed/simple; bh=DAoeTCIIwwGqg9u3B1JkXfX42HpCsPKCXtkx/QE8BvU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VSv5EuIUYFxvZXUNFGBQWYeJe2gKD1cYv2TID2d6mPOp/H5VsCccPG5n0/1cNAmkokvlGNYbw04gpbHTykG6WJ2esZMc5lkxpW93mVqz/HOsTywazJ3a8gxgE21Sju0wPkp4sLCjikOjEDE8Bbfz+L8N2QyvtXeEFs7Mb2nqOzU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=UVSsZQlu; arc=none smtp.client-ip=209.85.218.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="UVSsZQlu" Received: by mail-ej1-f43.google.com with SMTP id a640c23a62f3a-b0e7bc49263so59071366b.1 for ; Sun, 14 Sep 2025 10:16:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1757870178; x=1758474978; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VnBZKBOJmiN67eQQM1Bf1khwvZJgal4hwMc9eP3h39w=; b=UVSsZQluv6vZS+LKZcxOEI5hXkPSN3YLg+GSh3dyveuv5+BsdGI0xj2oOYlYiRK+9l 7Zm/XIwP61IAYanmrAdt9WOZynGYx9NdNzjbqkgVDIZY7JVGv+fKtm9Mis9Iy/Rzcpsq 4kT3NcLJRbnI/7OfWIMHbQElmdKMpay5nZyP4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757870178; x=1758474978; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VnBZKBOJmiN67eQQM1Bf1khwvZJgal4hwMc9eP3h39w=; b=QSZbON2Bk8bzPKY24PQ5wY/96WRGG0vAn7PysGTWINQntFDYiMb6hK6z4nGjs1lWqw Lb+h8dqFFiZv2OJ+y3UWi8mog64KS9TCgrM3iMEqKEfA6Td/S1AWu0pWYzbci886Rs/X ZWNECI+rKYSBFDyxcptvhu5J6ekMvMNWj1kSkRPrfQvz2Re+E5utVyxH2AUCdpoZqKm1 QRnzCb6fypXBYa4AzQqaL9QpDP8+gQFPsKoAV0usThPSA1WkQJzjMh3KkNNA8JB6qoa0 iFSnHtqd5FB7rxrCMcwenB8PkwCkw19H4zmQ4OocRFDi34wOShGEjAIgT+bjITG63XRn 4eRw== X-Gm-Message-State: AOJu0YyXyx8XbJxpITwyRQAze1sRxCtNSG2+OaEGSknXSyVOFFVvDIKK Oya6AjYTcE4/Bgtda0lb1CEHGX4jifubYmEAgXqhSQqqMFHN55wKpTkrUbcKXKUsd/rxOevaHzj Y5oQY X-Gm-Gg: ASbGncsl7PEzEZ9HTT+sOiaagWCpCy3HzHhTVQkzWP3oQhTY0TKB6GEzzxCNBz8yssV obU5d/lZn+6+LRP51wz7y9nLddjP+r/SetSQibjQO/21dMji++wctDdYdGsPxJwXsarN0Kmmoly H07YgpK+gtlg0tsosriY1+/O8z0s7ctMymMdrGQzDkhkxiVFtV01egzcB7sudTM1Jzknli87DsX AW5HfkITfd1XqYeWQJBY5uxYl+b0awmvByXeC3jKzki9EbMpXGhtSjsxrHCwHMjXh68rlzoDvaT LhqvjOlGIZnEex3OvEC8fDe0NXwM/nL+Xs68ZeThYwQo3sTM8fIUwrOxQeFvUJkWS7gkhCJFjQ7 otUECGbwebNfrdW5XFMGam+CFtbL7gjOqWx+WeUX+umfKtfKtr5iBjvn7cvbKKfqsNqgrpaX1pT +AFXGfM/S1QvlgNLRtsw8iTXx9HDcN2peLxqK4RVxr6yXHpI7OFwQSsiTjw8qEJGww X-Google-Smtp-Source: AGHT+IGTu8BD4q01N7jRbGlEMQ6UMK1mwiKmfPW/m2RwIO0Ts7qqmSd+/c4Mm3Jym91bOgEHInMb0g== X-Received: by 2002:a17:907:2da2:b0:afd:d94b:830d with SMTP id a640c23a62f3a-b07c3a7b887mr976251766b.62.1757870178516; Sun, 14 Sep 2025 10:16:18 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-82-56-38-125.retail.telecomitalia.it. [82.56.38.125]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b07b334e76dsm776980466b.102.2025.09.14.10.16.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Sep 2025 10:16:18 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Frank Li , linux-amarula@amarulasolutions.com, Dario Binacchi , Dmitry Torokhov , Fabio Estevam , Michael Trimarchi , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org Subject: [PATCH v2 2/6] Input: imx6ul_tsc - use BIT, FIELD_{GET,PREP} and GENMASK macros Date: Sun, 14 Sep 2025 19:15:59 +0200 Message-ID: <20250914171608.1050401-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250914171608.1050401-1-dario.binacchi@amarulasolutions.com> References: <20250914171608.1050401-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace opencoded masking and shifting, with BIT(), GENMASK(), FIELD_GET() and FIELD_PREP() macros. Signed-off-by: Dario Binacchi Reviewed-by: Frank Li --- Changes in v2: - Add Reviewed-by tag of Frank Li. - Move the patch right after the one fixing the typo according to Frank Li's suggestions. drivers/input/touchscreen/imx6ul_tsc.c | 96 +++++++++++++++----------- 1 file changed, 54 insertions(+), 42 deletions(-) diff --git a/drivers/input/touchscreen/imx6ul_tsc.c b/drivers/input/touchsc= reen/imx6ul_tsc.c index c2c6e50efc54..e2c59cc7c82c 100644 --- a/drivers/input/touchscreen/imx6ul_tsc.c +++ b/drivers/input/touchscreen/imx6ul_tsc.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -20,25 +21,23 @@ #include =20 /* ADC configuration registers field define */ -#define ADC_AIEN (0x1 << 7) +#define ADC_AIEN BIT(7) +#define ADC_ADCH_MASK GENMASK(4, 0) #define ADC_CONV_DISABLE 0x1F -#define ADC_AVGE (0x1 << 5) -#define ADC_CAL (0x1 << 7) -#define ADC_CALF 0x2 -#define ADC_12BIT_MODE (0x2 << 2) -#define ADC_CONV_MODE_MASK (0x3 << 2) +#define ADC_AVGE BIT(5) +#define ADC_CAL BIT(7) +#define ADC_CALF BIT(1) +#define ADC_CONV_MODE_MASK GENMASK(3, 2) +#define ADC_12BIT_MODE 0x2 #define ADC_IPG_CLK 0x00 -#define ADC_INPUT_CLK_MASK 0x3 -#define ADC_CLK_DIV_8 (0x03 << 5) -#define ADC_CLK_DIV_MASK (0x3 << 5) -#define ADC_SHORT_SAMPLE_MODE (0x0 << 4) -#define ADC_SAMPLE_MODE_MASK (0x1 << 4) -#define ADC_HARDWARE_TRIGGER (0x1 << 13) -#define ADC_AVGS_SHIFT 14 -#define ADC_AVGS_MASK (0x3 << 14) +#define ADC_INPUT_CLK_MASK GENMASK(1, 0) +#define ADC_CLK_DIV_8 0x03 +#define ADC_CLK_DIV_MASK GENMASK(6, 5) +#define ADC_SAMPLE_MODE BIT(4) +#define ADC_HARDWARE_TRIGGER BIT(13) +#define ADC_AVGS_MASK GENMASK(15, 14) #define SELECT_CHANNEL_4 0x04 #define SELECT_CHANNEL_1 0x01 -#define DISABLE_CONVERSION_INT (0x0 << 7) =20 /* ADC registers */ #define REG_ADC_HC0 0x00 @@ -65,19 +64,26 @@ #define REG_TSC_DEBUG_MODE 0x70 #define REG_TSC_DEBUG_MODE2 0x80 =20 +/* TSC_MEASURE_VALUE register field define */ +#define X_VALUE_MASK GENMASK(27, 16) +#define Y_VALUE_MASK GENMASK(11, 0) + /* TSC configuration registers field define */ -#define DETECT_4_WIRE_MODE (0x0 << 4) -#define AUTO_MEASURE 0x1 -#define MEASURE_SIGNAL 0x1 -#define DETECT_SIGNAL (0x1 << 4) -#define VALID_SIGNAL (0x1 << 8) -#define MEASURE_INT_EN 0x1 -#define MEASURE_SIG_EN 0x1 -#define VALID_SIG_EN (0x1 << 8) -#define DE_GLITCH_2 (0x2 << 29) -#define START_SENSE (0x1 << 12) -#define TSC_DISABLE (0x1 << 16) +#define MEASURE_DELAY_TIME_MASK GENMASK(31, 8) +#define DETECT_5_WIRE_MODE BIT(4) +#define AUTO_MEASURE BIT(0) +#define MEASURE_SIGNAL BIT(0) +#define DETECT_SIGNAL BIT(4) +#define VALID_SIGNAL BIT(8) +#define MEASURE_INT_EN BIT(0) +#define MEASURE_SIG_EN BIT(0) +#define VALID_SIG_EN BIT(8) +#define DE_GLITCH_MASK GENMASK(30, 29) +#define DE_GLITCH_2 0x02 +#define START_SENSE BIT(12) +#define TSC_DISABLE BIT(16) #define DETECT_MODE 0x2 +#define STATE_MACHINE_MASK GENMASK(22, 20) =20 struct imx6ul_tsc { struct device *dev; @@ -112,19 +118,20 @@ static int imx6ul_adc_init(struct imx6ul_tsc *tsc) =20 adc_cfg =3D readl(tsc->adc_regs + REG_ADC_CFG); adc_cfg &=3D ~(ADC_CONV_MODE_MASK | ADC_INPUT_CLK_MASK); - adc_cfg |=3D ADC_12BIT_MODE | ADC_IPG_CLK; - adc_cfg &=3D ~(ADC_CLK_DIV_MASK | ADC_SAMPLE_MODE_MASK); - adc_cfg |=3D ADC_CLK_DIV_8 | ADC_SHORT_SAMPLE_MODE; + adc_cfg |=3D FIELD_PREP(ADC_CONV_MODE_MASK, ADC_12BIT_MODE) | + FIELD_PREP(ADC_INPUT_CLK_MASK, ADC_IPG_CLK); + adc_cfg &=3D ~(ADC_CLK_DIV_MASK | ADC_SAMPLE_MODE); + adc_cfg |=3D FIELD_PREP(ADC_CLK_DIV_MASK, ADC_CLK_DIV_8); if (tsc->average_enable) { adc_cfg &=3D ~ADC_AVGS_MASK; - adc_cfg |=3D (tsc->average_select) << ADC_AVGS_SHIFT; + adc_cfg |=3D FIELD_PREP(ADC_AVGS_MASK, tsc->average_select); } adc_cfg &=3D ~ADC_HARDWARE_TRIGGER; writel(adc_cfg, tsc->adc_regs + REG_ADC_CFG); =20 /* enable calibration interrupt */ adc_hc |=3D ADC_AIEN; - adc_hc |=3D ADC_CONV_DISABLE; + adc_hc |=3D FIELD_PREP(ADC_ADCH_MASK, ADC_CONV_DISABLE); writel(adc_hc, tsc->adc_regs + REG_ADC_HC0); =20 /* start ADC calibration */ @@ -164,19 +171,21 @@ static void imx6ul_tsc_channel_config(struct imx6ul_t= sc *tsc) { u32 adc_hc0, adc_hc1, adc_hc2, adc_hc3, adc_hc4; =20 - adc_hc0 =3D DISABLE_CONVERSION_INT; + adc_hc0 =3D FIELD_PREP(ADC_AIEN, 0); writel(adc_hc0, tsc->adc_regs + REG_ADC_HC0); =20 - adc_hc1 =3D DISABLE_CONVERSION_INT | SELECT_CHANNEL_4; + adc_hc1 =3D FIELD_PREP(ADC_AIEN, 0) | + FIELD_PREP(ADC_ADCH_MASK, SELECT_CHANNEL_4); writel(adc_hc1, tsc->adc_regs + REG_ADC_HC1); =20 - adc_hc2 =3D DISABLE_CONVERSION_INT; + adc_hc2 =3D FIELD_PREP(ADC_AIEN, 0); writel(adc_hc2, tsc->adc_regs + REG_ADC_HC2); =20 - adc_hc3 =3D DISABLE_CONVERSION_INT | SELECT_CHANNEL_1; + adc_hc3 =3D FIELD_PREP(ADC_AIEN, 0) | + FIELD_PREP(ADC_ADCH_MASK, SELECT_CHANNEL_1); writel(adc_hc3, tsc->adc_regs + REG_ADC_HC3); =20 - adc_hc4 =3D DISABLE_CONVERSION_INT; + adc_hc4 =3D FIELD_PREP(ADC_AIEN, 0); writel(adc_hc4, tsc->adc_regs + REG_ADC_HC4); } =20 @@ -188,13 +197,16 @@ static void imx6ul_tsc_channel_config(struct imx6ul_t= sc *tsc) static void imx6ul_tsc_set(struct imx6ul_tsc *tsc) { u32 basic_setting =3D 0; + u32 debug_mode2; u32 start; =20 - basic_setting |=3D tsc->measure_delay_time << 8; - basic_setting |=3D DETECT_4_WIRE_MODE | AUTO_MEASURE; + basic_setting |=3D FIELD_PREP(MEASURE_DELAY_TIME_MASK, + tsc->measure_delay_time); + basic_setting |=3D AUTO_MEASURE; writel(basic_setting, tsc->tsc_regs + REG_TSC_BASIC_SETTING); =20 - writel(DE_GLITCH_2, tsc->tsc_regs + REG_TSC_DEBUG_MODE2); + debug_mode2 =3D FIELD_PREP(DE_GLITCH_MASK, DE_GLITCH_2); + writel(debug_mode2, tsc->tsc_regs + REG_TSC_DEBUG_MODE2); =20 writel(tsc->pre_charge_time, tsc->tsc_regs + REG_TSC_PRE_CHARGE_TIME); writel(MEASURE_INT_EN, tsc->tsc_regs + REG_TSC_INT_EN); @@ -250,7 +262,7 @@ static bool tsc_wait_detect_mode(struct imx6ul_tsc *tsc) =20 usleep_range(200, 400); debug_mode2 =3D readl(tsc->tsc_regs + REG_TSC_DEBUG_MODE2); - state_machine =3D (debug_mode2 >> 20) & 0x7; + state_machine =3D FIELD_GET(STATE_MACHINE_MASK, debug_mode2); } while (state_machine !=3D DETECT_MODE); =20 usleep_range(200, 400); @@ -278,8 +290,8 @@ static irqreturn_t tsc_irq_fn(int irq, void *dev_id) =20 if (status & MEASURE_SIGNAL) { value =3D readl(tsc->tsc_regs + REG_TSC_MEASURE_VALUE); - x =3D (value >> 16) & 0x0fff; - y =3D value & 0x0fff; + x =3D FIELD_GET(X_VALUE_MASK, value); + y =3D FIELD_GET(Y_VALUE_MASK, value); =20 /* * In detect mode, we can get the xnur gpio value, --=20 2.43.0 From nobody Thu Oct 2 16:35:37 2025 Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CB1D635 for ; Sun, 14 Sep 2025 17:16:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757870184; cv=none; b=JLeSKmK6TBylcvD2FlLsr8huHO6j3GqRHFFs/1aPn8XTvaZ3NaoedLdO9/8rdSir0PuWlocmKC4sbVnD3y9o9mqyVrfVynby5hIuQDtDi6N64ONLnQYPod6CsXRcb74UY+sBW+YB1TNDCiSr/c8ZTTyXdxV93s5Od0uejrHyJI0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757870184; c=relaxed/simple; bh=Jy5vrJ90AiD6jtnSaZVQFAUaOXKIYVVwz21RLq/eHTc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=X87G33/U3RG3TAaXDMsZMZlhCN6mQgjpekCmwxU6u7+FW4dtHcXuw6SiOgANIORM0j0r95e285QrySioOj/GoDHMf0gaMnxEeuhu6QDe60yC4KfpR/JPrtpNlVry43yE40sUaaO/RjlRFVY6fpL2Op16fIpEM0Mnd8bbhPwwwKw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=BR8gfHcu; arc=none smtp.client-ip=209.85.218.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="BR8gfHcu" Received: by mail-ej1-f42.google.com with SMTP id a640c23a62f3a-b07dac96d1eso261606066b.1 for ; Sun, 14 Sep 2025 10:16:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1757870180; x=1758474980; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Sx0EwU0te/usZ13a8MurPgLe0A2g8omNenFnNxHAiqE=; b=BR8gfHcuRC32Q6eRp8toJOZf+lv58YU2GNNYSv6Oi+nbSLkourz+U0JSAXNA2kMsgH 4BWqzb9rrtCEHGr3d4dTLqfeBXhbZGW5dJ98jT/NTlu1B2eZn76YsWzWwtef+FbIHFOT MUzRx/Xc0PpGvjlowZMLLXrUPq82+h5cRmAJU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757870180; x=1758474980; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Sx0EwU0te/usZ13a8MurPgLe0A2g8omNenFnNxHAiqE=; b=cz/sREBEg++CuggqPJCnwAMf6LmnpqoactsvPX09C41duirDNty0k9FzGtITUGT0cY EINUkGuECOMR1z37s7gfKJjXb3VHQvz2gl1CEjfsyrLc0mJcRjhYeZrHCs/EZ8TUhKlw 4538Ls4v7/tAR4AjEI+M/KQzUj0UQqTU6ADyLZI3DhEfb4kD9nlkTcsOvsSSkFMBkghS ppAnJATQI/65ZGHn0NojDbVWYJ2k3lI9l81tYiCQKWVGrFWFut6lOEkJb8zqAOBWH5wG ykuir1OOH6Ud+rIVCRqpM+LFjqGXQUmlcPH4mtnHlsDg+bQc5R8TlamdNgKEv3CSeg9g JgKA== X-Gm-Message-State: AOJu0Ywz8w79rhXYTsrCKeX/hlc3vTV8TW6LKCK1ceAs0O1GMCY24UA8 2x41+vNoqQIFPpXpOi66+oxXPh4plIhnRJ+CwSIq+coN5uVnr7tPo9druaje8Jbiay4Dq24Ydd4 eU090 X-Gm-Gg: ASbGncsqb26EpHA1ZqPWRdDlsoNJH+/zwj9JQq0wpUcwXiI5iAJH0bg9g94g896Zvkt 1L4DvrnsXHICTKHKZGNXwDNi6dO4y4eVkUEwEOccWE92hS9ZEVPgeAI3UKj/ifEOHyiSy73E4nv ZPBQyybcIbfLDQjAAVczFTlvy/vOW7acgK2/uNnpnLtp3gzfkrDzCFOa2qRNlIztW1ham/+zdRc WbA9OZLdz+wrMvQ30+ZyosR3LslREL4typ/1206rriqReoTNiXc7WLLCKwbaTtFodM3x3ioDwYO VO7ySj4XscnYXe/w4G2u4cBp7z7+uQOuCJ0OHApWivT4r+hjfRvQ1Bl9EakgkVPsH9qryP068R2 L078JM5YJ+AWaVv8VepO8nOyH0t0Uat71qPU82//JzM/GuFkMm9/9WSgFwn6qFh2nKXRqDxZ2dS TkhMSdPSMdiB5jLeLJ4IsONl0aHFhbVQroU24wmbLbwfxlpQLiYCXT+kZxjl67MDTv/r2c/wp2g lA= X-Google-Smtp-Source: AGHT+IGg07tGI6gHsEGbzuf3VDSE6YFsTBt5Lon/+TCDORrB5jYkJHCYrktC1RHIPug9flWo1dwbuA== X-Received: by 2002:a17:907:d8b:b0:afe:8de8:290d with SMTP id a640c23a62f3a-b07a629945emr1504682966b.6.1757870179840; Sun, 14 Sep 2025 10:16:19 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-82-56-38-125.retail.telecomitalia.it. [82.56.38.125]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b07b334e76dsm776980466b.102.2025.09.14.10.16.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Sep 2025 10:16:19 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Frank Li , linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Dmitry Torokhov , Javier Carrasco , Jeff LaBundy , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-input@vger.kernel.org Subject: [PATCH v2 3/6] dt-bindings: touchscreen: add touchscreen-glitch-threshold-ns property Date: Sun, 14 Sep 2025 19:16:00 +0200 Message-ID: <20250914171608.1050401-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250914171608.1050401-1-dario.binacchi@amarulasolutions.com> References: <20250914171608.1050401-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for glitch threshold configuration. A detected signal is valid only if it lasts longer than the set threshold; otherwise, it is regarded as a glitch. Signed-off-by: Dario Binacchi --- Changes in v2: - Added in v2. .../devicetree/bindings/input/touchscreen/touchscreen.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/input/touchscreen/touchscree= n.yaml b/Documentation/devicetree/bindings/input/touchscreen/touchscreen.ya= ml index 3e3572aa483a..a60b4d08620d 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/touchscreen.yaml +++ b/Documentation/devicetree/bindings/input/touchscreen/touchscreen.yaml @@ -206,6 +206,10 @@ properties: =20 unevaluatedProperties: false =20 + touchscreen-glitch-threshold-ns: + description: Minimum duration in nanoseconds a signal must remain stab= le + to be considered valid. + dependencies: touchscreen-size-x: [ touchscreen-size-y ] touchscreen-size-y: [ touchscreen-size-x ] --=20 2.43.0 From nobody Thu Oct 2 16:35:37 2025 Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36C0E2DECAA for ; Sun, 14 Sep 2025 17:16:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757870185; cv=none; b=OSDadUjiPzDuWgYkBQa+BZRdC6C3FH2OuAwEIEotNMOTkZkLE8VAAg65Atmyxh73AyTAU5/eDDDu24QSi0tgzNbHZeVXp5CuWKdqR8y2nImBCQC5MH1fWpBIIN5xMnyjFZGs1YT3Hytw+nfujPrTTUavAWjdnJrLLhSWxPtHG5k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757870185; c=relaxed/simple; bh=RJXStlwzS4+/UQXUO3hnO45i3KP2svoFAvMb0SbrmwY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TwLOOaW0501Ip+aTxj0/NXbSZ7q72GAv6yUmOtyl2K4/I+22Cy96kHCtUIsNDFmtsHa7qLTVAYp7cFQnrjuDvjWmBe2dWJv71AjoSK8FUfvv/3YStyQ9A+/szQE1SwwGXgOm+RGb2iDJZpvBJjcMeBY8jr5tV/b70FPD9dJMrqA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=CF7mrgTM; arc=none smtp.client-ip=209.85.218.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="CF7mrgTM" Received: by mail-ej1-f48.google.com with SMTP id a640c23a62f3a-b0787fdb137so511049466b.0 for ; Sun, 14 Sep 2025 10:16:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1757870181; x=1758474981; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WMdgI0iZ2TvocV4JZ7DyZgorR1pQL3heQi0CeqfMARw=; b=CF7mrgTMDalZ3SCRHrEyOUgyTsYwPAy+4kpAHCl27Wnnrgm62ESOw4PGIK15JJy1g4 Yxv+FreXh0s7xbb99bAbtIXu+RG0Nq+ORO5LAVOfvhteDUojSKyeh1zYuI0kVGx39Qhr AnP3Fn65Nv0oGyGZWCMVB1fhA8XG2JRmO47AM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757870181; x=1758474981; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WMdgI0iZ2TvocV4JZ7DyZgorR1pQL3heQi0CeqfMARw=; b=R+D1jQtLfnoybkN3RUxBpW3S424wgirgGle0haUcZt/qZpydOt3zuzG2cXMU1GzMND IQgaNC3Ong9Wq55M9nu2yIVuv/HK906Orgs4k+bDp9fuC8LtndW/UQ90k7laOysXfmnr FJuO5QAzBkk5TKgqCFgE71iKxI7JGTuaOrw7BKwd8dEGeUZyhw1RvtBe76Gdo9qDMotM wcrg/86q7jqUjLyGiiHtv/CmRlkt7WFsIUkxtuYR0om8NQOWzPOz8SuKIsQ60ycheM6f r6RxBOHKfS8JdTNsBPq72sJB0O98t7BLZ4GStL80B3ZqD1zg3J6Fdk5UAOt+zDiqF8F4 7a2w== X-Gm-Message-State: AOJu0YyqmTLgob/cAZsS/P5ZbQLmqYvEG4MejmWqqtAszKsw3U4fORXB ehAOo9rtBGCt46Q40G+vfh2uSzh6cwz0/u5wdSDQ363hXOiOWhy0aB7CwU0oaGU9+TlCfQMmHZe CbUEK X-Gm-Gg: ASbGncuT4GsBKt9jmeWmuzMsVTbs8KKlxe7ohG1d3VfDoOODVdfEAxZMRPchefR5jmT R3g/DiyTKvwNy0Jn2llQWDttc55TZjCmCALQwftg1znj3TQEVzLIt/GLhl7yvJKulUBqgxKABCv TQYOWCYVX2KAAKIvQsiHczTlvh26nXn38RTB0cFKlGkLzr5zC/PNcPWWW2xxwncJ1v4doPkB6k5 sGB72JAcxmIhwEOCXqo2oe8bx/o4v+xT0lqgg3jc6fRHJ9Ca/ldMpvgZfTVmUxHUVTQN86agxwA 7JAsVDktcbxJqVfRfMhvFTOGpCyhZBcqeLQWeEw4cwHGwqhXLYYrRUFsGcR4dkH+G4Ub6HrOjd/ hB6NL0Lg82Yp2bVVugdB0p0CHe17fLz6Z5NeB31RVb55MtVlTUPH4h23ZbSLM6wpsZMNQ5lazbH X+kTtFs4FYG+gPpZ8vGyp8EsR8YbUGu03svZt2A/AJBugF92nsvl6+0b1NebCoRWoX X-Google-Smtp-Source: AGHT+IHfjFWKG/mF8+Rc9t6eyI85z35rKOGB32yV2tBXoq5uOjqdENe0BpELyw7Da4eiS0RVUPNPpw== X-Received: by 2002:a17:907:c08:b0:b04:3a46:c4f2 with SMTP id a640c23a62f3a-b07c383f1bemr990265066b.48.1757870181371; Sun, 14 Sep 2025 10:16:21 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-82-56-38-125.retail.telecomitalia.it. [82.56.38.125]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b07b334e76dsm776980466b.102.2025.09.14.10.16.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Sep 2025 10:16:21 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Frank Li , linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Dmitry Torokhov , Fabio Estevam , Haibo Chen , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org Subject: [PATCH v2 4/6] dt-bindings: touchscreen: fsl,imx6ul-tsc: support glitch thresold Date: Sun, 14 Sep 2025 19:16:01 +0200 Message-ID: <20250914171608.1050401-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250914171608.1050401-1-dario.binacchi@amarulasolutions.com> References: <20250914171608.1050401-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support the touchscreen-glitch-threshold-ns property. Unlike the generic description in touchscreen.yaml, this controller maps the provided value to one of four discrete thresholds internally. Signed-off-by: Dario Binacchi --- (no changes since v1) .../input/touchscreen/fsl,imx6ul-tsc.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/input/touchscreen/fsl,imx6ul= -tsc.yaml b/Documentation/devicetree/bindings/input/touchscreen/fsl,imx6ul-= tsc.yaml index 678756ad0f92..310af56a0be6 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/fsl,imx6ul-tsc.ya= ml +++ b/Documentation/devicetree/bindings/input/touchscreen/fsl,imx6ul-tsc.ya= ml @@ -62,6 +62,21 @@ properties: description: Number of data samples which are averaged for each read. enum: [ 1, 4, 8, 16, 32 ] =20 + touchscreen-glitch-threshold-ns: + description: | + Unlike the generic property defined in touchscreen.yaml, this + controller does not allow arbitrary values. Internally the value is + converted to IPG clock cycles and mapped to one of four discrete + thresholds exposed by the TSC_DEBUG_MODE2 register: + + 0: 8191 IPG cycles + 1: 4095 IPG cycles + 2: 2047 IPG cycles + 3: 1023 IPG cycles + + Any value provided in device tree is converted to cycles and rounded + up to the next supported threshold, or to 8191 if above 4095. + required: - compatible - reg --=20 2.43.0 From nobody Thu Oct 2 16:35:37 2025 Received: from mail-ed1-f43.google.com (mail-ed1-f43.google.com [209.85.208.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A17102DF123 for ; Sun, 14 Sep 2025 17:16:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757870186; cv=none; b=q6jaoYmC16YdAvhR5FgVG4/L4rqTNAyJcwuO3vU4aZfhreangFzkTx+o33NxsK/td9RCp2qi6Vm/txtdPzRGei6U/ITDt7mLTMWWH1GEUUghFv0jYmlnA/dRZGyL3Vr096HTb4Y1pW3UUS/JK5Td6FX8C3wIhXNn2m2FPjRHFa0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757870186; c=relaxed/simple; bh=7R8rcOL3f1HwsUpPHaL0+BUAREAOiXb98Mm1tlgtyCA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=nbUcrB6IYxY9VSxl78L4tsQEpaWkOFsM4TIPdPdA+7ArW+Z3hnORO7nLu+YeSFT1K4N5rXGlxe62NdvZwtdiOMcjCbnS3L6wVe7t6VHP+G/W6a5dZE4Xx2iGwYq68UftrrhjK1HxzJ10xD3vV3q1wnKs3K1/fIGRrZiunBtjH7Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=CZNKGi/I; arc=none smtp.client-ip=209.85.208.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="CZNKGi/I" Received: by mail-ed1-f43.google.com with SMTP id 4fb4d7f45d1cf-62f0411577aso2406796a12.1 for ; Sun, 14 Sep 2025 10:16:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1757870183; x=1758474983; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AJ9ovkCr6DqOwPekQL9mbbfb8pXGwCeM0TnyH7IdLxU=; b=CZNKGi/IHBMBaVws9rL4ax1ta6pLgauB7OVRZScLOr7GMmxwpF6Mn1vRQs0Y4e3wRZ BVnds2dTwTS6sB0cLZy0mZaUx1HvPMy+x+yVf/W9lifjneFWy3Wbo3E2tGVNdVrZcq4j PGJ2xZPqqs1iE7AD30ofJv2M3m1VmSVqQAGoM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757870183; x=1758474983; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AJ9ovkCr6DqOwPekQL9mbbfb8pXGwCeM0TnyH7IdLxU=; b=opbwcODFFganzvukRHmgT9V3CUWHeHja2+OLkcRoz+4JzD+DQKE05LjnvvbVxpe46g GR2IMYsWD6s2bChmrFP37Xa+yPFV4qVTUb13cNOGa38um8QqnUKK9DLyMHl+i5ePHHmV 4nCdNbVopVR8AUzwRaAL96pBE6X4P5xdzf1VjZOxJ4SJtuVePhIQv94kyopNnLHP5Yj3 5ayT835FHgowtQaZDMV+kBGRA1qiMkmGybnmjsoXuvkJiREZFGZlIyW2pTVRc8CENluK ZjKBAE6tX/04TDeJosNsfcvfTd6Yxiz+esfnBn3Unv2qVCZ0haN7koiJvU7oOGu8hBTN H0gw== X-Gm-Message-State: AOJu0YxYj6dqVmgn1I4a792/Jpqk/1yX6kGXD/8vzFd8xgIqVf+CPdcl FGecao8bhgD9Z4Vw4gKddZNqfEaicLKk0sNRSTApQA8Qpb5fQDaRSOeG7EEdzswk+kkhZiQxR14 EAlqd X-Gm-Gg: ASbGncuT6oFcHm0dBUOGdCEraEmOzF3E/plDTrcmCHuRBMBB3k2uO0BO8wPKYZvfW/U HInk50VVetjNw5ICXQzdexGReX3XcDaIIAqf71sCGBEJ+K/91KiTIVf9362HN3yCLScYuxKOqI8 LerULN5MlB7lspXbGXYbMhdnIyhq8iPw95/ez/w34sxKjI14KAWgJAdBN3hgwHLU1ehBAk77h4P jjaJONac4UiFf+ColuySkgREaTLh8YgT2zVmoagZCPDL4hs/we1hAmD90EKVY1D5GJXeoUU0f7z smmgT2kGdvSdITZQ9ix2/arPDKxV7SBAoKrB0mHugo+qRYq9DW96KRxauh0zxj5aX3ipBCrekCT f5NjP/uZ86HMpUuJFKJ/3ePlZJ5/YnMpsxaivuo6lN8IwjFbH+jKUd7vlI42XAxQIHWGjwM0/x6 Cb0dAJ5muBjLF5DnjBg038+NH3UqFQKk0iAh2QarLNC6ucJHFq8jeQvJk2qetboTQ4 X-Google-Smtp-Source: AGHT+IGvSuqYu1iID/ihliDiP5cWiNfNXKYVhuVRH/gmTXAOtDLlKa3rm5WJL/vzrHXGf7HRci4VUQ== X-Received: by 2002:a05:6402:1d51:b0:628:62d0:fdaa with SMTP id 4fb4d7f45d1cf-62ed82c5a2dmr9785589a12.23.1757870182851; Sun, 14 Sep 2025 10:16:22 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-82-56-38-125.retail.telecomitalia.it. [82.56.38.125]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b07b334e76dsm776980466b.102.2025.09.14.10.16.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Sep 2025 10:16:22 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Frank Li , linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 5/6] ARM: dts: imx6ull-engicam-microgea-bmm: set touchscreen glitch threshold Date: Sun, 14 Sep 2025 19:16:02 +0200 Message-ID: <20250914171608.1050401-6-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250914171608.1050401-1-dario.binacchi@amarulasolutions.com> References: <20250914171608.1050401-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable This way the detected signal is valid only if it lasts longer than 62 =C2=B5s, otherwise it is not sampled. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dts b/a= rch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dts index 279d46c22cd7..f12084d8f2a0 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-engicam-microgea-bmm.dts @@ -154,6 +154,7 @@ &tsc { pinctrl-0 =3D <&pinctrl_tsc>; measure-delay-time =3D <0x9ffff>; pre-charge-time =3D <0xfff>; + touchscreen-glitch-threshold-ns =3D <62000>; xnur-gpios =3D <&gpio1 3 GPIO_ACTIVE_LOW>; status =3D "okay"; }; --=20 2.43.0 From nobody Thu Oct 2 16:35:37 2025 Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20E762DF15E for ; Sun, 14 Sep 2025 17:16:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757870188; cv=none; b=u/82jKPSugKA8n7uNwkPVIPLdu6M523/bAiKhohUOf1EsM9uclH/c5Ck2rWf/LUA2NE3nWGInLqUwWR0dVDGQ97guUwslEMZd35oZE4FpnPLjgvvuFxEAtulIXCtxdgiQq0NwtS6vzYz5g68yc7dfwXQO7hc28QLa1YEuU5kVlI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757870188; c=relaxed/simple; bh=OV+qmjeU3NDC/Cst8F7wHNfjJbgMYyX+vlId2SAEZuc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=idnKfUKiPNrXq1GcBDtuTEV6osARta+qn3fut/HWbDeOqyMdgHhyQuKnUA5VxFiXUOsCBtDQ5G6VOYtVUFaRooehHTT+li1JfmPWt5k4vr7vbN2Y//XIZ8cxmCDTl+1dwKWH84LtF0ihj3qEG8q2xvXUenFvwzlXabrR5QFRcGU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=Z0skW9vB; arc=none smtp.client-ip=209.85.218.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="Z0skW9vB" Received: by mail-ej1-f53.google.com with SMTP id a640c23a62f3a-b0aaa7ea90fso140429166b.1 for ; Sun, 14 Sep 2025 10:16:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1757870184; x=1758474984; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VeIUZQnFQ6a6zAGoQDZv+bvlaQadCTCZH0QLhkeT9NE=; b=Z0skW9vBv0VTzA0nXahQ+hGdrEpjI4hEeWxnvprqm0sbqRkGZyWd9PpWC/7CKVOBnB /RFw0uEIPXlWaB6VPFr1MyRNsGM2EqwvAdfn2Q6I9dKMc+oQMSYmStmno8JHy7D/sI2b +Z3k3zfkKlMtQOLRIU3W3qnosqqZmP+Y30gXE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1757870184; x=1758474984; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VeIUZQnFQ6a6zAGoQDZv+bvlaQadCTCZH0QLhkeT9NE=; b=atq0Y+bUvJotS2HPs1+psqs8Y2GNMY5m+atFdh7ASh850DDQpxkTmPITWFYH2PxNc8 7KtGR49FUBJN/tRmRcd57wocY5eJmHwmifglCgRZ5QNsPA2UmrZ+Jzi7DyxtUk+3PP6d d7IGOYLzjEh89erjCcUf18/5Pu1DkcamAK8Bfbh4gA/oySInNP81ZkfOuxMTlishgNru xXG4U+RocPkuWEtbp1u9TuNcMYFmoHgJ3vLcs0amQTLHFcpQNjegYUM8RXj2A1KfoPZg 9LHLpB+cfgDEo2uD6MGfNLz4wJedoqYPVXv0x7oL7IO2ggb8WJa1hA5nyVjRVarIEog0 No7A== X-Gm-Message-State: AOJu0YxBkJx19LV7SytP+LjZfcnRUytbhOACm7CDTD1VDtzEPIqsadbl 4L7HCUnXSmQYjwkg2Uleqet4KkyC51ZOLQ1v+ht8pKyETsJ4VI3BzoYRatJCLQTrWztHhTZNxU+ AXKy/ X-Gm-Gg: ASbGncv0QZRriPMn+dYWrHLITbHlnJdyPOyBwsPNPIl79mdJSwCFctDQgyp2OpXuNVH kSW6I1JWp18XuIqf8n3HF9k6bB/vqbXy/cfu9L8N2oRrK99Y/NP6eEO0k7nb8MV385uWDVp3IvI WGfO2twPFadqje7WAqzAZeXJsRf7AZAUVE0JGs1vB6D3Ua88hqDHFm+7UYRwyaei8gQR6Fc+Q5o lXDZosZevdl+uuC5Z3oz34EAFn5oFMqCgTyaRm4VLzY3bsExJdPRiRx+aEg2v1hhJLOSpxB7EJU t7U/pV5uw1bRq45AyJ4/J5ZNGn378H/XyJyq/tug48k5kzzZDd8Ag6yYRoV8VwiEeYHr8AGy3Pm 30wkIe4ghGH3ZOg7NcYSOI4NAHU6pJR0UMUB6o8NDbp2RlQKtwmOh1+atCiw8rir3zhOlzy8pHV Ori8/XL04zZ4VlHWZ6yv1sQPS2dAhI4Yb2WL1eeeoW+nlh64mvDXAhcngRF/Zmi6Es X-Google-Smtp-Source: AGHT+IETORtFdx7V7/ajkoRQBW7LbAmBCbFNX2/FEUSZSUzDQGbJV03GOggXdksYhxvqH+4PusvMbA== X-Received: by 2002:a17:907:78b:b0:b10:aab8:3816 with SMTP id a640c23a62f3a-b10aab8432amr71331666b.32.1757870184256; Sun, 14 Sep 2025 10:16:24 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-82-56-38-125.retail.telecomitalia.it. [82.56.38.125]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b07b334e76dsm776980466b.102.2025.09.14.10.16.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Sep 2025 10:16:23 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Frank Li , linux-amarula@amarulasolutions.com, Dario Binacchi , Dmitry Torokhov , Fabio Estevam , Michael Trimarchi , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-input@vger.kernel.org Subject: [PATCH v2 6/6] Input: imx6ul_tsc - set glitch threshold by DTS property Date: Sun, 14 Sep 2025 19:16:03 +0200 Message-ID: <20250914171608.1050401-7-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250914171608.1050401-1-dario.binacchi@amarulasolutions.com> References: <20250914171608.1050401-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Set the glitch threshold previously hardcoded in the driver. The change is backward compatible. Signed-off-by: Dario Binacchi --- Changes in v2: - Replace patch ("dt-bindings: input: touchscreen: fsl,imx6ul-tsc: add fsl,glitch-threshold") with ("dt-bindings: touchscreen: add touchscreen-glitch-threshold-ns property"), making the previous property general by moving it to touchscreen.yaml. - Rework "Input: imx6ul_tsc - set glitch threshold by DTS property" patch to match changes made to the DTS property. - Move "Input: imx6ul_tsc - use BIT, FIELD_{GET,PREP} and GENMASK macros" patch right after the patch fixing the typo. - Rework to match changes made to the DTS property. drivers/input/touchscreen/imx6ul_tsc.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/input/touchscreen/imx6ul_tsc.c b/drivers/input/touchsc= reen/imx6ul_tsc.c index e2c59cc7c82c..0d753aa05fbf 100644 --- a/drivers/input/touchscreen/imx6ul_tsc.c +++ b/drivers/input/touchscreen/imx6ul_tsc.c @@ -79,7 +79,7 @@ #define MEASURE_SIG_EN BIT(0) #define VALID_SIG_EN BIT(8) #define DE_GLITCH_MASK GENMASK(30, 29) -#define DE_GLITCH_2 0x02 +#define DE_GLITCH_DEF 0x02 #define START_SENSE BIT(12) #define TSC_DISABLE BIT(16) #define DETECT_MODE 0x2 @@ -98,6 +98,7 @@ struct imx6ul_tsc { u32 pre_charge_time; bool average_enable; u32 average_select; + u32 de_glitch; =20 struct completion completion; }; @@ -205,7 +206,7 @@ static void imx6ul_tsc_set(struct imx6ul_tsc *tsc) basic_setting |=3D AUTO_MEASURE; writel(basic_setting, tsc->tsc_regs + REG_TSC_BASIC_SETTING); =20 - debug_mode2 =3D FIELD_PREP(DE_GLITCH_MASK, DE_GLITCH_2); + debug_mode2 =3D FIELD_PREP(DE_GLITCH_MASK, tsc->de_glitch); writel(debug_mode2, tsc->tsc_regs + REG_TSC_DEBUG_MODE2); =20 writel(tsc->pre_charge_time, tsc->tsc_regs + REG_TSC_PRE_CHARGE_TIME); @@ -391,6 +392,7 @@ static int imx6ul_tsc_probe(struct platform_device *pde= v) int tsc_irq; int adc_irq; u32 average_samples; + u32 de_glitch; =20 tsc =3D devm_kzalloc(&pdev->dev, sizeof(*tsc), GFP_KERNEL); if (!tsc) @@ -513,6 +515,26 @@ static int imx6ul_tsc_probe(struct platform_device *pd= ev) return -EINVAL; } =20 + err =3D of_property_read_u32(np, "touchscreen-glitch-threshold-ns", + &de_glitch); + if (err) { + tsc->de_glitch =3D DE_GLITCH_DEF; + } else { + u64 cycles; + unsigned long rate =3D clk_get_rate(tsc->tsc_clk); + + cycles =3D DIV64_U64_ROUND_UP((u64)de_glitch * rate, NSEC_PER_SEC); + + if (cycles <=3D 0x3ff) + tsc->de_glitch =3D 3; + else if (cycles <=3D 0x7ff) + tsc->de_glitch =3D 2; + else if (cycles <=3D 0xfff) + tsc->de_glitch =3D 1; + else + tsc->de_glitch =3D 0; + } + err =3D input_register_device(tsc->input); if (err) { dev_err(&pdev->dev, --=20 2.43.0