From nobody Thu Oct 2 16:35:38 2025 Received: from smtpbg154.qq.com (smtpbg154.qq.com [15.184.224.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA42F2D9EC5; Sun, 14 Sep 2025 15:57:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=15.184.224.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757865450; cv=none; b=Yx/1SU4fUZUYtru90pKZ+WyH+lNPO920kacpUTJPfl7p+F5YWZuREQwfHwskjwExIOdVe5wmJ4Xfc0//1XEo/n+cruoZ53W8Ejw7R5LvuNFkvxe8gBTjb/Sj61p1cFJLuvkE7bQK6vjKgQM6Uo+yE5uJPUS7I4inPG8KOyPLl34= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757865450; c=relaxed/simple; bh=+iv5zRGMLQo5WENFMbbcB6yHAuv5xbx2teATjhd7cMM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=p2F/KiNGljCnMiaWvgiUyVpLhbOJV4JUtJzpzHD/lJ3cyeQ04P0kVCXNpYkRPk+2xz0SJSBMSS5grSPSR/zR24rKcgkn6BWF8ZLL3G7BMdsfOFw0vneVQz/BwWuglvvjJm0X7BiT+GsizUVlR9pfB8XziLXVd7FSZYlvMtJ3IIA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=radxa.com; spf=pass smtp.mailfrom=radxa.com; arc=none smtp.client-ip=15.184.224.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=radxa.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=radxa.com X-QQ-mid: zesmtpip2t1757865431t0c66b8ab X-QQ-Originating-IP: S7nT+GMUYRpDXn7Z8+1Fwd49cQqEch6LdR1e2x1FIPg= Received: from [192.168.30.36] ( [localhost]) by bizesmtp.qq.com (ESMTP) with id ; Sun, 14 Sep 2025 23:57:10 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 2342445468012948641 EX-QQ-RecipientCnt: 13 From: Xilin Wu Date: Sun, 14 Sep 2025 23:57:04 +0800 Subject: [PATCH v2 1/5] dt-bindings: arm: qcom: Add Radxa Dragon Q6A Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250914-radxa-dragon-q6a-v2-1-045f7e92b3bb@radxa.com> References: <20250914-radxa-dragon-q6a-v2-0-045f7e92b3bb@radxa.com> In-Reply-To: <20250914-radxa-dragon-q6a-v2-0-045f7e92b3bb@radxa.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Viken Dadhaniya , Ram Kumar Dwivedi , Xilin Wu , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1757865427; l=921; i=sophon@radxa.com; s=20240424; h=from:subject:message-id; bh=+iv5zRGMLQo5WENFMbbcB6yHAuv5xbx2teATjhd7cMM=; b=lIBliRBEifCegCHHvAD3Ro5Lo7s+VC/wQ3Xd/SUpe+Yz2/Go5nVIGWfUbpC3sVa6K8cY9J4Nm onNzwi2QWyNDWBX2+bOY+GKV5rs6ZmEaOjODsQCuIqCBHS8zWlD6LKT X-Developer-Key: i=sophon@radxa.com; a=ed25519; pk=vPnxeJnlD/PfEbyQPZzaay5ezxI/lMrke7qXy31lSM8= X-QQ-SENDSIZE: 520 Feedback-ID: zesmtpip:radxa.com:qybglogicsvrgz:qybglogicsvrgz8a-1 X-QQ-XMAILINFO: NzSDQCFWCzVT6b19V2z28JcCDzIM/bv/KgvfEJI2ROevhotP0OOSRKin /F3U0jr4sO4Q9jVvI9HaiFQxAObmIMo32vPwuUEkPYzokyFf0YUqElpV4PkC8l3Jen88qnn OLnvQXOFBoVQv9e+JNK0w19Ks6057RjqRWAcB+xklUWxIF3918Q6G1CCMT6mS6/IiCnRGL6 tXx2iEc9zVnnoAteQJ3Ar6336Dd6JU3p+0oScKW2+EiCJliR6yf1pO4eG12CG8cjNKhSKMM vW4aJ3FSZl8q8TE06+5fTkCDSjrL06Vzg4YZ3q1m0EfNNTZoaHKdgVvMdyAlAiH2sGdax3Y X8+Rem5I+JWC6GAiqgXHTm0bGlFLcRHQlLmK0Q2/5jwYiWiUcjVmLfBLYnQNdHETlXnPhxb 5JchFy1TNjRDQ7cyj8hVCJPdRhqqn73AbtcKfFM7JqedssGl/Z4L152SAuipYsWsp86A0b7 s2EEAAfQpb1MPY0aVoxrdJOLRI7PxIcbQzzQcDpdAR/ft3iGKdIxteHQeY0b/UI0f6vZTOX vFmTi6aHWplcoms5rSD4KinXfphZGqimY7DCvOxsZD/nkZoDafn+CAHYqn12Y6ggdn1d1SJ wr9T/vk6w/wVxkXyX5f5Mt8c9luK87K2Uw/U9h4H1Gg5bM7dKWFIfXYLnQrFZRDk9lo6iBN R/ctP/8F2/9WW9lt2hZtpe680A5L2/COHCxterkf4gaerFEfwDELdukC4DAMBNQkjv+OYTX 62V9ArnaAQ9/bagnewRwHeVtfXT+MHazMmVPbIwRCJxk+jBADr5cLxU+nXkOfqMYj/EG24z 2Xlj572NPYapa5ZZBSaKkgv2eRod3E5Ba7wVGe/MqJpbaiuLrX0S7UD+t/KvPAXKoVgBTKj uiqGUvLHrvCDisQ8Plm9UUj3FhqPKnfZDDeqaw8NPnlxT3pmRYMnF0WZeBD7tKq2fTzxTZT MZ+BgTy/q/vhoIwx3HQHBDokaPrFATZG6YaAEEuQAlBsmMitu0aSLjsgu X-QQ-XMRINFO: Nq+8W0+stu50PRdwbJxPCL0= X-QQ-RECHKSPAM: 0 Radxa Dragon Q6A is a single board computer, based on the Qualcomm QCS6490 platform. Document the top-level compatible for this board. Acked-by: Krzysztof Kozlowski Signed-off-by: Xilin Wu --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index 0a3222d6f3686f1647b9e2ea192c175b0b96d48a..a7469a51adf0d6ebc1bf25acce8= f125a844dcdbf 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -339,6 +339,7 @@ properties: - fairphone,fp5 - qcom,qcm6490-idp - qcom,qcs6490-rb3gen2 + - radxa,dragon-q6a - shift,otter - const: qcom,qcm6490 =20 --=20 2.51.0 From nobody Thu Oct 2 16:35:38 2025 Received: from smtpbgsg1.qq.com (smtpbgsg1.qq.com [54.254.200.92]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A508C2C3749; Sun, 14 Sep 2025 15:57:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.254.200.92 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757865448; cv=none; b=uvsAj0TuJaPsq0WLxKLhT1szWcZ0zv4UbFtoZB1/qd1AVaNkLR38awuViYdyWI1BqtWsbUo8EQdOIiBnC39PJEoLfvwht6Nfs0Cab0srnRwkQJbmMn7o47bl63sy4Xdv1mjfP3R5OF6tVg+7WzQYsWSv+rg/gnwqQS/686LvLq0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757865448; c=relaxed/simple; bh=EyV9C0+0WM0VMHB0uqhnvaW2gLMbaOhAX6zDA2IFQcs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Tf0bS1QXSLElL3UOeMuWJnI+oS6sRNwUHL9m5EhCwZGQZddiZKaxf+51jaPy/rkWozqYJr4l8yvt3at3YYhHltD7D+PCNu5mnTjsSPQku+ddNvk+LOxaUnyE6EDLz1aqvNGxghEtRb93L8U4iZ0mmzhkZvC7r7DF2digoZcRyNo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=radxa.com; spf=pass smtp.mailfrom=radxa.com; arc=none smtp.client-ip=54.254.200.92 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=radxa.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=radxa.com X-QQ-mid: zesmtpip2t1757865434t6cca6a1f X-QQ-Originating-IP: 0zWBNPtMkVR2aGLW0Ko+jXO7q/UUhaVf0JMLEceT2sE= Received: from [192.168.30.36] ( [localhost]) by bizesmtp.qq.com (ESMTP) with id ; Sun, 14 Sep 2025 23:57:12 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 12141690102200628095 EX-QQ-RecipientCnt: 13 From: Xilin Wu Date: Sun, 14 Sep 2025 23:57:05 +0800 Subject: [PATCH v2 2/5] arm64: dts: qcom: qcs6490: Introduce Radxa Dragon Q6A Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250914-radxa-dragon-q6a-v2-2-045f7e92b3bb@radxa.com> References: <20250914-radxa-dragon-q6a-v2-0-045f7e92b3bb@radxa.com> In-Reply-To: <20250914-radxa-dragon-q6a-v2-0-045f7e92b3bb@radxa.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Viken Dadhaniya , Ram Kumar Dwivedi , Xilin Wu , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1757865427; l=24400; i=sophon@radxa.com; s=20240424; h=from:subject:message-id; bh=EyV9C0+0WM0VMHB0uqhnvaW2gLMbaOhAX6zDA2IFQcs=; b=B3H3cfvvA7RRyKsC9CeAGLRkgCG+Oxnl5JtUbRgHuPYbqocl0/XFOqn9vdQOH4Ku9lOtMD4eK yVyRBN56CxTBvigLbnmZp5k57AyVyyUioZX73YOw8NTxhF57ia1jRAE X-Developer-Key: i=sophon@radxa.com; a=ed25519; pk=vPnxeJnlD/PfEbyQPZzaay5ezxI/lMrke7qXy31lSM8= X-QQ-SENDSIZE: 520 Feedback-ID: zesmtpip:radxa.com:qybglogicsvrgz:qybglogicsvrgz8a-1 X-QQ-XMAILINFO: MjlOSqg8Riw02UKMqyYyRqPxnDQarGv3eCrez/b4RcugoFZKUlqP9PbG Wyii/z05Ty5OwXjHOjGmvECc9h52ndepTpvyPV9TRu6NE53aBcl82OU2tsEX1jJyUCqcEf/ 7EVroOxTkh4oj2xIj83ljrKeFbXv6ikPuZtor7c4QbaulYy4BJTFFzUxZ4HXRZ70urc2C6g X2p+c+/MoJ31KUl2dFf1w0lMQBSD8ncR5KvEw4BHFsYC4bfEDITfAESoRPVQcT2DVWj14/2 Z6hN1RimC/dE5PX1IlUGbIFpmtpq8FRscBrSqpSflSsjt3JiwGMR8jjooVkNiYQQlXwEkOL cRAzCcpFYZrmdoTZA57oiWqLnE1stGuv1EhHZ/O7964sh0Mc6WzPHQ5/UoxlZsPz5NPKamA gk3Vg8UmWG6EY3TEdHzdjIEYkCfSOgy2mmsH+5Rn20M361QANDOpVtyG6qOdbb9oPiG4TAi LNUskgByOoJZN9EGiAfipvj7uiKtI7CSnPWOTLKy+D2S36BzOe+xmZJO7b9ynLVVZOQftA0 8HuBYCEpjT5qEk4o+XgW6m7WrwUMXpNR/WSO7ojF5zGmLlGRSH49TCiepJ+8iC0MB8GSSQO GhXxawBvHJSGwExA0Ti08f90g6+Rpw4vVy88Z+qC6PaTlMowtL1chQtGq6hy+L5VzPGpZ/G xRw4+OyEm2qc9HXPVeeFGHER36BglfYvbrgxt0TkK1PHENLapxwnKX5FbQ0vWP7h7Fne87t g6JuGTPCvTnec7KHb+2MbSSJsLFsfIwqetWa8Edfcz4EQ5yEeRY3EKcEFp9Tf4AUfeJDwUt auNgoP6ebzK2RKGny2K/alIU2OQQAz/UZ40mPQDG3ESe34uRrF5KNwjUdKNoB2Qn20K8Tdv xuYCAV6De9oAAqMNq9SwB/uNG6po87HVYbqui+iQJhkoKj3my4TrPBVzz4bD/jp+AlPHmEY wdXy11oaMVXCm6Amz1NiQUbtU7RV6+ImjZcdFDMrSgkdzj+KCOxeWaaR+ZxPzQba0Lh8= X-QQ-XMRINFO: NS+P29fieYNw95Bth2bWPxk= X-QQ-RECHKSPAM: 0 Radxa Dragon Q6A is a single board computer, based on the Qualcomm QCS6490 platform. Features enabled and working: - Three USB-A 2.0 ports - RTL8111K Ethernet connected to PCIe0 - eMMC module - SD card - M.2 M-Key 2230 PCIe 3.0 x2 - Headphone jack - Onboard thermal sensors - QSPI controller for updating boot firmware - ADSP remoteproc (Type-C and charging features disabled in firmware) - CDSP remoteproc (for AI applications using QNN) - Venus video encode and decode accelerator Reviewed-by: Krzysztof Kozlowski Signed-off-by: Xilin Wu --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 961 +++++++++++++++++= ++++ 2 files changed, 962 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 5b52f9e4e5f31ac5a398d0762337a0a31af1f4dd..3a246adb0c435d7b08dda404ed2= bcb2a9c8c48b0 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -120,6 +120,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D qcm6490-shift-otter.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs615-ride.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D qcs6490-radxa-dragon-q6a.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs6490-rb3gen2.dtb =20 qcs6490-rb3gen2-vision-mezzanine-dtbs :=3D qcs6490-rb3gen2.dtb qcs6490-rb3= gen2-vision-mezzanine.dtbo diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/a= rm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts new file mode 100644 index 0000000000000000000000000000000000000000..85465702279efb7ab324baea066= 3bdbdbd5fb5ac --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts @@ -0,0 +1,961 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025 Radxa Computer (Shenzhen) Co., Ltd. + */ + +/dts-v1/; + +/* PM7250B is configured to use SID8/9 */ +#define PM7250B_SID 8 +#define PM7250B_SID1 9 + +#include +#include +#include +#include +#include +#include "sc7280.dtsi" +#include "pm7250b.dtsi" +#include "pm7325.dtsi" +#include "pm8350c.dtsi" /* PM7350C */ +#include "pmk8350.dtsi" /* PMK7325 */ +#include "qcs6490-audioreach.dtsi" + +/delete-node/ &adsp_mem; +/delete-node/ &cdsp_mem; +/delete-node/ &ipa_fw_mem; +/delete-node/ &mpss_mem; +/delete-node/ &remoteproc_mpss; +/delete-node/ &remoteproc_wpss; +/delete-node/ &rmtfs_mem; +/delete-node/ &video_mem; +/delete-node/ &wifi; +/delete-node/ &wlan_ce_mem; +/delete-node/ &wlan_fw_mem; +/delete-node/ &wpss_mem; +/delete-node/ &xbl_mem; + +/ { + model =3D "Radxa Dragon Q6A"; + compatible =3D "radxa,dragon-q6a", "qcom,qcm6490"; + chassis-type =3D "embedded"; + + aliases { + mmc0 =3D &sdhc_1; + mmc1 =3D &sdhc_2; + serial0 =3D &uart5; + }; + + wcd938x: audio-codec { + compatible =3D "qcom,wcd9380-codec"; + + pinctrl-0 =3D <&wcd_default>; + pinctrl-names =3D "default"; + + reset-gpios =3D <&tlmm 83 GPIO_ACTIVE_LOW>; + + vdd-rxtx-supply =3D <&vreg_l18b_1p8>; + vdd-io-supply =3D <&vreg_l18b_1p8>; + vdd-buck-supply =3D <&vreg_l17b_1p8>; + vdd-mic-bias-supply =3D <&vreg_bob_3p296>; + + qcom,micbias1-microvolt =3D <1800000>; + qcom,micbias2-microvolt =3D <1800000>; + qcom,micbias3-microvolt =3D <1800000>; + qcom,micbias4-microvolt =3D <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt =3D <75000 150000 237000 500000 5= 00000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt =3D <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt =3D <50000>; + qcom,rx-device =3D <&wcd_rx>; + qcom,tx-device =3D <&wcd_tx>; + + qcom,hphl-jack-type-normally-closed; + + #sound-dai-cells =3D <1>; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + leds { + compatible =3D "gpio-leds"; + + pinctrl-0 =3D <&user_led>; + pinctrl-names =3D "default"; + + user-led { + color =3D ; + function =3D LED_FUNCTION_HEARTBEAT; + gpios =3D <&tlmm 42 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "heartbeat"; + }; + }; + + reserved-memory { + xbl_mem: xbl@80700000 { + reg =3D <0x0 0x80700000 0x0 0x100000>; + no-map; + }; + + cdsp_secure_heap_mem: cdsp-secure-heap@81800000 { + reg =3D <0x0 0x81800000 0x0 0x1e00000>; + no-map; + }; + + camera_mem: camera@84300000 { + reg =3D <0x0 0x84300000 0x0 0x500000>; + no-map; + }; + + adsp_mem: adsp@84800000 { + reg =3D <0x0 0x84800000 0x0 0x2800000>; + no-map; + }; + + cdsp_mem: cdsp@87000000 { + reg =3D <0x0 0x87000000 0x0 0x1e00000>; + no-map; + }; + + video_mem: video@88e00000 { + reg =3D <0x0 0x88e00000 0x0 0x700000>; + no-map; + }; + + cvp_mem: cvp@89500000 { + reg =3D <0x0 0x89500000 0x0 0x500000>; + no-map; + }; + + gpu_microcode_mem: gpu-microcode@89a00000 { + reg =3D <0x0 0x89a00000 0x0 0x2000>; + no-map; + }; + + tz_stat_mem: tz-stat@c0000000 { + reg =3D <0x0 0xc0000000 0x0 0x100000>; + no-map; + }; + + tags_mem: tags@c0100000 { + reg =3D <0x0 0xc0100000 0x0 0x1200000>; + no-map; + }; + + qtee_mem: qtee@c1300000 { + reg =3D <0x0 0xc1300000 0x0 0x500000>; + no-map; + }; + + trusted_apps_mem: trusted-apps@c1800000 { + reg =3D <0x0 0xc1800000 0x0 0x1c00000>; + no-map; + }; + + debug_vm_mem: debug-vm@d0600000 { + reg =3D <0x0 0xd0600000 0x0 0x100000>; + no-map; + }; + }; + + thermal-zones { + msm-skin-thermal { + polling-delay-passive =3D <0>; + thermal-sensors =3D <&pmk8350_adc_tm 2>; + }; + + quiet-thermal { + polling-delay-passive =3D <0>; + thermal-sensors =3D <&pmk8350_adc_tm 1>; + }; + + ufs-thermal { + polling-delay-passive =3D <0>; + thermal-sensors =3D <&pmk8350_adc_tm 3>; + }; + + xo-thermal { + polling-delay-passive =3D <0>; + thermal-sensors =3D <&pmk8350_adc_tm 0>; + }; + }; + + vcc_1v8: regulator-vcc-1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&vcc_5v_peri>; + + regulator-boot-on; + regulator-always-on; + }; + + vcc_3v3: regulator-vcc-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc_5v_peri>; + + regulator-boot-on; + regulator-always-on; + }; + + vcc_5v_peri: regulator-vcc-5v-peri { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_5v_peri"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vph_pwr>; + + regulator-boot-on; + regulator-always-on; + }; + + vph_pwr: regulator-vph-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + + regulator-boot-on; + regulator-always-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pm7325-rpmh-regulators"; + qcom,pmic-id =3D "b"; + + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + vdd-s6-supply =3D <&vph_pwr>; + vdd-s7-supply =3D <&vph_pwr>; + vdd-s8-supply =3D <&vph_pwr>; + vdd-l1-l4-l12-l15-supply =3D <&vreg_s7b_0p536>; + vdd-l2-l7-supply =3D <&vreg_bob_3p296>; + vdd-l3-supply =3D <&vreg_s2b_0p572>; + vdd-l5-supply =3D <&vreg_s2b_0p572>; + vdd-l6-l9-l10-supply =3D <&vreg_s8b_1p2>; + vdd-l8-supply =3D <&vreg_s7b_0p536>; + vdd-l11-l17-l18-l19-supply =3D <&vreg_s1b_1p84>; + vdd-l13-supply =3D <&vreg_s7b_0p536>; + vdd-l14-l16-supply =3D <&vreg_s8b_1p2>; + + vreg_s1b_1p84: smps1 { + regulator-name =3D "vreg_s1b_1p84"; + regulator-min-microvolt =3D <1840000>; + regulator-max-microvolt =3D <2040000>; + }; + + vreg_s2b_0p572: smps2 { + regulator-name =3D "vreg_s2b_0p572"; + regulator-min-microvolt =3D <572000>; + regulator-max-microvolt =3D <1048000>; + }; + + vreg_s7b_0p536: smps7 { + regulator-name =3D "vreg_s7b_0p536"; + regulator-min-microvolt =3D <536000>; + regulator-max-microvolt =3D <1120000>; + }; + + vreg_s8b_1p2: smps8 { + regulator-name =3D "vreg_s8b_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1496000>; + regulator-initial-mode =3D ; + }; + + vreg_l1b_0p912: ldo1 { + regulator-name =3D "vreg_l1b_0p912"; + regulator-min-microvolt =3D <832000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2b_3p072: ldo2 { + regulator-name =3D "vreg_l2b_3p072"; + regulator-min-microvolt =3D <2704000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l6b_1p2: ldo6 { + regulator-name =3D "vreg_l6b_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1256000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7b_2p96: ldo7 { + regulator-name =3D "vreg_l7b_2p96"; + regulator-min-microvolt =3D <2960000>; + regulator-max-microvolt =3D <2960000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l9b_1p2: ldo9 { + regulator-name =3D "vreg_l9b_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1304000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l17b_1p8: ldo17 { + regulator-name =3D "vreg_l17b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1896000>; + regulator-initial-mode =3D ; + }; + + vreg_l18b_1p8: ldo18 { + regulator-name =3D "vreg_l18b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + regulator-always-on; + }; + + vreg_l19b_1p8: ldo19 { + regulator-name =3D "vreg_l19b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pm8350c-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + vdd-s6-supply =3D <&vph_pwr>; + vdd-s7-supply =3D <&vph_pwr>; + vdd-s8-supply =3D <&vph_pwr>; + vdd-s9-supply =3D <&vph_pwr>; + vdd-s10-supply =3D <&vph_pwr>; + vdd-l1-l12-supply =3D <&vreg_s1b_1p84>; + vdd-l2-l8-supply =3D <&vreg_s1b_1p84>; + vdd-l3-l4-l5-l7-l13-supply =3D <&vreg_bob_3p296>; + vdd-l6-l9-l11-supply =3D <&vreg_bob_3p296>; + vdd-l10-supply =3D <&vreg_s7b_0p536>; + vdd-bob-supply =3D <&vph_pwr>; + + vreg_l1c_1p8: ldo1 { + regulator-name =3D "vreg_l1c_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1976000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l6c_2p96: ldo6 { + regulator-name =3D "vreg_l6c_2p96"; + regulator-min-microvolt =3D <1650000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l9c_2p96: ldo9 { + regulator-name =3D "vreg_l9c_2p96"; + regulator-min-microvolt =3D <2704000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l10c_0p88: ldo10 { + regulator-name =3D "vreg_l10c_0p88"; + regulator-min-microvolt =3D <720000>; + regulator-max-microvolt =3D <1048000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_bob_3p296: bob { + regulator-name =3D "vreg_bob_3p296"; + regulator-min-microvolt =3D <3032000>; + regulator-max-microvolt =3D <3960000>; + }; + }; +}; + +&gcc { + protected-clocks =3D , + , + , + , + , + , + , + , + , + , + ; +}; + +&gpu { + status =3D "okay"; +}; + +&gpu_zap_shader { + firmware-name =3D "qcom/qcs6490/a660_zap.mbn"; +}; + +&lpass_audiocc { + compatible =3D "qcom,qcm6490-lpassaudiocc"; + /delete-property/ power-domains; +}; + +&lpass_rx_macro { + status =3D "okay"; +}; + +&lpass_tx_macro { + status =3D "okay"; +}; + +&lpass_va_macro { + status =3D "okay"; +}; + +&pcie0 { + perst-gpios =3D <&tlmm 87 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 89 GPIO_ACTIVE_HIGH>; + + pinctrl-0 =3D <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie0_phy { + vdda-phy-supply =3D <&vreg_l10c_0p88>; + vdda-pll-supply =3D <&vreg_l6b_1p2>; + + status =3D "okay"; +}; + +&pcie1 { + perst-gpios =3D <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 3 GPIO_ACTIVE_HIGH>; + + pinctrl-0 =3D <&pcie1_clkreq_n>, <&pcie1_reset_n>, <&pcie1_wake_n>; + pinctrl-names =3D "default"; + + /* Support for QPS615 PCIe switch */ + iommu-map =3D <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>, + <0x208 &apps_smmu 0x1c84 0x1>, + <0x210 &apps_smmu 0x1c85 0x1>, + <0x218 &apps_smmu 0x1c86 0x1>, + <0x300 &apps_smmu 0x1c87 0x1>, + <0x400 &apps_smmu 0x1c88 0x1>, + <0x500 &apps_smmu 0x1c89 0x1>, + <0x501 &apps_smmu 0x1c90 0x1>; + + status =3D "okay"; +}; + +&pcie1_phy { + vdda-phy-supply =3D <&vreg_l10c_0p88>; + vdda-pll-supply =3D <&vreg_l6b_1p2>; + + status =3D "okay"; +}; + +&pm7325_gpios { + pm7325_adc_default: adc-default-state { + pins =3D "gpio2"; + function =3D PMIC_GPIO_FUNC_NORMAL; + bias-high-impedance; + }; +}; + +&pm7325_temp_alarm { + io-channels =3D <&pmk8350_vadc PM7325_ADC7_DIE_TEMP>; + io-channel-names =3D "thermal"; +}; + +&pmk8350_adc_tm { + status =3D "okay"; + + xo-therm@0 { + reg =3D <0>; + io-channels =3D <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us =3D <200>; + }; + + quiet-therm@1 { + reg =3D <1>; + io-channels =3D <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us =3D <200>; + }; + + msm-skin-therm@2 { + reg =3D <2>; + io-channels =3D <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us =3D <200>; + }; + + ufs-therm@3 { + reg =3D <3>; + io-channels =3D <&pmk8350_vadc PM7325_ADC7_GPIO1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us =3D <200>; + }; +}; + +&pmk8350_vadc { + pinctrl-0 =3D <&pm7325_adc_default>; + pinctrl-names =3D "default"; + + channel@3 { + reg =3D ; + label =3D "pmk7325_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@44 { + reg =3D ; + label =3D "xo_therm"; + qcom,hw-settle-time =3D <200>; + qcom,pre-scaling =3D <1 1>; + qcom,ratiometric; + }; + + channel@103 { + reg =3D ; + label =3D "pm7325_die_temp"; + qcom,pre-scaling =3D <1 1>; + }; + + channel@144 { + reg =3D ; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,pre-scaling =3D <1 1>; + label =3D "quiet_therm"; + }; + + channel@146 { + reg =3D ; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,pre-scaling =3D <1 1>; + label =3D "msm_skin_therm"; + }; + + channel@14a { + /* According to datasheet, 0x4a =3D AMUX1_GPIO =3D GPIO_02 */ + reg =3D ; + qcom,ratiometric; + qcom,hw-settle-time =3D <200>; + qcom,pre-scaling =3D <1 1>; + label =3D "ufs_therm"; + }; +}; + +&pon_pwrkey { + status =3D "okay"; +}; + +&qspi { + /* It's not possible to use QSPI with iommu */ + /* due to an error in qcom_smmu_write_s2cr */ + /delete-property/ iommus; + + pinctrl-0 =3D <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, + <&qspi_data1>, <&qspi_data23>; + pinctrl-1 =3D <&qspi_sleep>; + pinctrl-names =3D "default", "sleep"; + + status =3D "okay"; + + spi_flash: flash@0 { + compatible =3D "winbond,w25q256", "jedec,spi-nor"; + reg =3D <0>; + + spi-max-frequency =3D <104000000>; + spi-tx-bus-width =3D <4>; + spi-rx-bus-width =3D <4>; + }; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/qcs6490/radxa/dragon-q6a/adsp.mbn"; + status =3D "okay"; +}; + +&remoteproc_cdsp { + firmware-name =3D "qcom/qcs6490/radxa/dragon-q6a/cdsp.mbn"; + status =3D "okay"; +}; + +&sdhc_1 { + non-removable; + no-sd; + no-sdio; + + vmmc-supply =3D <&vreg_l7b_2p96>; + vqmmc-supply =3D <&vreg_l19b_1p8>; + + status =3D "okay"; +}; + +&sdhc_2 { + pinctrl-0 =3D <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>, <&sd_cd>; + pinctrl-1 =3D <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>, <= &sd_cd>; + + vmmc-supply =3D <&vreg_l9c_2p96>; + vqmmc-supply =3D <&vreg_l6c_2p96>; + + cd-gpios =3D <&tlmm 91 GPIO_ACTIVE_LOW>; + status =3D "okay"; +}; + +&sound { + compatible =3D "qcom,qcs6490-rb3gen2-sndcard"; + model =3D "QCS6490-Radxa-Dragon-Q6A"; + + audio-routing =3D + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "TX SWR_ADC1", "ADC2_OUTPUT"; + + wcd-playback-dai-link { + link-name =3D "WCD Playback"; + + codec { + sound-dai =3D <&wcd938x 0>, <&swr0 0>, <&lpass_rx_macro 0>; + }; + + cpu { + sound-dai =3D <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name =3D "WCD Capture"; + + codec { + sound-dai =3D <&wcd938x 1>, <&swr1 0>, <&lpass_tx_macro 0>; + }; + + cpu { + sound-dai =3D <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; +}; + +&swr0 { + status =3D "okay"; + + wcd_rx: codec@0,4 { + compatible =3D "sdw20217010d00"; + reg =3D <0 4>; + qcom,rx-port-mapping =3D <1 2 3 4 5>; + }; +}; + +&swr1 { + status =3D "okay"; + + wcd_tx: codec@0,3 { + compatible =3D "sdw20217010d00"; + reg =3D <0 3>; + qcom,tx-port-mapping =3D <1 1 2 3>; + }; +}; + +&tlmm { + gpio-line-names =3D + /* GPIO_0 ~ GPIO_3 */ + "PIN_13", "PIN_15", "", "", + /* GPIO_4 ~ GPIO_7 */ + "", "", "", "", + /* GPIO_8 ~ GPIO_11 */ + "PIN_27", "PIN_28", "", "", + /* GPIO_12 ~ GPIO_15 */ + "", "", "", "", + /* GPIO_16 ~ GPIO_19 */ + "", "", "", "", + /* GPIO_20 ~ GPIO_23 */ + "", "", "PIN_8", "PIN_10", + /* GPIO_24 ~ GPIO_27 */ + "PIN_3", "PIN_5", "PIN_16", "PIN_27", + /* GPIO_28 ~ GPIO_31 */ + "PIN_31", "PIN_11", "PIN_32", "PIN_29", + /* GPIO_32 ~ GPIO_35 */ + "", "", "", "", + /* GPIO_36 ~ GPIO_39 */ + "", "", "", "", + /* GPIO_40 ~ GPIO_43 */ + "", "", "", "", + /* GPIO_44 ~ GPIO_47 */ + "", "", "", "", + /* GPIO_48 ~ GPIO_51 */ + "PIN_21", "PIN_19", "PIN_23", "PIN_24", + /* GPIO_52 ~ GPIO_55 */ + "", "", "", "PIN_26", + /* GPIO_56 ~ GPIO_59 */ + "PIN_33", "PIN_22", "PIN_37", "PIN_36", + /* GPIO_60 ~ GPIO_63 */ + "", "", "", "", + /* GPIO_64 ~ GPIO_67 */ + "", "", "", "", + /* GPIO_68 ~ GPIO_71 */ + "", "", "", "", + /* GPIO_72 ~ GPIO_75 */ + "", "", "", "", + /* GPIO_76 ~ GPIO_79 */ + "", "", "", "", + /* GPIO_80 ~ GPIO_83 */ + "", "", "", "", + /* GPIO_84 ~ GPIO_87 */ + "", "", "", "", + /* GPIO_88 ~ GPIO_91 */ + "", "", "", "", + /* GPIO_92 ~ GPIO_95 */ + "", "", "", "", + /* GPIO_96 ~ GPIO_99 */ + "PIN_7", "PIN_12", "PIN_38", "PIN_40", + /* GPIO_100 ~ GPIO_103 */ + "PIN_35", "", "", "", + /* GPIO_104 ~ GPIO_107 */ + "", "", "", "", + /* GPIO_108 ~ GPIO_111 */ + "", "", "", "", + /* GPIO_112 ~ GPIO_115 */ + "", "", "", "", + /* GPIO_116 ~ GPIO_119 */ + "", "", "", "", + /* GPIO_120 ~ GPIO_123 */ + "", "", "", "", + /* GPIO_124 ~ GPIO_127 */ + "", "", "", "", + /* GPIO_128 ~ GPIO_131 */ + "", "", "", "", + /* GPIO_132 ~ GPIO_135 */ + "", "", "", "", + /* GPIO_136 ~ GPIO_139 */ + "", "", "", "", + /* GPIO_140 ~ GPIO_143 */ + "", "", "", "", + /* GPIO_144 ~ GPIO_147 */ + "", "", "", "", + /* GPIO_148 ~ GPIO_151 */ + "", "", "", "", + /* GPIO_152 ~ GPIO_155 */ + "", "", "", "", + /* GPIO_156 ~ GPIO_159 */ + "", "", "", "", + /* GPIO_160 ~ GPIO_163 */ + "", "", "", "", + /* GPIO_164 ~ GPIO_167 */ + "", "", "", "", + /* GPIO_168 ~ GPIO_171 */ + "", "", "", "", + /* GPIO_172 ~ GPIO_174 */ + "", "", ""; + + pcie0_reset_n: pcie0-reset-n-state { + pins =3D "gpio87"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + pcie0_wake_n: pcie0-wake-n-state { + pins =3D "gpio89"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + pcie1_reset_n: pcie1-reset-n-state { + pins =3D "gpio2"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + pcie1_wake_n: pcie1-wake-n-state { + pins =3D "gpio3"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qspi_sleep: qspi-sleep-state { + pins =3D "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17"; + function =3D "gpio"; + output-disable; + }; + + sd_cd: sd-cd-state { + pins =3D "gpio91"; + function =3D "gpio"; + bias-pull-up; + }; + + user_led: user-led-state { + pins =3D "gpio42"; + function =3D "gpio"; + bias-pull-up; + }; + + wcd_default: wcd-reset-n-active-state { + pins =3D "gpio83"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + output-low; + }; +}; + +&uart5 { + status =3D "okay"; +}; + +&usb_2 { + dr_mode =3D "host"; + + status =3D "okay"; +}; + +&usb_2_hsphy { + status =3D "okay"; + + vdda-pll-supply =3D <&vreg_l10c_0p88>; + vdda33-supply =3D <&vreg_l2b_3p072>; + vdda18-supply =3D <&vreg_l1c_1p8>; +}; + +&venus { + status =3D "okay"; +}; + +/* PINCTRL - additions to nodes defined in sc7280.dtsi */ +&pcie0_clkreq_n { + bias-pull-up; + drive-strength =3D <2>; +}; + +&pcie1_clkreq_n { + bias-pull-up; + drive-strength =3D <2>; +}; + +&qspi_clk { + bias-disable; + drive-strength =3D <16>; +}; + +&qspi_cs0 { + bias-disable; + drive-strength =3D <8>; +}; + +&qspi_data0 { + bias-disable; + drive-strength =3D <8>; +}; + +&qspi_data1 { + bias-disable; + drive-strength =3D <8>; +}; + +&qspi_data23 { + bias-disable; + drive-strength =3D <8>; +}; + +&sdc1_clk { + bias-disable; + drive-strength =3D <16>; +}; + +&sdc1_cmd { + bias-pull-up; + drive-strength =3D <10>; +}; + +&sdc1_data { + bias-pull-up; + drive-strength =3D <10>; +}; + +&sdc1_rclk { + bias-pull-down; +}; + +&sdc2_clk { + bias-disable; + drive-strength =3D <16>; +}; + +&sdc2_cmd { + bias-pull-up; + drive-strength =3D <10>; +}; + +&sdc2_data { + bias-pull-up; + drive-strength =3D <10>; +}; --=20 2.51.0 From nobody Thu Oct 2 16:35:38 2025 Received: from smtpbguseast1.qq.com (smtpbguseast1.qq.com [54.204.34.129]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFC692D9EC7 for ; Sun, 14 Sep 2025 15:57:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.204.34.129 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757865450; cv=none; b=jE6HL2apQeC4KbVMZkZyltpo71wxmRtoRseDZeWVJgtoZ1Se2LmPRPpeLfgYzT20CC0LsLgKUezTgFvbLTGxTuw/XnKmdkgO//s9u6GE5nZfSqo3rZdRUQNI+0nocXKCdzVryFYIxWzkE7LyTp4nBLD6XzOBAjQFUVa/1L/SpUo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757865450; c=relaxed/simple; bh=1V85CMmb+/2qUjFLnDfCZdknLQA+oopxoMSIenFyMe8=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250914-radxa-dragon-q6a-v2-3-045f7e92b3bb@radxa.com> References: <20250914-radxa-dragon-q6a-v2-0-045f7e92b3bb@radxa.com> In-Reply-To: <20250914-radxa-dragon-q6a-v2-0-045f7e92b3bb@radxa.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Viken Dadhaniya , Ram Kumar Dwivedi , Xilin Wu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1757865427; l=2330; i=sophon@radxa.com; s=20240424; h=from:subject:message-id; bh=1V85CMmb+/2qUjFLnDfCZdknLQA+oopxoMSIenFyMe8=; b=TuFr0pwF+lxMqslNRC/5jwCyurLqwTBpmtsP9Cr0xeR6dCj+txxmdR3drRAjStdz2sTCkJRiw iG2Gz8jHapiDZh7r05lbakuRs7cAdbYdWyMPCbu+H6ndn0x0HGCKIMU X-Developer-Key: i=sophon@radxa.com; a=ed25519; pk=vPnxeJnlD/PfEbyQPZzaay5ezxI/lMrke7qXy31lSM8= X-QQ-SENDSIZE: 520 Feedback-ID: zesmtpip:radxa.com:qybglogicsvrgz:qybglogicsvrgz8a-1 X-QQ-XMAILINFO: OQDnMK6ucigbOsVUkPafzjTw4D1SAUl+vBEygNYkBqa3J4jX896aWgBJ 8VMR9P5ddfUToFaya/h35hMVlu0zdVYYvqyADke45wnzZbuo6i1HWmWa2z9fKFRwOsDhy3s Fj1Eq/vSIJp0MxSyXa1uHEaStHU7/dgIkGG9zbvVrnYf2e4AUAGQNp+UJJpq6C6T5JNOEmP bNU21zsRdXoLenRXG1AEp+iPOLLRKOh1Mmoj7ruyJuuKnGeRU/3DscOs/sO8d12EGiC6j/t aTAvzPdWp2p4uuhoXo7JLM1VXu1+hgi7tk/giU0henFYj+7OtFgelsMTkseB89Dkn9UV6rS uSWrS15nXxvjoffSrUN7/6Q6uiROg4BpGYA/RSpxOQDIIoplrwoY9D+X/dO9GX/T9yEcDEU McUHI7KnGUWvoQLBdgw4D56+eWRk9Ea/nIHf2fo/t9Sk4V/IjVzSPpS7w8EzB1aJDAP1YaK mh7ElldcfkTEoFd3qoL8QJA9ZI1xM2RdJvy6gYVlEX5OVvrTvLf7YvsDsffasUI6zDrHbQw 2tuAn7BxvC2HFevTTsYXXRc51CCO+oEpBPR5CTVvN0UKKypZhMm8c2Yd4CWoCZe7twznEKx ZcnXfDGNFG783Q/+WzLq6ynvjZRSQcbYk/rs44LhuP4HjVT1DKTGaNU60wVO0pato2u42dK /REt1nfDIvLjmkMadgpQE9Dzf9338QoGd1JrikESqWzCv3IX/wo4tJaXMzUIsUhrfnxTsrV uaUE+1zHMsFxY07Jf9PC6nGUdyoPoMGiy49BugZrmrk0S1b8kn8NT9srawflBtkTndaH43f FYDxJl3ar5XS/kK6aQAx7irZd2NUtWT0AiczRI4JIfUMzL1KMGUSQuH4iRq570eT3V0QKHb I6f7i+wjRJDo5OchZjmoZYW1itNL4r+fk79hdy/q4WYSNnD2D9v6z4L0Qn4c1eeTDGV0hK0 YeHMHAd0i8nL6bVai6dapwf4DnOark2q/wD1WEoYs/IF7g2J59FSk+VjZB+aw+3wP6KQJ3+ JUT4N2kI3a52I5CbsPVCwiyurW9pFCVVgs1S6A+4fBhSjk8IBfd4ZlWsK9fK4= X-QQ-XMRINFO: MSVp+SPm3vtS1Vd6Y4Mggwc= X-QQ-RECHKSPAM: 0 Add and enable all available QUP SEs on this board, allowing I2C, SPI and UART functions from the 40-Pin GPIO header to work. Signed-off-by: Xilin Wu --- This change depends on the following patch series: https://lore.kernel.org/all/20250911043256.3523057-1-viken.dadhaniya@oss.qu= alcomm.com/ --- .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 66 ++++++++++++++++++= ++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/a= rm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts index 85465702279efb7ab324baea0663bdbdbd5fb5ac..d30cddfc3eff07237c7e3480a5d= 42b29091d87d6 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts @@ -432,6 +432,14 @@ &gcc { ; }; =20 +&gpi_dma0 { + status =3D "okay"; +}; + +&gpi_dma1 { + status =3D "okay"; +}; + &gpu { status =3D "okay"; }; @@ -440,6 +448,40 @@ &gpu_zap_shader { firmware-name =3D "qcom/qcs6490/a660_zap.mbn"; }; =20 +/* Pin 13, 15 in GPIO header */ +&i2c0 { + qcom,enable-gsi-dma; + status =3D "okay"; +}; + +/* Pin 27, 28 in GPIO header */ +&i2c2 { + qcom,enable-gsi-dma; + status =3D "okay"; +}; + +/* Pin 3, 5 in GPIO header */ +&i2c6 { + qcom,enable-gsi-dma; + status =3D "okay"; +}; + +&i2c10 { + qcom,enable-gsi-dma; + status =3D "okay"; + + rtc: rtc@68 { + compatible =3D "st,m41t11"; + reg =3D <0x68>; + }; +}; + +/* External touchscreen */ +&i2c13 { + qcom,enable-gsi-dma; + status =3D "okay"; +}; + &lpass_audiocc { compatible =3D "qcom,qcm6490-lpassaudiocc"; /delete-property/ power-domains; @@ -624,6 +666,12 @@ spi_flash: flash@0 { }; =20 &qupv3_id_0 { + firmware-name =3D "qcom/qcm6490/qupv3fw.elf"; + status =3D "okay"; +}; + +&qupv3_id_1 { + firmware-name =3D "qcom/qcm6490/qupv3fw.elf"; status =3D "okay"; }; =20 @@ -702,6 +750,24 @@ platform { }; }; =20 +/* Pin 11, 29, 31, 32 in GPIO header */ +&spi7 { + qcom,enable-gsi-dma; + status =3D "okay"; +}; + +/* Pin 19, 21, 23, 24, 26 in GPIO header */ +&spi12 { + qcom,enable-gsi-dma; + status =3D "okay"; +}; + +/* Pin 22, 33, 36, 37 in GPIO header */ +&spi14 { + qcom,enable-gsi-dma; + status =3D "okay"; +}; + &swr0 { status =3D "okay"; =20 --=20 2.51.0 From nobody Thu Oct 2 16:35:38 2025 Received: from smtpbguseast2.qq.com (smtpbguseast2.qq.com [54.204.34.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BBB32DCBF3 for ; Sun, 14 Sep 2025 15:57:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.204.34.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757865452; cv=none; b=EJmOwlxnu0AC06jL2CDzY+0qvCiGPECqapF00DNf6HSVkXBsjt0RSCOfwyzIuvnVht+DLz220ccIH1MAH/g9D/GLivXdwOz3lB9YkpeBYfXRDoMABBNRZwITzFojp407dI3mJ+FLpphazJ4LmxMPxO5Vm5N3yW+I/NydHNKD9TA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757865452; c=relaxed/simple; bh=EiMdQ56FSpoh+jezouVccupggQusRUgVW7KiFFuQ6YU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sdZo9JWHjhVQRjy1aYUnWu3IighHfXk4ZLawiqRvFlNPPjtNlOSgfEq2NajfUBvFsl3MrgLmVx0cAwLo1glv4TyUSxbkT8060xcmv70BzfT3Orj7UXrAlA9BI8+yXZiyaEIpepyohq3pR3isa+cNgPnt1iCzr0oOznbIUtsFKuw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=radxa.com; spf=pass smtp.mailfrom=radxa.com; arc=none smtp.client-ip=54.204.34.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=radxa.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=radxa.com X-QQ-mid: zesmtpip2t1757865439t8f0c438a X-QQ-Originating-IP: pLxyR+EOCK0wlpAMNCC3ZcyEEqs9dXvj/pHWXxrhJUc= Received: from [192.168.30.36] ( [localhost]) by bizesmtp.qq.com (ESMTP) with id ; Sun, 14 Sep 2025 23:57:17 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 11041455606322930672 EX-QQ-RecipientCnt: 12 From: Xilin Wu Date: Sun, 14 Sep 2025 23:57:07 +0800 Subject: [PATCH DNM v2 4/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable UFS controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250914-radxa-dragon-q6a-v2-4-045f7e92b3bb@radxa.com> References: <20250914-radxa-dragon-q6a-v2-0-045f7e92b3bb@radxa.com> In-Reply-To: <20250914-radxa-dragon-q6a-v2-0-045f7e92b3bb@radxa.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Viken Dadhaniya , Ram Kumar Dwivedi , Xilin Wu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Note that UFS Gear-4 Rate-B is unstable due to board and UFS module design limitations. UFS on this board is stable when working at Gear-4 Rate-A. Signed-off-by: Xilin Wu --- This change depends on the following patch series: https://lore.kernel.org/all/20250902164900.21685-1-quic_rdwivedi@quicinc.co= m/ --- .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 29 ++++++++++++++++++= ++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/a= rm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts index d30cddfc3eff07237c7e3480a5d42b29091d87d6..3bf85d68c97891db1f1f0b84fb5= 649803948e06f 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts @@ -482,6 +482,11 @@ &i2c13 { status =3D "okay"; }; =20 +/* It takes a long time in ufshcd_init_crypto when enabled */ +&ice { + status =3D "disabled"; +}; + &lpass_audiocc { compatible =3D "qcom,qcm6490-lpassaudiocc"; /delete-property/ power-domains; @@ -938,6 +943,30 @@ &uart5 { status =3D "okay"; }; =20 +&ufs_mem_hc { + reset-gpios =3D <&tlmm 175 GPIO_ACTIVE_LOW>; + vcc-supply =3D <&vreg_l7b_2p96>; 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Sun, 14 Sep 2025 23:57:20 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 11909047073940114166 EX-QQ-RecipientCnt: 12 From: Xilin Wu Date: Sun, 14 Sep 2025 23:57:08 +0800 Subject: [PATCH DNM v2 5/5] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable USB 3.0 and HDMI ports Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250914-radxa-dragon-q6a-v2-5-045f7e92b3bb@radxa.com> References: <20250914-radxa-dragon-q6a-v2-0-045f7e92b3bb@radxa.com> In-Reply-To: <20250914-radxa-dragon-q6a-v2-0-045f7e92b3bb@radxa.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Viken Dadhaniya , Ram Kumar Dwivedi , Xilin Wu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1757865427; l=4169; i=sophon@radxa.com; s=20240424; h=from:subject:message-id; bh=+hcwblRIBuQ+J9Yk8H60awXsSZXJkpOUptbXJftZtOQ=; b=siCeStVnL8gXcVL0AicvXdoc3c1XwFNtfzOSwSc0lPIEUMPgA/NGguQeVNQ7DrsV/pCn06Sx8 pDlq35z4XUYCNhI9SToIbpmQdj/4wxBeCRBFX8Hp7bI8F+ngLAy3Jjn X-Developer-Key: i=sophon@radxa.com; a=ed25519; pk=vPnxeJnlD/PfEbyQPZzaay5ezxI/lMrke7qXy31lSM8= X-QQ-SENDSIZE: 520 Feedback-ID: zesmtpip:radxa.com:qybglogicsvrgz:qybglogicsvrgz8a-1 X-QQ-XMAILINFO: NDyJFjRsJu3snF/xX8KzmrBgXsDrQrFYJRWJ7Ba8m+3lSe2MeikYKUam FWjjzL0wGrYKc71ymqXPRLOZpJJYoq+Vv0jVoCMuib51DH3eUNDp9SJFdOXmoZOz58FN7bj JBU3a11TrXwlZmiYG9AjfxfgWfTbxX7wJTHmbgAIfRJJaqHAxVabkTh8oBED1DCYHuNlNJN wKzatmvbGUiUoww47DLrBwVTN1l4IUSvCLrK1C/QbpCkVJPtEXLRJkuFlNoDJ0BRu/nmCWY qq19arEL6dJEu11xTykfHi2u8/zbeaW/Hzok9flyXM2C+GMznw1ZurQwrTNakc3j3I7aLm9 f0TCqWzTrlwfn6yPsRjBwN1GQFGxqc0vCISQs/bNOS+P+jI3+MAtpp+J4uZ9CdZgA4UW0nP KbhsM5HQT4mLn/uz/4rfdhfqbp3kcL+YvAgfHLS7iG1lA2rqGFwM40eUG5nTEhle4trf+ch hk9Awv/TxeGYhsOfaudJWuB6ciYYDWkh2ZMHiSa9UWO7lDcEYyLY4rLq0J1qL2TocwY1JBe sOxtmhyAfkLb+ymDd803QolVoV8LOnkK5VZ/H96V5Mk/2FiJwGmCzIO13NTd7CiMv4KHwiP SI/AG2yue6aRjWO7TTxXCkGtUtGSELMtAGaGq+AjwjH1RIXqPj2j14skFka3/whlnXFLI1w Pf2xwGZ7F+tvpzxZMcCv8SUQlsn6tMow9tCCRkgqkYHI/0aq/2I33TJ/oFp/rdQEA76o66d WnezUQjr2moW1fmXbnG72/QcrryJc1r5OG8eKwU2XB7nSgyMTZur8Pw7oYNaRKHhwNg5g6y CaI9MEJypE9veujGhChLFZMTyghAy7M/hewhCpRr/X0fwsCVQbaVhR7egeHb9usx9qoc/tm dezGYXLiyWThx9OmbhmVMuSses3aXC6Vrkap681H2DPveEhUZXFN5tDNKLlOraUWQYApgvn uSio2myhozfbYowpn0oJBI7QrDdpeRS5ziIixITE7pAjJG+1sRsM3OCcDVJS3A40KYiZRuA uj5/q48ElX6GPhx0v1VtrR+0YI3OcJtzyu0J+HjDY+SbHzOf8bTZwN18LuQ7i/sYlQmLGDU g== X-QQ-XMRINFO: OD9hHCdaPRBwq3WW+NvGbIU= X-QQ-RECHKSPAM: 0 This board doesn't feature a regular Type-C port. The usb_1_qmpphy's RX1/TX1 pair is statically connected to the USB-A port, while its RX0/TX0 pair is connected to the RA620 DP-to-HDMI bridge. Add and enable the nodes for the features to work. Signed-off-by: Xilin Wu --- This change depends on the following patch series: https://lore.kernel.org/all/20250908-topic-x1e80100-hdmi-v3-4-c53b0f2bc2fb@= linaro.org/ --- .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 152 +++++++++++++++++= ++++ 1 file changed, 152 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/a= rm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts index 3bf85d68c97891db1f1f0b84fb5649803948e06f..12bc9a0fcfbfeaabf6ede351f96= c61193a8261c0 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts @@ -78,6 +78,71 @@ chosen { stdout-path =3D "serial0:115200n8"; }; =20 + usb3_con: connector { + compatible =3D "usb-a-connector"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb3_con_hs_in: endpoint { + remote-endpoint =3D <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg =3D <1>; + + usb3_con_ss_in: endpoint { + remote-endpoint =3D <&usb_dp_qmpphy_out_usb>; + }; + }; + }; + }; + + hdmi-bridge { + compatible =3D "radxa,ra620"; + + pinctrl-0 =3D <&dp_hot_plug_det>; + pinctrl-names =3D "default"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + hdmi_bridge_in: endpoint { + remote-endpoint =3D <&usb_dp_qmpphy_out_dp>; + }; + }; + + port@1 { + reg =3D <1>; + + hdmi_bridge_out: endpoint { + remote-endpoint =3D <&hdmi_connector_in>; + }; + }; + }; + }; + + hdmi-connector { + compatible =3D "hdmi-connector"; + label =3D "hdmi"; + type =3D "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint =3D <&hdmi_bridge_out>; + }; + }; + }; + leds { compatible =3D "gpio-leds"; =20 @@ -504,6 +569,21 @@ &lpass_va_macro { status =3D "okay"; }; =20 +&mdss { + status =3D "okay"; +}; + +&mdss_dp { + sound-name-prefix =3D "Display Port0"; + + status =3D "okay"; +}; + +&mdss_dp_out { + data-lanes =3D <0 1>; + remote-endpoint =3D <&usb_dp_qmpphy_dp_in>; +}; + &pcie0 { perst-gpios =3D <&tlmm 87 GPIO_ACTIVE_LOW>; wake-gpios =3D <&tlmm 89 GPIO_ACTIVE_HIGH>; @@ -753,6 +833,22 @@ platform { sound-dai =3D <&q6apm>; }; }; + + dp0-dai-link { + link-name =3D "DP0 Playback"; + + codec { + sound-dai =3D <&mdss_dp>; + }; + + cpu { + sound-dai =3D <&q6apmbedai DISPLAY_PORT_RX_0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; }; =20 /* Pin 11, 29, 31, 32 in GPIO header */ @@ -967,6 +1063,58 @@ &ufs_mem_phy { status =3D "okay"; }; =20 +&usb_1 { + dr_mode =3D "host"; + + status =3D "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint =3D <&usb3_con_hs_in>; +}; + +&usb_1_hsphy { + vdda-pll-supply =3D <&vreg_l10c_0p88>; + vdda33-supply =3D <&vreg_l2b_3p072>; + vdda18-supply =3D <&vreg_l1c_1p8>; + + status =3D "okay"; +}; + +&usb_1_qmpphy { + vdda-phy-supply =3D <&vreg_l6b_1p2>; + vdda-pll-supply =3D <&vreg_l1b_0p912>; + + /delete-property/ orientation-switch; + + status =3D "okay"; + + ports { + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /delete-node/ endpoint; + + /* RX1/TX1 is statically connected to USB-A port */ + usb_dp_qmpphy_out_usb: endpoint@0 { + reg =3D <0>; + + data-lanes =3D <2 3>; + remote-endpoint =3D <&usb3_con_ss_in>; + }; + + /* RX0/TX0 is statically connected to RA620 bridge */ + usb_dp_qmpphy_out_dp: endpoint@1 { + reg =3D <1>; + + data-lanes =3D <3 2>; + remote-endpoint =3D <&hdmi_bridge_in>; + }; + }; + }; +}; + &usb_2 { dr_mode =3D "host"; =20 @@ -986,6 +1134,10 @@ &venus { }; =20 /* PINCTRL - additions to nodes defined in sc7280.dtsi */ +&dp_hot_plug_det { + bias-disable; +}; + &pcie0_clkreq_n { bias-pull-up; drive-strength =3D <2>; --=20 2.51.0